viaide.c revision 1.71
1 /* $NetBSD: viaide.c,v 1.71 2010/11/06 01:24:55 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.71 2010/11/06 01:24:55 jakllsch Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/pci/pciide_apollo_reg.h> 39 40 static int via_pcib_match(struct pci_attach_args *); 41 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 42 static void via_mapchan(struct pci_attach_args *, struct pciide_channel *, 43 pcireg_t, int (*)(void *)); 44 static void via_mapregs_compat_native(struct pci_attach_args *, 45 struct pciide_channel *); 46 static int via_sata_chip_map_common(struct pciide_softc *, 47 struct pci_attach_args *); 48 static void via_sata_chip_map(struct pciide_softc *, 49 struct pci_attach_args *, int); 50 static void via_sata_chip_map_6(struct pciide_softc *, 51 struct pci_attach_args *); 52 static void via_sata_chip_map_7(struct pciide_softc *, 53 struct pci_attach_args *); 54 static void via_sata_chip_map_new(struct pciide_softc *, 55 struct pci_attach_args *); 56 static void via_setup_channel(struct ata_channel *); 57 58 static int viaide_match(device_t, cfdata_t, void *); 59 static void viaide_attach(device_t, device_t, void *); 60 static const struct pciide_product_desc * 61 viaide_lookup(pcireg_t); 62 static bool viaide_suspend(device_t, const pmf_qual_t *); 63 static bool viaide_resume(device_t, const pmf_qual_t *); 64 65 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 66 viaide_match, viaide_attach, pciide_detach, NULL); 67 68 static const struct pciide_product_desc pciide_amd_products[] = { 69 { PCI_PRODUCT_AMD_PBC756_IDE, 70 0, 71 "AMD AMD756 IDE Controller", 72 via_chip_map 73 }, 74 { PCI_PRODUCT_AMD_PBC766_IDE, 75 0, 76 "AMD AMD766 IDE Controller", 77 via_chip_map 78 }, 79 { PCI_PRODUCT_AMD_PBC768_IDE, 80 0, 81 "AMD AMD768 IDE Controller", 82 via_chip_map 83 }, 84 { PCI_PRODUCT_AMD_PBC8111_IDE, 85 0, 86 "AMD AMD8111 IDE Controller", 87 via_chip_map 88 }, 89 { PCI_PRODUCT_AMD_CS5536_IDE, 90 0, 91 "AMD CS5536 IDE Controller", 92 via_chip_map 93 }, 94 { 0, 95 0, 96 NULL, 97 NULL 98 } 99 }; 100 101 static const struct pciide_product_desc pciide_nvidia_products[] = { 102 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 103 0, 104 "NVIDIA nForce IDE Controller", 105 via_chip_map 106 }, 107 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 108 0, 109 "NVIDIA nForce2 IDE Controller", 110 via_chip_map 111 }, 112 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 113 0, 114 "NVIDIA nForce2 Ultra 400 IDE Controller", 115 via_chip_map 116 }, 117 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 118 0, 119 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 120 via_sata_chip_map_6 121 }, 122 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 123 0, 124 "NVIDIA nForce3 IDE Controller", 125 via_chip_map 126 }, 127 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 128 0, 129 "NVIDIA nForce3 250 IDE Controller", 130 via_chip_map 131 }, 132 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 133 0, 134 "NVIDIA nForce3 250 Serial ATA Controller", 135 via_sata_chip_map_6 136 }, 137 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 138 0, 139 "NVIDIA nForce3 250 Serial ATA Controller", 140 via_sata_chip_map_6 141 }, 142 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 143 0, 144 "NVIDIA nForce4 IDE Controller", 145 via_chip_map 146 }, 147 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 148 0, 149 "NVIDIA nForce4 Serial ATA Controller", 150 via_sata_chip_map_6 151 }, 152 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 153 0, 154 "NVIDIA nForce4 Serial ATA Controller", 155 via_sata_chip_map_6 156 }, 157 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 158 0, 159 "NVIDIA nForce430 IDE Controller", 160 via_chip_map 161 }, 162 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 163 0, 164 "NVIDIA nForce430 Serial ATA Controller", 165 via_sata_chip_map_6 166 }, 167 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 168 0, 169 "NVIDIA nForce430 Serial ATA Controller", 170 via_sata_chip_map_6 171 }, 172 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 173 0, 174 "NVIDIA MCP04 IDE Controller", 175 via_chip_map 176 }, 177 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 178 0, 179 "NVIDIA MCP04 Serial ATA Controller", 180 via_sata_chip_map_6 181 }, 182 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 183 0, 184 "NVIDIA MCP04 Serial ATA Controller", 185 via_sata_chip_map_6 186 }, 187 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 188 0, 189 "NVIDIA MCP55 IDE Controller", 190 via_chip_map 191 }, 192 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 193 0, 194 "NVIDIA MCP55 Serial ATA Controller", 195 via_sata_chip_map_6 196 }, 197 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 198 0, 199 "NVIDIA MCP55 Serial ATA Controller", 200 via_sata_chip_map_6 201 }, 202 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 203 0, 204 "NVIDIA MCP61 IDE Controller", 205 via_chip_map 206 }, 207 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 208 0, 209 "NVIDIA MCP65 IDE Controller", 210 via_chip_map 211 }, 212 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 213 0, 214 "NVIDIA MCP73 IDE Controller", 215 via_chip_map 216 }, 217 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 218 0, 219 "NVIDIA MCP77 IDE Controller", 220 via_chip_map 221 }, 222 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 223 0, 224 "NVIDIA MCP61 Serial ATA Controller", 225 via_sata_chip_map_6 226 }, 227 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 228 0, 229 "NVIDIA MCP61 Serial ATA Controller", 230 via_sata_chip_map_6 231 }, 232 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 233 0, 234 "NVIDIA MCP61 Serial ATA Controller", 235 via_sata_chip_map_6 236 }, 237 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 238 0, 239 "NVIDIA MCP65 Serial ATA Controller", 240 via_sata_chip_map_6 241 }, 242 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 243 0, 244 "NVIDIA MCP65 Serial ATA Controller", 245 via_sata_chip_map_6 246 }, 247 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 248 0, 249 "NVIDIA MCP65 Serial ATA Controller", 250 via_sata_chip_map_6 251 }, 252 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 253 0, 254 "NVIDIA MCP65 Serial ATA Controller", 255 via_sata_chip_map_6 256 }, 257 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 258 0, 259 "NVIDIA MCP67 IDE Controller", 260 via_chip_map, 261 }, 262 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 263 0, 264 "NVIDIA MCP67 Serial ATA Controller", 265 via_sata_chip_map_6, 266 }, 267 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 268 0, 269 "NVIDIA MCP67 Serial ATA Controller", 270 via_sata_chip_map_6, 271 }, 272 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 273 0, 274 "NVIDIA MCP67 Serial ATA Controller", 275 via_sata_chip_map_6, 276 }, 277 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 278 0, 279 "NVIDIA MCP67 Serial ATA Controller", 280 via_sata_chip_map_6, 281 }, 282 { 0, 283 0, 284 NULL, 285 NULL 286 } 287 }; 288 289 static const struct pciide_product_desc pciide_via_products[] = { 290 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 291 0, 292 NULL, 293 via_chip_map, 294 }, 295 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 296 0, 297 NULL, 298 via_chip_map, 299 }, 300 { PCI_PRODUCT_VIATECH_CX700_IDE, 301 0, 302 NULL, 303 via_chip_map, 304 }, 305 { PCI_PRODUCT_VIATECH_CX700M2_IDE, 306 0, 307 NULL, 308 via_chip_map, 309 }, 310 { PCI_PRODUCT_VIATECH_VT6421_RAID, 311 0, 312 "VIA Technologies VT6421 Serial RAID Controller", 313 via_sata_chip_map_new, 314 }, 315 { PCI_PRODUCT_VIATECH_VT8237_SATA, 316 0, 317 "VIA Technologies VT8237 SATA Controller", 318 via_sata_chip_map_7, 319 }, 320 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 321 0, 322 "VIA Technologies VT8237A SATA Controller", 323 via_sata_chip_map_7, 324 }, 325 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, 326 0, 327 "VIA Technologies VT8237A (5337) SATA Controller", 328 via_sata_chip_map_7, 329 }, 330 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 331 0, 332 "VIA Technologies VT8237R SATA Controller", 333 via_sata_chip_map_7, 334 }, 335 { PCI_PRODUCT_VIATECH_VT8237S_SATA, 336 0, 337 "VIA Technologies VT8237S SATA Controller", 338 via_sata_chip_map_7, 339 }, 340 { 0, 341 0, 342 NULL, 343 NULL 344 } 345 }; 346 347 static const struct pciide_product_desc * 348 viaide_lookup(pcireg_t id) 349 { 350 351 switch (PCI_VENDOR(id)) { 352 case PCI_VENDOR_VIATECH: 353 return (pciide_lookup_product(id, pciide_via_products)); 354 355 case PCI_VENDOR_AMD: 356 return (pciide_lookup_product(id, pciide_amd_products)); 357 358 case PCI_VENDOR_NVIDIA: 359 return (pciide_lookup_product(id, pciide_nvidia_products)); 360 } 361 return (NULL); 362 } 363 364 static int 365 viaide_match(device_t parent, cfdata_t match, void *aux) 366 { 367 struct pci_attach_args *pa = aux; 368 369 if (viaide_lookup(pa->pa_id) != NULL) 370 return (2); 371 return (0); 372 } 373 374 static void 375 viaide_attach(device_t parent, device_t self, void *aux) 376 { 377 struct pci_attach_args *pa = aux; 378 struct pciide_softc *sc = device_private(self); 379 const struct pciide_product_desc *pp; 380 381 sc->sc_wdcdev.sc_atac.atac_dev = self; 382 383 pp = viaide_lookup(pa->pa_id); 384 if (pp == NULL) 385 panic("viaide_attach"); 386 pciide_common_attach(sc, pa, pp); 387 388 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 389 aprint_error_dev(self, "couldn't establish power handler\n"); 390 } 391 392 static int 393 via_pcib_match(struct pci_attach_args *pa) 394 { 395 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 396 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 397 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 398 return (1); 399 return 0; 400 } 401 402 static bool 403 viaide_suspend(device_t dv, const pmf_qual_t *qual) 404 { 405 struct pciide_softc *sc = device_private(dv); 406 407 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 408 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 409 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 410 /* This two are VIA-only, but should be ignored by other devices. */ 411 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 412 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 413 414 return true; 415 } 416 417 static bool 418 viaide_resume(device_t dv, const pmf_qual_t *qual) 419 { 420 struct pciide_softc *sc = device_private(dv); 421 422 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 423 sc->sc_pm_reg[0]); 424 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 425 sc->sc_pm_reg[1]); 426 /* This two are VIA-only, but should be ignored by other devices. */ 427 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 428 sc->sc_pm_reg[2]); 429 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 430 sc->sc_pm_reg[3]); 431 432 return true; 433 } 434 435 static void 436 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 437 { 438 struct pciide_channel *cp; 439 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 440 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 441 int channel; 442 u_int32_t ideconf; 443 pcireg_t pcib_id, pcib_class; 444 struct pci_attach_args pcib_pa; 445 446 if (pciide_chipen(sc, pa) == 0) 447 return; 448 449 switch (vendor) { 450 case PCI_VENDOR_VIATECH: 451 /* 452 * get a PCI tag for the ISA bridge. 453 */ 454 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 455 goto unknown; 456 pcib_id = pcib_pa.pa_id; 457 pcib_class = pcib_pa.pa_class; 458 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 459 "VIA Technologies "); 460 switch (PCI_PRODUCT(pcib_id)) { 461 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 462 aprint_normal("VT82C586 (Apollo VP) "); 463 if(PCI_REVISION(pcib_class) >= 0x02) { 464 aprint_normal("ATA33 controller\n"); 465 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 466 } else { 467 aprint_normal("controller\n"); 468 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 469 } 470 break; 471 case PCI_PRODUCT_VIATECH_VT82C596A: 472 aprint_normal("VT82C596A (Apollo Pro) "); 473 if (PCI_REVISION(pcib_class) >= 0x12) { 474 aprint_normal("ATA66 controller\n"); 475 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 476 } else { 477 aprint_normal("ATA33 controller\n"); 478 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 479 } 480 break; 481 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 482 aprint_normal("VT82C686A (Apollo KX133) "); 483 if (PCI_REVISION(pcib_class) >= 0x40) { 484 aprint_normal("ATA100 controller\n"); 485 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 486 } else { 487 aprint_normal("ATA66 controller\n"); 488 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 489 } 490 break; 491 case PCI_PRODUCT_VIATECH_VT8231: 492 aprint_normal("VT8231 ATA100 controller\n"); 493 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 494 break; 495 case PCI_PRODUCT_VIATECH_VT8233: 496 aprint_normal("VT8233 ATA100 controller\n"); 497 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 498 break; 499 case PCI_PRODUCT_VIATECH_VT8233A: 500 aprint_normal("VT8233A ATA133 controller\n"); 501 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 502 break; 503 case PCI_PRODUCT_VIATECH_VT8235: 504 aprint_normal("VT8235 ATA133 controller\n"); 505 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 506 break; 507 case PCI_PRODUCT_VIATECH_VT8237: 508 aprint_normal("VT8237 ATA133 controller\n"); 509 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 510 break; 511 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 512 aprint_normal("VT8237A ATA133 controller\n"); 513 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 514 break; 515 case PCI_PRODUCT_VIATECH_CX700: 516 aprint_normal("CX700 ATA133 controller\n"); 517 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 518 break; 519 case PCI_PRODUCT_VIATECH_VT8251: 520 aprint_normal("VT8251 ATA133 controller\n"); 521 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 522 break; 523 default: 524 unknown: 525 aprint_normal("unknown VIA ATA controller\n"); 526 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 527 } 528 sc->sc_apo_regbase = APO_VIA_REGBASE; 529 break; 530 case PCI_VENDOR_AMD: 531 switch (sc->sc_pp->ide_product) { 532 case PCI_PRODUCT_AMD_PBC8111_IDE: 533 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 534 break; 535 case PCI_PRODUCT_AMD_CS5536_IDE: 536 case PCI_PRODUCT_AMD_PBC766_IDE: 537 case PCI_PRODUCT_AMD_PBC768_IDE: 538 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 539 break; 540 default: 541 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 542 } 543 sc->sc_apo_regbase = APO_AMD_REGBASE; 544 break; 545 case PCI_VENDOR_NVIDIA: 546 switch (sc->sc_pp->ide_product) { 547 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 548 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 549 break; 550 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 551 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 552 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 553 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 554 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 555 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 556 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 557 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 558 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 559 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 560 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 561 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 562 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 563 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 564 break; 565 } 566 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 567 break; 568 default: 569 panic("via_chip_map: unknown vendor"); 570 } 571 572 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 573 "bus-master DMA support present"); 574 pciide_mapreg_dma(sc, pa); 575 aprint_verbose("\n"); 576 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 577 if (sc->sc_dma_ok) { 578 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 579 sc->sc_wdcdev.irqack = pciide_irqack; 580 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 581 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 582 } 583 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 584 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 585 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 586 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 587 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 588 589 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 590 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 591 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 592 593 wdc_allocate_regs(&sc->sc_wdcdev); 594 595 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 596 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 597 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 598 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 599 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 600 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 601 DEBUG_PROBE); 602 603 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 604 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 605 channel++) { 606 cp = &sc->pciide_channels[channel]; 607 if (pciide_chansetup(sc, channel, interface) == 0) 608 continue; 609 610 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 611 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 612 "%s channel ignored (disabled)\n", cp->name); 613 cp->ata_channel.ch_flags |= ATACH_DISABLED; 614 continue; 615 } 616 via_mapchan(pa, cp, interface, pciide_pci_intr); 617 } 618 } 619 620 static void 621 via_mapchan(struct pci_attach_args *pa, struct pciide_channel *cp, 622 pcireg_t interface, int (*pci_intr)(void *)) 623 { 624 struct ata_channel *wdc_cp; 625 struct pciide_softc *sc; 626 prop_bool_t compat_nat_enable; 627 628 wdc_cp = &cp->ata_channel; 629 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 630 compat_nat_enable = prop_dictionary_get( 631 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 632 "use-compat-native-irq"); 633 634 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 635 /* native mode with irq 14/15 requested? */ 636 if (compat_nat_enable != NULL && 637 prop_bool_true(compat_nat_enable)) 638 via_mapregs_compat_native(pa, cp); 639 else 640 pciide_mapregs_native(pa, cp, pci_intr); 641 } else { 642 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 643 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 644 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 645 } 646 wdcattach(wdc_cp); 647 } 648 649 /* 650 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 651 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 652 * programmed to use a single native PCI irq alone. So we install an interrupt 653 * handler for each channel, as in compatibility mode. 654 */ 655 static void 656 via_mapregs_compat_native(struct pci_attach_args *pa, 657 struct pciide_channel *cp) 658 { 659 struct ata_channel *wdc_cp; 660 struct pciide_softc *sc; 661 662 wdc_cp = &cp->ata_channel; 663 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 664 665 /* XXX prevent pciide_mapregs_native from installing a handler */ 666 if (sc->sc_pci_ih == NULL) 667 sc->sc_pci_ih = (void *)~0; 668 pciide_mapregs_native(pa, cp, NULL); 669 670 /* interrupts are fixed to 14/15, as in compatibility mode */ 671 cp->compat = 1; 672 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 673 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 674 cp->ih = pciide_machdep_compat_intr_establish( 675 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 676 pciide_compat_intr, cp); 677 if (cp->ih == NULL) { 678 #endif 679 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 680 "no compatibility interrupt for " 681 "use by %s channel\n", cp->name); 682 wdc_cp->ch_flags |= ATACH_DISABLED; 683 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 684 } 685 sc->sc_pci_ih = cp->ih; /* XXX */ 686 #endif 687 } 688 } 689 690 static void 691 via_setup_channel(struct ata_channel *chp) 692 { 693 u_int32_t udmatim_reg, datatim_reg; 694 u_int8_t idedma_ctl; 695 int mode, drive, s; 696 struct ata_drive_datas *drvp; 697 struct atac_softc *atac = chp->ch_atac; 698 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 699 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 700 #ifndef PCIIDE_AMD756_ENABLEDMA 701 int rev = PCI_REVISION( 702 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 703 #endif 704 705 idedma_ctl = 0; 706 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 707 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 708 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 709 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 710 711 /* setup DMA if needed */ 712 pciide_channel_dma_setup(cp); 713 714 for (drive = 0; drive < 2; drive++) { 715 drvp = &chp->ch_drive[drive]; 716 /* If no drive, skip */ 717 if ((drvp->drive_flags & DRIVE) == 0) 718 continue; 719 /* add timing values, setup DMA if needed */ 720 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 721 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 722 mode = drvp->PIO_mode; 723 goto pio; 724 } 725 if ((atac->atac_cap & ATAC_CAP_UDMA) && 726 (drvp->drive_flags & DRIVE_UDMA)) { 727 /* use Ultra/DMA */ 728 s = splbio(); 729 drvp->drive_flags &= ~DRIVE_DMA; 730 splx(s); 731 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 732 APO_UDMA_EN_MTH(chp->ch_channel, drive); 733 switch (PCI_VENDOR(sc->sc_pci_id)) { 734 case PCI_VENDOR_VIATECH: 735 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 736 /* 8233a */ 737 udmatim_reg |= APO_UDMA_TIME( 738 chp->ch_channel, 739 drive, 740 via_udma133_tim[drvp->UDMA_mode]); 741 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 742 /* 686b */ 743 udmatim_reg |= APO_UDMA_TIME( 744 chp->ch_channel, 745 drive, 746 via_udma100_tim[drvp->UDMA_mode]); 747 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 748 /* 596b or 686a */ 749 udmatim_reg |= APO_UDMA_CLK66( 750 chp->ch_channel); 751 udmatim_reg |= APO_UDMA_TIME( 752 chp->ch_channel, 753 drive, 754 via_udma66_tim[drvp->UDMA_mode]); 755 } else { 756 /* 596a or 586b */ 757 udmatim_reg |= APO_UDMA_TIME( 758 chp->ch_channel, 759 drive, 760 via_udma33_tim[drvp->UDMA_mode]); 761 } 762 break; 763 case PCI_VENDOR_AMD: 764 case PCI_VENDOR_NVIDIA: 765 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 766 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 767 break; 768 } 769 /* can use PIO timings, MW DMA unused */ 770 mode = drvp->PIO_mode; 771 } else { 772 /* use Multiword DMA, but only if revision is OK */ 773 s = splbio(); 774 drvp->drive_flags &= ~DRIVE_UDMA; 775 splx(s); 776 #ifndef PCIIDE_AMD756_ENABLEDMA 777 /* 778 * The workaround doesn't seem to be necessary 779 * with all drives, so it can be disabled by 780 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 781 * triggered. 782 */ 783 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 784 sc->sc_pp->ide_product == 785 PCI_PRODUCT_AMD_PBC756_IDE && 786 AMD756_CHIPREV_DISABLEDMA(rev)) { 787 aprint_normal( 788 "%s:%d:%d: multi-word DMA disabled due " 789 "to chip revision\n", 790 device_xname( 791 sc->sc_wdcdev.sc_atac.atac_dev), 792 chp->ch_channel, drive); 793 mode = drvp->PIO_mode; 794 s = splbio(); 795 drvp->drive_flags &= ~DRIVE_DMA; 796 splx(s); 797 goto pio; 798 } 799 #endif 800 /* mode = min(pio, dma+2) */ 801 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 802 mode = drvp->PIO_mode; 803 else 804 mode = drvp->DMA_mode + 2; 805 } 806 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 807 808 pio: /* setup PIO mode */ 809 if (mode <= 2) { 810 drvp->DMA_mode = 0; 811 drvp->PIO_mode = 0; 812 mode = 0; 813 } else { 814 drvp->PIO_mode = mode; 815 drvp->DMA_mode = mode - 2; 816 } 817 datatim_reg |= 818 APO_DATATIM_PULSE(chp->ch_channel, drive, 819 apollo_pio_set[mode]) | 820 APO_DATATIM_RECOV(chp->ch_channel, drive, 821 apollo_pio_rec[mode]); 822 } 823 if (idedma_ctl != 0) { 824 /* Add software bits in status register */ 825 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 826 idedma_ctl); 827 } 828 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 829 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 830 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 831 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 832 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 833 } 834 835 static int 836 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 837 { 838 int maptype, ret; 839 840 if (pciide_chipen(sc, pa) == 0) 841 return 0; 842 843 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 844 "bus-master DMA support present"); 845 pciide_mapreg_dma(sc, pa); 846 aprint_verbose("\n"); 847 848 if (sc->sc_dma_ok) { 849 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 850 sc->sc_wdcdev.irqack = pciide_irqack; 851 } 852 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 853 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 854 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 855 856 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 857 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 858 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 859 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 860 861 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 862 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 863 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 864 865 wdc_allocate_regs(&sc->sc_wdcdev); 866 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 867 PCI_MAPREG_START + 0x14); 868 switch(maptype) { 869 case PCI_MAPREG_TYPE_IO: 870 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 871 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 872 NULL, &sc->sc_ba5_ss); 873 break; 874 case PCI_MAPREG_MEM_TYPE_32BIT: 875 /* 876 * Enable memory-space access if it isn't already there. 877 */ 878 if ((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) == 0) { 879 pcireg_t csr; 880 881 pa->pa_flags |= PCI_FLAGS_MEM_ENABLED; 882 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, 883 PCI_COMMAND_STATUS_REG); 884 pci_conf_write(pa->pa_pc, pa->pa_tag, 885 PCI_COMMAND_STATUS_REG, 886 csr | PCI_COMMAND_MEM_ENABLE); 887 } 888 889 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 890 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 891 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 892 NULL, &sc->sc_ba5_ss); 893 break; 894 default: 895 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 896 "couldn't map sata regs, unsupported maptype (0x%x)\n", 897 maptype); 898 return 0; 899 } 900 if (ret != 0) { 901 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 902 "couldn't map sata regs\n"); 903 return 0; 904 } 905 return 1; 906 } 907 908 static void 909 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 910 int satareg_shift) 911 { 912 struct pciide_channel *cp; 913 struct ata_channel *wdc_cp; 914 struct wdc_regs *wdr; 915 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 916 int channel; 917 918 if (via_sata_chip_map_common(sc, pa) == 0) 919 return; 920 921 if (interface == 0) { 922 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 923 DEBUG_PROBE); 924 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 925 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 926 } 927 928 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 929 channel++) { 930 cp = &sc->pciide_channels[channel]; 931 if (pciide_chansetup(sc, channel, interface) == 0) 932 continue; 933 wdc_cp = &cp->ata_channel; 934 wdr = CHAN_TO_WDC_REGS(wdc_cp); 935 wdr->sata_iot = sc->sc_ba5_st; 936 wdr->sata_baseioh = sc->sc_ba5_sh; 937 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 938 (wdc_cp->ch_channel << satareg_shift) + 0x0, 4, 939 &wdr->sata_status) != 0) { 940 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 941 "couldn't map channel %d sata_status regs\n", 942 wdc_cp->ch_channel); 943 continue; 944 } 945 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 946 (wdc_cp->ch_channel << satareg_shift) + 0x4, 4, 947 &wdr->sata_error) != 0) { 948 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 949 "couldn't map channel %d sata_error regs\n", 950 wdc_cp->ch_channel); 951 continue; 952 } 953 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 954 (wdc_cp->ch_channel << satareg_shift) + 0x8, 4, 955 &wdr->sata_control) != 0) { 956 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 957 "couldn't map channel %d sata_control regs\n", 958 wdc_cp->ch_channel); 959 continue; 960 } 961 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 962 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 963 } 964 } 965 966 static void 967 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 968 { 969 via_sata_chip_map(sc, pa, 6); 970 } 971 972 static void 973 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 974 { 975 via_sata_chip_map(sc, pa, 7); 976 } 977 978 static void 979 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 980 { 981 struct pciide_channel *cp; 982 struct ata_channel *wdc_cp; 983 struct wdc_regs *wdr; 984 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 985 int channel; 986 pci_intr_handle_t intrhandle; 987 const char *intrstr; 988 int i; 989 990 if (via_sata_chip_map_common(sc, pa) == 0) 991 return; 992 993 if (interface == 0) { 994 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 995 DEBUG_PROBE); 996 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 997 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 998 } 999 1000 if (pci_intr_map(pa, &intrhandle) != 0) { 1001 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1002 "couldn't map native-PCI interrupt\n"); 1003 return; 1004 } 1005 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1006 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 1007 intrhandle, IPL_BIO, pciide_pci_intr, sc); 1008 if (sc->sc_pci_ih == NULL) { 1009 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1010 "couldn't establish native-PCI interrupt"); 1011 if (intrstr != NULL) 1012 aprint_error(" at %s", intrstr); 1013 aprint_error("\n"); 1014 return; 1015 } 1016 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1017 "using %s for native-PCI interrupt\n", 1018 intrstr ? intrstr : "unknown interrupt"); 1019 1020 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1021 channel++) { 1022 cp = &sc->pciide_channels[channel]; 1023 if (pciide_chansetup(sc, channel, interface) == 0) 1024 continue; 1025 cp->ata_channel.ch_ndrive = 1; 1026 wdc_cp = &cp->ata_channel; 1027 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1028 1029 wdr->sata_iot = sc->sc_ba5_st; 1030 wdr->sata_baseioh = sc->sc_ba5_sh; 1031 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1032 (wdc_cp->ch_channel << 6) + 0x0, 4, 1033 &wdr->sata_status) != 0) { 1034 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1035 "couldn't map channel %d sata_status regs\n", 1036 wdc_cp->ch_channel); 1037 continue; 1038 } 1039 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1040 (wdc_cp->ch_channel << 6) + 0x4, 4, 1041 &wdr->sata_error) != 0) { 1042 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1043 "couldn't map channel %d sata_error regs\n", 1044 wdc_cp->ch_channel); 1045 continue; 1046 } 1047 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1048 (wdc_cp->ch_channel << 6) + 0x8, 4, 1049 &wdr->sata_control) != 0) { 1050 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1051 "couldn't map channel %d sata_control regs\n", 1052 wdc_cp->ch_channel); 1053 continue; 1054 } 1055 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 1056 1057 if (pci_mapreg_map(pa, (PCI_MAPREG_START + (4 * (channel))), 1058 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1059 NULL, &wdr->cmd_ios) != 0) { 1060 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1061 "couldn't map %s channel regs\n", cp->name); 1062 } 1063 wdr->ctl_iot = wdr->cmd_iot; 1064 for (i = 0; i < WDC_NREG; i++) { 1065 if (bus_space_subregion(wdr->cmd_iot, 1066 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1067 &wdr->cmd_iohs[i]) != 0) { 1068 aprint_error_dev( 1069 sc->sc_wdcdev.sc_atac.atac_dev, 1070 "couldn't subregion %s " 1071 "channel cmd regs\n", cp->name); 1072 return; 1073 } 1074 } 1075 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1076 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1077 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1078 "couldn't map channel %d ctl regs\n", channel); 1079 return; 1080 } 1081 wdc_init_shadow_regs(wdc_cp); 1082 wdr->data32iot = wdr->cmd_iot; 1083 wdr->data32ioh = wdr->cmd_iohs[wd_data]; 1084 wdcattach(wdc_cp); 1085 } 1086 } 1087
Indexes created Sun Oct 19 02:09:48 GMT 2025