viaide.c revision 1.83.2.1
1 /* $NetBSD: viaide.c,v 1.83.2.1 2012/10/09 13:36:06 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.83.2.1 2012/10/09 13:36:06 bouyer Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_apollo_reg.h> 40 41 static int via_pcib_match(const struct pci_attach_args *); 42 static void via_chip_map(struct pciide_softc *, 43 const struct pci_attach_args *); 44 static void via_mapchan(const struct pci_attach_args *, 45 struct pciide_channel *, 46 pcireg_t, int (*)(void *)); 47 static void via_mapregs_compat_native(const struct pci_attach_args *, 48 struct pciide_channel *); 49 static int via_sata_chip_map_common(struct pciide_softc *, 50 const struct pci_attach_args *); 51 static void via_sata_chip_map(struct pciide_softc *, 52 const struct pci_attach_args *, int); 53 static void via_sata_chip_map_6(struct pciide_softc *, 54 const struct pci_attach_args *); 55 static void via_sata_chip_map_7(struct pciide_softc *, 56 const struct pci_attach_args *); 57 static void via_sata_chip_map_new(struct pciide_softc *, 58 const struct pci_attach_args *); 59 static void via_setup_channel(struct ata_channel *); 60 61 static int viaide_match(device_t, cfdata_t, void *); 62 static void viaide_attach(device_t, device_t, void *); 63 static const struct pciide_product_desc * 64 viaide_lookup(pcireg_t); 65 static bool viaide_suspend(device_t, const pmf_qual_t *); 66 static bool viaide_resume(device_t, const pmf_qual_t *); 67 68 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 69 viaide_match, viaide_attach, pciide_detach, NULL); 70 71 static const struct pciide_product_desc pciide_amd_products[] = { 72 { PCI_PRODUCT_AMD_PBC756_IDE, 73 0, 74 "AMD AMD756 IDE Controller", 75 via_chip_map 76 }, 77 { PCI_PRODUCT_AMD_PBC766_IDE, 78 0, 79 "AMD AMD766 IDE Controller", 80 via_chip_map 81 }, 82 { PCI_PRODUCT_AMD_PBC768_IDE, 83 0, 84 "AMD AMD768 IDE Controller", 85 via_chip_map 86 }, 87 { PCI_PRODUCT_AMD_PBC8111_IDE, 88 0, 89 "AMD AMD8111 IDE Controller", 90 via_chip_map 91 }, 92 { PCI_PRODUCT_AMD_CS5536_IDE, 93 0, 94 "AMD CS5536 IDE Controller", 95 via_chip_map 96 }, 97 { 0, 98 0, 99 NULL, 100 NULL 101 } 102 }; 103 104 static const struct pciide_product_desc pciide_nvidia_products[] = { 105 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 106 0, 107 "NVIDIA nForce IDE Controller", 108 via_chip_map 109 }, 110 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 111 0, 112 "NVIDIA nForce2 IDE Controller", 113 via_chip_map 114 }, 115 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 116 0, 117 "NVIDIA nForce2 Ultra 400 IDE Controller", 118 via_chip_map 119 }, 120 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 121 0, 122 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 123 via_sata_chip_map_6 124 }, 125 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 126 0, 127 "NVIDIA nForce3 IDE Controller", 128 via_chip_map 129 }, 130 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 131 0, 132 "NVIDIA nForce3 250 IDE Controller", 133 via_chip_map 134 }, 135 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 136 0, 137 "NVIDIA nForce3 250 Serial ATA Controller", 138 via_sata_chip_map_6 139 }, 140 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 141 0, 142 "NVIDIA nForce3 250 Serial ATA Controller", 143 via_sata_chip_map_6 144 }, 145 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 146 0, 147 "NVIDIA nForce4 IDE Controller", 148 via_chip_map 149 }, 150 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 151 0, 152 "NVIDIA nForce4 Serial ATA Controller", 153 via_sata_chip_map_6 154 }, 155 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 156 0, 157 "NVIDIA nForce4 Serial ATA Controller", 158 via_sata_chip_map_6 159 }, 160 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 161 0, 162 "NVIDIA nForce430 IDE Controller", 163 via_chip_map 164 }, 165 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 166 0, 167 "NVIDIA nForce430 Serial ATA Controller", 168 via_sata_chip_map_6 169 }, 170 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 171 0, 172 "NVIDIA nForce430 Serial ATA Controller", 173 via_sata_chip_map_6 174 }, 175 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 176 0, 177 "NVIDIA MCP04 IDE Controller", 178 via_chip_map 179 }, 180 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 181 0, 182 "NVIDIA MCP04 Serial ATA Controller", 183 via_sata_chip_map_6 184 }, 185 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 186 0, 187 "NVIDIA MCP04 Serial ATA Controller", 188 via_sata_chip_map_6 189 }, 190 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 191 0, 192 "NVIDIA MCP55 IDE Controller", 193 via_chip_map 194 }, 195 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 196 0, 197 "NVIDIA MCP55 Serial ATA Controller", 198 via_sata_chip_map_6 199 }, 200 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 201 0, 202 "NVIDIA MCP55 Serial ATA Controller", 203 via_sata_chip_map_6 204 }, 205 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 206 0, 207 "NVIDIA MCP61 IDE Controller", 208 via_chip_map 209 }, 210 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 211 0, 212 "NVIDIA MCP65 IDE Controller", 213 via_chip_map 214 }, 215 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 216 0, 217 "NVIDIA MCP73 IDE Controller", 218 via_chip_map 219 }, 220 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 221 0, 222 "NVIDIA MCP77 IDE Controller", 223 via_chip_map 224 }, 225 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 226 0, 227 "NVIDIA MCP61 Serial ATA Controller", 228 via_sata_chip_map_6 229 }, 230 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 231 0, 232 "NVIDIA MCP61 Serial ATA Controller", 233 via_sata_chip_map_6 234 }, 235 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 236 0, 237 "NVIDIA MCP61 Serial ATA Controller", 238 via_sata_chip_map_6 239 }, 240 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 241 0, 242 "NVIDIA MCP65 Serial ATA Controller", 243 via_sata_chip_map_6 244 }, 245 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 246 0, 247 "NVIDIA MCP65 Serial ATA Controller", 248 via_sata_chip_map_6 249 }, 250 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 251 0, 252 "NVIDIA MCP65 Serial ATA Controller", 253 via_sata_chip_map_6 254 }, 255 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 256 0, 257 "NVIDIA MCP65 Serial ATA Controller", 258 via_sata_chip_map_6 259 }, 260 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 261 0, 262 "NVIDIA MCP67 IDE Controller", 263 via_chip_map, 264 }, 265 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 266 0, 267 "NVIDIA MCP67 Serial ATA Controller", 268 via_sata_chip_map_6, 269 }, 270 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 271 0, 272 "NVIDIA MCP67 Serial ATA Controller", 273 via_sata_chip_map_6, 274 }, 275 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 276 0, 277 "NVIDIA MCP67 Serial ATA Controller", 278 via_sata_chip_map_6, 279 }, 280 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 281 0, 282 "NVIDIA MCP67 Serial ATA Controller", 283 via_sata_chip_map_6, 284 }, 285 { 0, 286 0, 287 NULL, 288 NULL 289 } 290 }; 291 292 static const struct pciide_product_desc pciide_via_products[] = { 293 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 294 0, 295 NULL, 296 via_chip_map, 297 }, 298 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 299 0, 300 NULL, 301 via_chip_map, 302 }, 303 { PCI_PRODUCT_VIATECH_CX700_IDE, 304 0, 305 NULL, 306 via_chip_map, 307 }, 308 { PCI_PRODUCT_VIATECH_CX700M2_IDE, 309 0, 310 NULL, 311 via_chip_map, 312 }, 313 { PCI_PRODUCT_VIATECH_VX900_IDE, 314 0, 315 NULL, 316 via_chip_map, 317 }, 318 { PCI_PRODUCT_VIATECH_VT6410_RAID, 319 0, 320 NULL, 321 via_chip_map, 322 }, 323 { PCI_PRODUCT_VIATECH_VT6421_RAID, 324 0, 325 "VIA Technologies VT6421 Serial ATA RAID Controller", 326 via_sata_chip_map_new, 327 }, 328 { PCI_PRODUCT_VIATECH_VT8237_SATA, 329 0, 330 "VIA Technologies VT8237 SATA Controller", 331 via_sata_chip_map_7, 332 }, 333 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 334 0, 335 "VIA Technologies VT8237A SATA Controller", 336 via_sata_chip_map_7, 337 }, 338 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, 339 0, 340 "VIA Technologies VT8237A (5337) SATA Controller", 341 via_sata_chip_map_7, 342 }, 343 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 344 0, 345 "VIA Technologies VT8237R SATA Controller", 346 via_sata_chip_map_7, 347 }, 348 { PCI_PRODUCT_VIATECH_VT8237S_SATA, 349 0, 350 "VIA Technologies VT8237S SATA Controller", 351 via_sata_chip_map_7, 352 }, 353 { 0, 354 0, 355 NULL, 356 NULL 357 } 358 }; 359 360 static const struct pciide_product_desc * 361 viaide_lookup(pcireg_t id) 362 { 363 364 switch (PCI_VENDOR(id)) { 365 case PCI_VENDOR_VIATECH: 366 return (pciide_lookup_product(id, pciide_via_products)); 367 368 case PCI_VENDOR_AMD: 369 return (pciide_lookup_product(id, pciide_amd_products)); 370 371 case PCI_VENDOR_NVIDIA: 372 return (pciide_lookup_product(id, pciide_nvidia_products)); 373 } 374 return (NULL); 375 } 376 377 static int 378 viaide_match(device_t parent, cfdata_t match, void *aux) 379 { 380 const struct pci_attach_args *pa = aux; 381 382 if (viaide_lookup(pa->pa_id) != NULL) 383 return (2); 384 return (0); 385 } 386 387 static void 388 viaide_attach(device_t parent, device_t self, void *aux) 389 { 390 const struct pci_attach_args *pa = aux; 391 struct pciide_softc *sc = device_private(self); 392 const struct pciide_product_desc *pp; 393 394 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 395 396 sc->sc_wdcdev.sc_atac.atac_dev = self; 397 398 pp = viaide_lookup(pa->pa_id); 399 if (pp == NULL) 400 panic("viaide_attach"); 401 pciide_common_attach(sc, pa, pp); 402 403 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 404 aprint_error_dev(self, "couldn't establish power handler\n"); 405 } 406 407 static int 408 via_pcib_match(const struct pci_attach_args *pa) 409 { 410 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 411 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 412 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 413 return (1); 414 return 0; 415 } 416 417 static bool 418 viaide_suspend(device_t dv, const pmf_qual_t *qual) 419 { 420 struct pciide_softc *sc = device_private(dv); 421 422 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 423 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 424 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 425 /* This two are VIA-only, but should be ignored by other devices. */ 426 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 427 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 428 429 return true; 430 } 431 432 static bool 433 viaide_resume(device_t dv, const pmf_qual_t *qual) 434 { 435 struct pciide_softc *sc = device_private(dv); 436 437 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 438 sc->sc_pm_reg[0]); 439 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 440 sc->sc_pm_reg[1]); 441 /* This two are VIA-only, but should be ignored by other devices. */ 442 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 443 sc->sc_pm_reg[2]); 444 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 445 sc->sc_pm_reg[3]); 446 447 return true; 448 } 449 450 static void 451 via_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 452 { 453 struct pciide_channel *cp; 454 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 455 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 456 int channel; 457 u_int32_t ideconf; 458 pcireg_t pcib_id, pcib_class; 459 struct pci_attach_args pcib_pa; 460 461 if (pciide_chipen(sc, pa) == 0) 462 return; 463 464 switch (vendor) { 465 case PCI_VENDOR_VIATECH: 466 switch (PCI_PRODUCT(pa->pa_id)) { 467 case PCI_PRODUCT_VIATECH_VT6410_RAID: 468 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 469 "VIA Technologies VT6410 IDE controller\n"); 470 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 471 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 472 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 473 break; 474 case PCI_PRODUCT_VIATECH_VX900_IDE: 475 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 476 "VIA Technologies VX900 ATA133 controller\n"); 477 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 478 break; 479 default: 480 /* 481 * get a PCI tag for the ISA bridge. 482 */ 483 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 484 goto unknown; 485 pcib_id = pcib_pa.pa_id; 486 pcib_class = pcib_pa.pa_class; 487 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 488 "VIA Technologies "); 489 switch (PCI_PRODUCT(pcib_id)) { 490 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 491 aprint_normal("VT82C586 (Apollo VP) "); 492 if(PCI_REVISION(pcib_class) >= 0x02) { 493 aprint_normal("ATA33 controller\n"); 494 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 495 } else { 496 aprint_normal("controller\n"); 497 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 498 } 499 break; 500 case PCI_PRODUCT_VIATECH_VT82C596A: 501 aprint_normal("VT82C596A (Apollo Pro) "); 502 if (PCI_REVISION(pcib_class) >= 0x12) { 503 aprint_normal("ATA66 controller\n"); 504 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 505 } else { 506 aprint_normal("ATA33 controller\n"); 507 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 508 } 509 break; 510 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 511 aprint_normal("VT82C686A (Apollo KX133) "); 512 if (PCI_REVISION(pcib_class) >= 0x40) { 513 aprint_normal("ATA100 controller\n"); 514 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 515 } else { 516 aprint_normal("ATA66 controller\n"); 517 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 518 } 519 break; 520 case PCI_PRODUCT_VIATECH_VT8231: 521 aprint_normal("VT8231 ATA100 controller\n"); 522 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 523 break; 524 case PCI_PRODUCT_VIATECH_VT8233: 525 aprint_normal("VT8233 ATA100 controller\n"); 526 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 527 break; 528 case PCI_PRODUCT_VIATECH_VT8233A: 529 aprint_normal("VT8233A ATA133 controller\n"); 530 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 531 break; 532 case PCI_PRODUCT_VIATECH_VT8235: 533 aprint_normal("VT8235 ATA133 controller\n"); 534 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 535 break; 536 case PCI_PRODUCT_VIATECH_VT8237: 537 aprint_normal("VT8237 ATA133 controller\n"); 538 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 539 break; 540 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 541 aprint_normal("VT8237A ATA133 controller\n"); 542 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 543 break; 544 case PCI_PRODUCT_VIATECH_CX700: 545 aprint_normal("CX700 ATA133 controller\n"); 546 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 547 break; 548 case PCI_PRODUCT_VIATECH_VT8251: 549 aprint_normal("VT8251 ATA133 controller\n"); 550 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 551 break; 552 default: 553 unknown: 554 aprint_normal("unknown VIA ATA controller\n"); 555 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 556 } 557 break; 558 } 559 sc->sc_apo_regbase = APO_VIA_REGBASE; 560 break; 561 case PCI_VENDOR_AMD: 562 switch (sc->sc_pp->ide_product) { 563 case PCI_PRODUCT_AMD_PBC8111_IDE: 564 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 565 break; 566 case PCI_PRODUCT_AMD_CS5536_IDE: 567 case PCI_PRODUCT_AMD_PBC766_IDE: 568 case PCI_PRODUCT_AMD_PBC768_IDE: 569 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 570 break; 571 default: 572 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 573 } 574 sc->sc_apo_regbase = APO_AMD_REGBASE; 575 break; 576 case PCI_VENDOR_NVIDIA: 577 switch (sc->sc_pp->ide_product) { 578 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 579 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 580 break; 581 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 582 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 583 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 584 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 585 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 586 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 587 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 588 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 589 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 590 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 591 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 592 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 593 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 594 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 595 break; 596 } 597 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 598 break; 599 default: 600 panic("via_chip_map: unknown vendor"); 601 } 602 603 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 604 "bus-master DMA support present"); 605 pciide_mapreg_dma(sc, pa); 606 aprint_verbose("\n"); 607 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 608 if (sc->sc_dma_ok) { 609 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 610 sc->sc_wdcdev.irqack = pciide_irqack; 611 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 612 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 613 } 614 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 615 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 616 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 617 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 618 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 619 sc->sc_wdcdev.wdc_maxdrives = 2; 620 621 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 622 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 623 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 624 625 wdc_allocate_regs(&sc->sc_wdcdev); 626 627 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 628 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 629 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 630 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 631 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 632 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 633 DEBUG_PROBE); 634 635 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 636 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 637 channel++) { 638 cp = &sc->pciide_channels[channel]; 639 if (pciide_chansetup(sc, channel, interface) == 0) 640 continue; 641 642 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 643 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 644 "%s channel ignored (disabled)\n", cp->name); 645 cp->ata_channel.ch_flags |= ATACH_DISABLED; 646 continue; 647 } 648 via_mapchan(pa, cp, interface, pciide_pci_intr); 649 } 650 } 651 652 static void 653 via_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp, 654 pcireg_t interface, int (*pci_intr)(void *)) 655 { 656 struct ata_channel *wdc_cp; 657 struct pciide_softc *sc; 658 prop_bool_t compat_nat_enable; 659 660 wdc_cp = &cp->ata_channel; 661 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 662 compat_nat_enable = prop_dictionary_get( 663 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 664 "use-compat-native-irq"); 665 666 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 667 /* native mode with irq 14/15 requested? */ 668 if (compat_nat_enable != NULL && 669 prop_bool_true(compat_nat_enable)) 670 via_mapregs_compat_native(pa, cp); 671 else 672 pciide_mapregs_native(pa, cp, pci_intr); 673 } else { 674 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 675 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 676 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 677 } 678 wdcattach(wdc_cp); 679 } 680 681 /* 682 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 683 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 684 * programmed to use a single native PCI irq alone. So we install an interrupt 685 * handler for each channel, as in compatibility mode. 686 */ 687 static void 688 via_mapregs_compat_native(const struct pci_attach_args *pa, 689 struct pciide_channel *cp) 690 { 691 struct ata_channel *wdc_cp; 692 struct pciide_softc *sc; 693 694 wdc_cp = &cp->ata_channel; 695 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 696 697 /* XXX prevent pciide_mapregs_native from installing a handler */ 698 if (sc->sc_pci_ih == NULL) 699 sc->sc_pci_ih = (void *)~0; 700 pciide_mapregs_native(pa, cp, NULL); 701 702 /* interrupts are fixed to 14/15, as in compatibility mode */ 703 cp->compat = 1; 704 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 705 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 706 cp->ih = pciide_machdep_compat_intr_establish( 707 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 708 pciide_compat_intr, cp); 709 if (cp->ih == NULL) { 710 #endif 711 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 712 "no compatibility interrupt for " 713 "use by %s channel\n", cp->name); 714 wdc_cp->ch_flags |= ATACH_DISABLED; 715 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 716 } 717 sc->sc_pci_ih = cp->ih; /* XXX */ 718 #endif 719 } 720 } 721 722 static void 723 via_setup_channel(struct ata_channel *chp) 724 { 725 u_int32_t udmatim_reg, datatim_reg; 726 u_int8_t idedma_ctl; 727 int mode, drive, s; 728 struct ata_drive_datas *drvp; 729 struct atac_softc *atac = chp->ch_atac; 730 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 731 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 732 #ifndef PCIIDE_AMD756_ENABLEDMA 733 int rev = PCI_REVISION( 734 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 735 #endif 736 737 idedma_ctl = 0; 738 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 739 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 740 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 741 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 742 743 /* setup DMA if needed */ 744 pciide_channel_dma_setup(cp); 745 746 for (drive = 0; drive < 2; drive++) { 747 drvp = &chp->ch_drive[drive]; 748 /* If no drive, skip */ 749 if (drvp->drive_type == ATA_DRIVET_NONE) 750 continue; 751 /* add timing values, setup DMA if needed */ 752 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 753 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0)) { 754 mode = drvp->PIO_mode; 755 goto pio; 756 } 757 if ((atac->atac_cap & ATAC_CAP_UDMA) && 758 (drvp->drive_flags & ATA_DRIVE_UDMA)) { 759 /* use Ultra/DMA */ 760 s = splbio(); 761 drvp->drive_flags &= ~ATA_DRIVE_DMA; 762 splx(s); 763 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 764 APO_UDMA_EN_MTH(chp->ch_channel, drive); 765 switch (PCI_VENDOR(sc->sc_pci_id)) { 766 case PCI_VENDOR_VIATECH: 767 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 768 /* 8233a */ 769 udmatim_reg |= APO_UDMA_TIME( 770 chp->ch_channel, 771 drive, 772 via_udma133_tim[drvp->UDMA_mode]); 773 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 774 /* 686b */ 775 udmatim_reg |= APO_UDMA_TIME( 776 chp->ch_channel, 777 drive, 778 via_udma100_tim[drvp->UDMA_mode]); 779 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 780 /* 596b or 686a */ 781 udmatim_reg |= APO_UDMA_CLK66( 782 chp->ch_channel); 783 udmatim_reg |= APO_UDMA_TIME( 784 chp->ch_channel, 785 drive, 786 via_udma66_tim[drvp->UDMA_mode]); 787 } else { 788 /* 596a or 586b */ 789 udmatim_reg |= APO_UDMA_TIME( 790 chp->ch_channel, 791 drive, 792 via_udma33_tim[drvp->UDMA_mode]); 793 } 794 break; 795 case PCI_VENDOR_AMD: 796 case PCI_VENDOR_NVIDIA: 797 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 798 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 799 break; 800 } 801 /* can use PIO timings, MW DMA unused */ 802 mode = drvp->PIO_mode; 803 } else { 804 /* use Multiword DMA, but only if revision is OK */ 805 s = splbio(); 806 drvp->drive_flags &= ~ATA_DRIVE_UDMA; 807 splx(s); 808 #ifndef PCIIDE_AMD756_ENABLEDMA 809 /* 810 * The workaround doesn't seem to be necessary 811 * with all drives, so it can be disabled by 812 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 813 * triggered. 814 */ 815 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 816 sc->sc_pp->ide_product == 817 PCI_PRODUCT_AMD_PBC756_IDE && 818 AMD756_CHIPREV_DISABLEDMA(rev)) { 819 aprint_normal( 820 "%s:%d:%d: multi-word DMA disabled due " 821 "to chip revision\n", 822 device_xname( 823 sc->sc_wdcdev.sc_atac.atac_dev), 824 chp->ch_channel, drive); 825 mode = drvp->PIO_mode; 826 s = splbio(); 827 drvp->drive_flags &= ~ATA_DRIVE_DMA; 828 splx(s); 829 goto pio; 830 } 831 #endif 832 /* mode = min(pio, dma+2) */ 833 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 834 mode = drvp->PIO_mode; 835 else 836 mode = drvp->DMA_mode + 2; 837 } 838 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 839 840 pio: /* setup PIO mode */ 841 if (mode <= 2) { 842 drvp->DMA_mode = 0; 843 drvp->PIO_mode = 0; 844 mode = 0; 845 } else { 846 drvp->PIO_mode = mode; 847 drvp->DMA_mode = mode - 2; 848 } 849 datatim_reg |= 850 APO_DATATIM_PULSE(chp->ch_channel, drive, 851 apollo_pio_set[mode]) | 852 APO_DATATIM_RECOV(chp->ch_channel, drive, 853 apollo_pio_rec[mode]); 854 } 855 if (idedma_ctl != 0) { 856 /* Add software bits in status register */ 857 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 858 idedma_ctl); 859 } 860 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 861 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 862 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 863 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 864 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 865 } 866 867 static int 868 via_sata_chip_map_common(struct pciide_softc *sc, 869 const struct pci_attach_args *cpa) 870 { 871 pcireg_t csr; 872 int maptype, ret; 873 struct pci_attach_args pac, *pa = &pac; 874 875 pac = *cpa; 876 877 if (pciide_chipen(sc, pa) == 0) 878 return 0; 879 880 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 881 "bus-master DMA support present"); 882 pciide_mapreg_dma(sc, pa); 883 aprint_verbose("\n"); 884 885 if (sc->sc_dma_ok) { 886 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 887 sc->sc_wdcdev.irqack = pciide_irqack; 888 } 889 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 890 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 891 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 892 893 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 894 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 895 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 896 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 897 sc->sc_wdcdev.wdc_maxdrives = 2; 898 899 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 900 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 901 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 902 903 wdc_allocate_regs(&sc->sc_wdcdev); 904 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 905 PCI_MAPREG_START + 0x14); 906 switch(maptype) { 907 case PCI_MAPREG_TYPE_IO: 908 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 909 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 910 NULL, &sc->sc_ba5_ss); 911 break; 912 case PCI_MAPREG_MEM_TYPE_32BIT: 913 /* 914 * Enable memory-space access if it isn't already there. 915 */ 916 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, 917 PCI_COMMAND_STATUS_REG); 918 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 && 919 (pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) { 920 921 pci_conf_write(pa->pa_pc, pa->pa_tag, 922 PCI_COMMAND_STATUS_REG, 923 csr | PCI_COMMAND_MEM_ENABLE); 924 } 925 926 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 927 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 928 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 929 NULL, &sc->sc_ba5_ss); 930 break; 931 default: 932 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 933 "couldn't map sata regs, unsupported maptype (0x%x)\n", 934 maptype); 935 return 0; 936 } 937 if (ret != 0) { 938 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 939 "couldn't map sata regs\n"); 940 return 0; 941 } 942 return 1; 943 } 944 945 static void 946 via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa, 947 int satareg_shift) 948 { 949 struct pciide_channel *cp; 950 struct ata_channel *wdc_cp; 951 struct wdc_regs *wdr; 952 pcireg_t interface; 953 int channel; 954 955 interface = PCI_INTERFACE(pa->pa_class); 956 957 if (via_sata_chip_map_common(sc, pa) == 0) 958 return; 959 960 if (interface == 0) { 961 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 962 DEBUG_PROBE); 963 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 964 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 965 } 966 967 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 968 sc->sc_wdcdev.wdc_maxdrives = 1; 969 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 970 channel++) { 971 cp = &sc->pciide_channels[channel]; 972 if (pciide_chansetup(sc, channel, interface) == 0) 973 continue; 974 wdc_cp = &cp->ata_channel; 975 wdr = CHAN_TO_WDC_REGS(wdc_cp); 976 wdr->sata_iot = sc->sc_ba5_st; 977 wdr->sata_baseioh = sc->sc_ba5_sh; 978 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 979 (wdc_cp->ch_channel << satareg_shift) + 0x0, 4, 980 &wdr->sata_status) != 0) { 981 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 982 "couldn't map channel %d sata_status regs\n", 983 wdc_cp->ch_channel); 984 continue; 985 } 986 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 987 (wdc_cp->ch_channel << satareg_shift) + 0x4, 4, 988 &wdr->sata_error) != 0) { 989 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 990 "couldn't map channel %d sata_error regs\n", 991 wdc_cp->ch_channel); 992 continue; 993 } 994 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 995 (wdc_cp->ch_channel << satareg_shift) + 0x8, 4, 996 &wdr->sata_control) != 0) { 997 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 998 "couldn't map channel %d sata_control regs\n", 999 wdc_cp->ch_channel); 1000 continue; 1001 } 1002 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 1003 } 1004 } 1005 1006 static void 1007 via_sata_chip_map_6(struct pciide_softc *sc, const struct pci_attach_args *pa) 1008 { 1009 via_sata_chip_map(sc, pa, 6); 1010 } 1011 1012 static void 1013 via_sata_chip_map_7(struct pciide_softc *sc, const struct pci_attach_args *pa) 1014 { 1015 via_sata_chip_map(sc, pa, 7); 1016 } 1017 1018 static void 1019 via_vt6421_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 1020 { 1021 struct pciide_channel *pc; 1022 int chan, reg; 1023 bus_size_t size; 1024 1025 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 1026 PCI_MAPREG_TYPE_IO, 0, &sc->sc_dma_iot, &sc->sc_dma_ioh, 1027 NULL, &sc->sc_dma_ios) == 0); 1028 sc->sc_dmat = pa->pa_dmat; 1029 if (sc->sc_dma_ok == 0) { 1030 aprint_verbose(", but unused (couldn't map registers)"); 1031 } else { 1032 sc->sc_wdcdev.dma_arg = sc; 1033 sc->sc_wdcdev.dma_init = pciide_dma_init; 1034 sc->sc_wdcdev.dma_start = pciide_dma_start; 1035 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 1036 } 1037 1038 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 1039 PCIIDE_OPTIONS_NODMA) { 1040 aprint_verbose( 1041 ", but unused (forced off by config file)"); 1042 sc->sc_dma_ok = 0; 1043 } 1044 1045 if (sc->sc_dma_ok == 0) 1046 return; 1047 1048 for (chan = 0; chan < 4; chan++) { 1049 pc = &sc->pciide_channels[chan]; 1050 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 1051 size = 4; 1052 if (size > (IDEDMA_SCH_OFFSET - reg)) 1053 size = IDEDMA_SCH_OFFSET - reg; 1054 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 1055 IDEDMA_SCH_OFFSET * chan + reg, size, 1056 &pc->dma_iohs[reg]) != 0) { 1057 sc->sc_dma_ok = 0; 1058 aprint_verbose(", but can't subregion offset " 1059 "%d size %lu", 1060 reg, (u_long)size); 1061 return; 1062 } 1063 } 1064 } 1065 } 1066 1067 static int 1068 via_vt6421_chansetup(struct pciide_softc *sc, int channel) 1069 { 1070 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1071 1072 sc->wdc_chanarray[channel] = &cp->ata_channel; 1073 1074 cp->ata_channel.ch_channel = channel; 1075 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 1076 cp->ata_channel.ch_queue = 1077 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 1078 if (cp->ata_channel.ch_queue == NULL) { 1079 aprint_error("%s channel %d: " 1080 "can't allocate memory for command queue", 1081 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel); 1082 return 0; 1083 } 1084 return 1; 1085 } 1086 1087 static void 1088 via_sata_chip_map_new(struct pciide_softc *sc, 1089 const struct pci_attach_args *pa) 1090 { 1091 struct pciide_channel *cp; 1092 struct ata_channel *wdc_cp; 1093 struct wdc_regs *wdr; 1094 int channel; 1095 pci_intr_handle_t intrhandle; 1096 const char *intrstr; 1097 int i; 1098 1099 if (pciide_chipen(sc, pa) == 0) 1100 return; 1101 1102 sc->sc_apo_regbase = APO_VIA_VT6421_REGBASE; 1103 1104 if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0, 1105 &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 1106 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1107 "couldn't map SATA regs\n"); 1108 } 1109 1110 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1111 "bus-master DMA support present"); 1112 via_vt6421_mapreg_dma(sc, pa); 1113 aprint_verbose("\n"); 1114 1115 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 1116 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 1117 if (sc->sc_dma_ok) { 1118 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 1119 sc->sc_wdcdev.irqack = pciide_irqack; 1120 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 1121 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 1122 } 1123 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 1124 1125 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 1126 sc->sc_wdcdev.sc_atac.atac_nchannels = 3; 1127 sc->sc_wdcdev.wdc_maxdrives = 2; 1128 1129 wdc_allocate_regs(&sc->sc_wdcdev); 1130 1131 if (pci_intr_map(pa, &intrhandle) != 0) { 1132 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1133 "couldn't map native-PCI interrupt\n"); 1134 return; 1135 } 1136 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1137 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 1138 intrhandle, IPL_BIO, pciide_pci_intr, sc); 1139 if (sc->sc_pci_ih == NULL) { 1140 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1141 "couldn't establish native-PCI interrupt"); 1142 if (intrstr != NULL) 1143 aprint_error(" at %s", intrstr); 1144 aprint_error("\n"); 1145 return; 1146 } 1147 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1148 "using %s for native-PCI interrupt\n", 1149 intrstr ? intrstr : "unknown interrupt"); 1150 1151 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1152 channel++) { 1153 cp = &sc->pciide_channels[channel]; 1154 if (via_vt6421_chansetup(sc, channel) == 0) 1155 continue; 1156 wdc_cp = &cp->ata_channel; 1157 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1158 1159 wdr->sata_iot = sc->sc_ba5_st; 1160 wdr->sata_baseioh = sc->sc_ba5_sh; 1161 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1162 (wdc_cp->ch_channel << 6) + 0x0, 4, 1163 &wdr->sata_status) != 0) { 1164 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1165 "couldn't map channel %d sata_status regs\n", 1166 wdc_cp->ch_channel); 1167 continue; 1168 } 1169 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1170 (wdc_cp->ch_channel << 6) + 0x4, 4, 1171 &wdr->sata_error) != 0) { 1172 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1173 "couldn't map channel %d sata_error regs\n", 1174 wdc_cp->ch_channel); 1175 continue; 1176 } 1177 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1178 (wdc_cp->ch_channel << 6) + 0x8, 4, 1179 &wdr->sata_control) != 0) { 1180 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1181 "couldn't map channel %d sata_control regs\n", 1182 wdc_cp->ch_channel); 1183 continue; 1184 } 1185 1186 if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel), 1187 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1188 NULL, &wdr->cmd_ios) != 0) { 1189 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1190 "couldn't map %s channel regs\n", cp->name); 1191 } 1192 wdr->ctl_iot = wdr->cmd_iot; 1193 for (i = 0; i < WDC_NREG; i++) { 1194 if (bus_space_subregion(wdr->cmd_iot, 1195 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1196 &wdr->cmd_iohs[i]) != 0) { 1197 aprint_error_dev( 1198 sc->sc_wdcdev.sc_atac.atac_dev, 1199 "couldn't subregion %s " 1200 "channel cmd regs\n", cp->name); 1201 return; 1202 } 1203 } 1204 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1205 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1206 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1207 "couldn't map channel %d ctl regs\n", channel); 1208 return; 1209 } 1210 wdc_init_shadow_regs(wdc_cp); 1211 wdr->data32iot = wdr->cmd_iot; 1212 wdr->data32ioh = wdr->cmd_iohs[wd_data]; 1213 wdcattach(wdc_cp); 1214 } 1215 } 1216
Indexes created Wed Oct 22 13:09:56 GMT 2025