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viaide.c revision 1.83.2.3
      1 /*	$NetBSD: viaide.c,v 1.83.2.3 2017/12/03 11:37:29 jdolecek Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     25  *
     26  */
     27 
     28 #include <sys/cdefs.h>
     29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.83.2.3 2017/12/03 11:37:29 jdolecek Exp $");
     30 
     31 #include <sys/param.h>
     32 #include <sys/systm.h>
     33 
     34 #include <dev/pci/pcivar.h>
     35 #include <dev/pci/pcidevs.h>
     36 #include <dev/pci/pciidereg.h>
     37 #include <dev/pci/pciidevar.h>
     38 #include <dev/pci/pciide_apollo_reg.h>
     39 
     40 static int	via_pcib_match(const struct pci_attach_args *);
     41 static void	via_chip_map(struct pciide_softc *,
     42 		    const struct pci_attach_args *);
     43 static void	via_mapchan(const struct pci_attach_args *,
     44 		    struct pciide_channel *,
     45 		    pcireg_t, int (*)(void *));
     46 static void	via_mapregs_compat_native(const struct pci_attach_args *,
     47 		    struct pciide_channel *);
     48 static int	via_sata_chip_map_common(struct pciide_softc *,
     49 		    const struct pci_attach_args *);
     50 static void	via_sata_chip_map(struct pciide_softc *,
     51 		    const struct pci_attach_args *, int);
     52 static void	via_sata_chip_map_6(struct pciide_softc *,
     53 		    const struct pci_attach_args *);
     54 static void	via_sata_chip_map_7(struct pciide_softc *,
     55 		    const struct pci_attach_args *);
     56 static void	via_sata_chip_map_new(struct pciide_softc *,
     57 		    const struct pci_attach_args *);
     58 static void	via_setup_channel(struct ata_channel *);
     59 
     60 static int	viaide_match(device_t, cfdata_t, void *);
     61 static void	viaide_attach(device_t, device_t, void *);
     62 static const struct pciide_product_desc *
     63 		viaide_lookup(pcireg_t);
     64 static bool	viaide_suspend(device_t, const pmf_qual_t *);
     65 static bool	viaide_resume(device_t, const pmf_qual_t *);
     66 
     67 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc),
     68     viaide_match, viaide_attach, pciide_detach, NULL);
     69 
     70 static const struct pciide_product_desc pciide_amd_products[] =  {
     71 	{ PCI_PRODUCT_AMD_PBC756_IDE,
     72 	  0,
     73 	  "AMD AMD756 IDE Controller",
     74 	  via_chip_map
     75 	},
     76 	{ PCI_PRODUCT_AMD_PBC766_IDE,
     77 	  0,
     78 	  "AMD AMD766 IDE Controller",
     79 	  via_chip_map
     80 	},
     81 	{ PCI_PRODUCT_AMD_PBC768_IDE,
     82 	  0,
     83 	  "AMD AMD768 IDE Controller",
     84 	  via_chip_map
     85 	},
     86 	{ PCI_PRODUCT_AMD_PBC8111_IDE,
     87 	  0,
     88 	  "AMD AMD8111 IDE Controller",
     89 	  via_chip_map
     90 	},
     91 	{ PCI_PRODUCT_AMD_CS5536_IDE,
     92 	  0,
     93 	  "AMD CS5536 IDE Controller",
     94 	  via_chip_map
     95 	},
     96 	{ 0,
     97 	  0,
     98 	  NULL,
     99 	  NULL
    100 	}
    101 };
    102 
    103 static const struct pciide_product_desc pciide_nvidia_products[] = {
    104 	{ PCI_PRODUCT_NVIDIA_NFORCE_ATA100,
    105 	  0,
    106 	  "NVIDIA nForce IDE Controller",
    107 	  via_chip_map
    108 	},
    109 	{ PCI_PRODUCT_NVIDIA_NFORCE2_ATA133,
    110 	  0,
    111 	  "NVIDIA nForce2 IDE Controller",
    112 	  via_chip_map
    113 	},
    114 	{ PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133,
    115 	  0,
    116 	  "NVIDIA nForce2 Ultra 400 IDE Controller",
    117 	  via_chip_map
    118 	},
    119 	{ PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA,
    120 	  0,
    121 	  "NVIDIA nForce2 Ultra 400 Serial ATA Controller",
    122 	  via_sata_chip_map_6
    123 	},
    124 	{ PCI_PRODUCT_NVIDIA_NFORCE3_ATA133,
    125 	  0,
    126 	  "NVIDIA nForce3 IDE Controller",
    127 	  via_chip_map
    128 	},
    129 	{ PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133,
    130 	  0,
    131 	  "NVIDIA nForce3 250 IDE Controller",
    132 	  via_chip_map
    133 	},
    134 	{ PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA,
    135 	  0,
    136 	  "NVIDIA nForce3 250 Serial ATA Controller",
    137 	  via_sata_chip_map_6
    138 	},
    139 	{ PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2,
    140 	  0,
    141 	  "NVIDIA nForce3 250 Serial ATA Controller",
    142 	  via_sata_chip_map_6
    143 	},
    144 	{ PCI_PRODUCT_NVIDIA_NFORCE4_ATA133,
    145 	  0,
    146 	  "NVIDIA nForce4 IDE Controller",
    147 	  via_chip_map
    148 	},
    149 	{ PCI_PRODUCT_NVIDIA_NFORCE4_SATA1,
    150 	  0,
    151 	  "NVIDIA nForce4 Serial ATA Controller",
    152 	  via_sata_chip_map_6
    153 	},
    154 	{ PCI_PRODUCT_NVIDIA_NFORCE4_SATA2,
    155 	  0,
    156 	  "NVIDIA nForce4 Serial ATA Controller",
    157 	  via_sata_chip_map_6
    158 	},
    159 	{ PCI_PRODUCT_NVIDIA_NFORCE430_ATA133,
    160 	  0,
    161 	  "NVIDIA nForce430 IDE Controller",
    162 	  via_chip_map
    163 	},
    164 	{ PCI_PRODUCT_NVIDIA_NFORCE430_SATA1,
    165 	  0,
    166 	  "NVIDIA nForce430 Serial ATA Controller",
    167 	  via_sata_chip_map_6
    168 	},
    169 	{ PCI_PRODUCT_NVIDIA_NFORCE430_SATA2,
    170 	  0,
    171 	  "NVIDIA nForce430 Serial ATA Controller",
    172 	  via_sata_chip_map_6
    173 	},
    174 	{ PCI_PRODUCT_NVIDIA_MCP04_IDE,
    175 	  0,
    176 	  "NVIDIA MCP04 IDE Controller",
    177 	  via_chip_map
    178 	},
    179 	{ PCI_PRODUCT_NVIDIA_MCP04_SATA,
    180 	  0,
    181 	  "NVIDIA MCP04 Serial ATA Controller",
    182 	  via_sata_chip_map_6
    183 	},
    184 	{ PCI_PRODUCT_NVIDIA_MCP04_SATA2,
    185 	  0,
    186 	  "NVIDIA MCP04 Serial ATA Controller",
    187 	  via_sata_chip_map_6
    188 	},
    189 	{ PCI_PRODUCT_NVIDIA_MCP55_IDE,
    190 	  0,
    191 	  "NVIDIA MCP55 IDE Controller",
    192 	  via_chip_map
    193 	},
    194 	{ PCI_PRODUCT_NVIDIA_MCP55_SATA,
    195 	  0,
    196 	  "NVIDIA MCP55 Serial ATA Controller",
    197 	  via_sata_chip_map_6
    198 	},
    199 	{ PCI_PRODUCT_NVIDIA_MCP55_SATA2,
    200 	  0,
    201 	  "NVIDIA MCP55 Serial ATA Controller",
    202 	  via_sata_chip_map_6
    203 	},
    204 	{ PCI_PRODUCT_NVIDIA_MCP61_IDE,
    205 	  0,
    206 	  "NVIDIA MCP61 IDE Controller",
    207 	  via_chip_map
    208 	},
    209 	{ PCI_PRODUCT_NVIDIA_MCP65_IDE,
    210 	  0,
    211 	  "NVIDIA MCP65 IDE Controller",
    212 	  via_chip_map
    213 	},
    214 	{ PCI_PRODUCT_NVIDIA_MCP73_IDE,
    215 	  0,
    216 	  "NVIDIA MCP73 IDE Controller",
    217 	  via_chip_map
    218 	},
    219 	{ PCI_PRODUCT_NVIDIA_MCP77_IDE,
    220 	  0,
    221 	  "NVIDIA MCP77 IDE Controller",
    222 	  via_chip_map
    223 	},
    224 	{ PCI_PRODUCT_NVIDIA_MCP61_SATA,
    225 	  0,
    226 	  "NVIDIA MCP61 Serial ATA Controller",
    227 	  via_sata_chip_map_6
    228 	},
    229 	{ PCI_PRODUCT_NVIDIA_MCP61_SATA2,
    230 	  0,
    231 	  "NVIDIA MCP61 Serial ATA Controller",
    232 	  via_sata_chip_map_6
    233 	},
    234 	{ PCI_PRODUCT_NVIDIA_MCP61_SATA3,
    235 	  0,
    236 	  "NVIDIA MCP61 Serial ATA Controller",
    237 	  via_sata_chip_map_6
    238 	},
    239 	{ PCI_PRODUCT_NVIDIA_MCP65_SATA,
    240 	  0,
    241 	  "NVIDIA MCP65 Serial ATA Controller",
    242 	  via_sata_chip_map_6
    243 	},
    244 	{ PCI_PRODUCT_NVIDIA_MCP65_SATA2,
    245 	  0,
    246 	  "NVIDIA MCP65 Serial ATA Controller",
    247 	  via_sata_chip_map_6
    248 	},
    249 	{ PCI_PRODUCT_NVIDIA_MCP65_SATA3,
    250 	  0,
    251 	  "NVIDIA MCP65 Serial ATA Controller",
    252 	  via_sata_chip_map_6
    253 	},
    254 	{ PCI_PRODUCT_NVIDIA_MCP65_SATA4,
    255 	  0,
    256 	  "NVIDIA MCP65 Serial ATA Controller",
    257 	  via_sata_chip_map_6
    258 	},
    259 	{ PCI_PRODUCT_NVIDIA_MCP67_IDE,
    260 	  0,
    261 	  "NVIDIA MCP67 IDE Controller",
    262 	  via_chip_map,
    263 	},
    264 	{ PCI_PRODUCT_NVIDIA_MCP67_SATA,
    265 	  0,
    266 	  "NVIDIA MCP67 Serial ATA Controller",
    267 	  via_sata_chip_map_6,
    268 	},
    269 	{ PCI_PRODUCT_NVIDIA_MCP67_SATA2,
    270 	  0,
    271 	  "NVIDIA MCP67 Serial ATA Controller",
    272 	  via_sata_chip_map_6,
    273 	},
    274 	{ PCI_PRODUCT_NVIDIA_MCP67_SATA3,
    275 	  0,
    276 	  "NVIDIA MCP67 Serial ATA Controller",
    277 	  via_sata_chip_map_6,
    278 	},
    279 	{ PCI_PRODUCT_NVIDIA_MCP67_SATA4,
    280 	  0,
    281 	  "NVIDIA MCP67 Serial ATA Controller",
    282 	  via_sata_chip_map_6,
    283 	},
    284 	{ 0,
    285 	  0,
    286 	  NULL,
    287 	  NULL
    288 	}
    289 };
    290 
    291 static const struct pciide_product_desc pciide_via_products[] =  {
    292 	{ PCI_PRODUCT_VIATECH_VT82C586_IDE,
    293 	  0,
    294 	  NULL,
    295 	  via_chip_map,
    296 	 },
    297 	{ PCI_PRODUCT_VIATECH_VT82C586A_IDE,
    298 	  0,
    299 	  NULL,
    300 	  via_chip_map,
    301 	},
    302 	{ PCI_PRODUCT_VIATECH_CX700_IDE,
    303 	  0,
    304 	  NULL,
    305 	  via_chip_map,
    306 	},
    307 	{ PCI_PRODUCT_VIATECH_CX700M2_IDE,
    308 	  0,
    309 	  NULL,
    310 	  via_chip_map,
    311 	},
    312 	{ PCI_PRODUCT_VIATECH_VX900_IDE,
    313 	  0,
    314 	  NULL,
    315 	  via_chip_map,
    316 	},
    317 	{ PCI_PRODUCT_VIATECH_VT6410_RAID,
    318 	  0,
    319 	  NULL,
    320 	  via_chip_map,
    321 	},
    322 	{ PCI_PRODUCT_VIATECH_VT6421_RAID,
    323 	  0,
    324 	  "VIA Technologies VT6421 Serial ATA RAID Controller",
    325 	  via_sata_chip_map_new,
    326 	},
    327 	{ PCI_PRODUCT_VIATECH_VT8237_SATA,
    328 	  0,
    329 	  "VIA Technologies VT8237 SATA Controller",
    330 	  via_sata_chip_map_7,
    331 	},
    332 	{ PCI_PRODUCT_VIATECH_VT8237A_SATA,
    333 	  0,
    334 	  "VIA Technologies VT8237A SATA Controller",
    335 	  via_sata_chip_map_7,
    336 	},
    337 	{ PCI_PRODUCT_VIATECH_VT8237A_SATA_2,
    338 	  0,
    339 	  "VIA Technologies VT8237A (5337) SATA Controller",
    340 	  via_sata_chip_map_7,
    341 	},
    342 	{ PCI_PRODUCT_VIATECH_VT8237R_SATA,
    343 	  0,
    344 	  "VIA Technologies VT8237R SATA Controller",
    345 	  via_sata_chip_map_7,
    346 	},
    347 	{ PCI_PRODUCT_VIATECH_VT8237S_SATA,
    348 	  0,
    349 	  "VIA Technologies VT8237S SATA Controller",
    350 	  via_sata_chip_map_7,
    351 	},
    352 	{ 0,
    353 	  0,
    354 	  NULL,
    355 	  NULL
    356 	}
    357 };
    358 
    359 static const struct pciide_product_desc *
    360 viaide_lookup(pcireg_t id)
    361 {
    362 
    363 	switch (PCI_VENDOR(id)) {
    364 	case PCI_VENDOR_VIATECH:
    365 		return (pciide_lookup_product(id, pciide_via_products));
    366 
    367 	case PCI_VENDOR_AMD:
    368 		return (pciide_lookup_product(id, pciide_amd_products));
    369 
    370 	case PCI_VENDOR_NVIDIA:
    371 		return (pciide_lookup_product(id, pciide_nvidia_products));
    372 	}
    373 	return (NULL);
    374 }
    375 
    376 static int
    377 viaide_match(device_t parent, cfdata_t match, void *aux)
    378 {
    379 	const struct pci_attach_args *pa = aux;
    380 
    381 	if (viaide_lookup(pa->pa_id) != NULL)
    382 		return (2);
    383 	return (0);
    384 }
    385 
    386 static void
    387 viaide_attach(device_t parent, device_t self, void *aux)
    388 {
    389 	const struct pci_attach_args *pa = aux;
    390 	struct pciide_softc *sc = device_private(self);
    391 	const struct pciide_product_desc *pp;
    392 
    393 	self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS);
    394 
    395 	sc->sc_wdcdev.sc_atac.atac_dev = self;
    396 
    397 	pp = viaide_lookup(pa->pa_id);
    398 	if (pp == NULL)
    399 		panic("viaide_attach");
    400 	pciide_common_attach(sc, pa, pp);
    401 
    402 	if (!pmf_device_register(self, viaide_suspend, viaide_resume))
    403 		aprint_error_dev(self, "couldn't establish power handler\n");
    404 }
    405 
    406 static int
    407 via_pcib_match(const struct pci_attach_args *pa)
    408 {
    409 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
    410 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
    411 	    PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH)
    412 		return (1);
    413 	return 0;
    414 }
    415 
    416 static bool
    417 viaide_suspend(device_t dv, const pmf_qual_t *qual)
    418 {
    419 	struct pciide_softc *sc = device_private(dv);
    420 
    421 	sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
    422 	/* APO_DATATIM(sc) includes APO_UDMA(sc) */
    423 	sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
    424 	/* This two are VIA-only, but should be ignored by other devices. */
    425 	sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc));
    426 	sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc));
    427 
    428 	return true;
    429 }
    430 
    431 static bool
    432 viaide_resume(device_t dv, const pmf_qual_t *qual)
    433 {
    434 	struct pciide_softc *sc = device_private(dv);
    435 
    436 	pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc),
    437 	    sc->sc_pm_reg[0]);
    438 	pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc),
    439 	    sc->sc_pm_reg[1]);
    440 	/* This two are VIA-only, but should be ignored by other devices. */
    441 	pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc),
    442 	    sc->sc_pm_reg[2]);
    443 	pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc),
    444 	    sc->sc_pm_reg[3]);
    445 
    446 	return true;
    447 }
    448 
    449 static void
    450 via_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
    451 {
    452 	struct pciide_channel *cp;
    453 	pcireg_t interface = PCI_INTERFACE(pa->pa_class);
    454 	pcireg_t vendor = PCI_VENDOR(pa->pa_id);
    455 	int channel;
    456 	u_int32_t ideconf;
    457 	pcireg_t pcib_id, pcib_class;
    458 	struct pci_attach_args pcib_pa;
    459 
    460 	if (pciide_chipen(sc, pa) == 0)
    461 		return;
    462 
    463 	switch (vendor) {
    464 	case PCI_VENDOR_VIATECH:
    465 		switch (PCI_PRODUCT(pa->pa_id)) {
    466 		case PCI_PRODUCT_VIATECH_VT6410_RAID:
    467 			aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    468 			    "VIA Technologies VT6410 IDE controller\n");
    469 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    470 			interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
    471 			    PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
    472 			break;
    473 		case PCI_PRODUCT_VIATECH_VX900_IDE:
    474 			aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    475 			    "VIA Technologies VX900 ATA133 controller\n");
    476 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    477 			break;
    478 		default:
    479 			/*
    480 			 * get a PCI tag for the ISA bridge.
    481 			 */
    482 			if (pci_find_device(&pcib_pa, via_pcib_match) == 0)
    483 				goto unknown;
    484 			pcib_id = pcib_pa.pa_id;
    485 			pcib_class = pcib_pa.pa_class;
    486 			aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    487 			    "VIA Technologies ");
    488 			switch (PCI_PRODUCT(pcib_id)) {
    489 			case PCI_PRODUCT_VIATECH_VT82C586_ISA:
    490 				aprint_normal("VT82C586 (Apollo VP) ");
    491 				if(PCI_REVISION(pcib_class) >= 0x02) {
    492 					aprint_normal("ATA33 controller\n");
    493 					sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
    494 				} else {
    495 					aprint_normal("controller\n");
    496 					sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
    497 				}
    498 				break;
    499 			case PCI_PRODUCT_VIATECH_VT82C596A:
    500 				aprint_normal("VT82C596A (Apollo Pro) ");
    501 				if (PCI_REVISION(pcib_class) >= 0x12) {
    502 					aprint_normal("ATA66 controller\n");
    503 					sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
    504 				} else {
    505 					aprint_normal("ATA33 controller\n");
    506 					sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
    507 				}
    508 				break;
    509 			case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
    510 				aprint_normal("VT82C686A (Apollo KX133) ");
    511 				if (PCI_REVISION(pcib_class) >= 0x40) {
    512 					aprint_normal("ATA100 controller\n");
    513 					sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    514 				} else {
    515 					aprint_normal("ATA66 controller\n");
    516 					sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
    517 				}
    518 				break;
    519 			case PCI_PRODUCT_VIATECH_VT8231:
    520 				aprint_normal("VT8231 ATA100 controller\n");
    521 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    522 				break;
    523 			case PCI_PRODUCT_VIATECH_VT8233:
    524 				aprint_normal("VT8233 ATA100 controller\n");
    525 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    526 				break;
    527 			case PCI_PRODUCT_VIATECH_VT8233A:
    528 				aprint_normal("VT8233A ATA133 controller\n");
    529 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    530 				break;
    531 			case PCI_PRODUCT_VIATECH_VT8235:
    532 				aprint_normal("VT8235 ATA133 controller\n");
    533 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    534 				break;
    535 			case PCI_PRODUCT_VIATECH_VT8237:
    536 				aprint_normal("VT8237 ATA133 controller\n");
    537 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    538 				break;
    539 			case PCI_PRODUCT_VIATECH_VT8237A_ISA:
    540 				aprint_normal("VT8237A ATA133 controller\n");
    541 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    542 				break;
    543 			case PCI_PRODUCT_VIATECH_CX700:
    544 				aprint_normal("CX700 ATA133 controller\n");
    545 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    546 				break;
    547 			case PCI_PRODUCT_VIATECH_VT8251:
    548 				aprint_normal("VT8251 ATA133 controller\n");
    549 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    550 				break;
    551 			default:
    552 		unknown:
    553 				aprint_normal("unknown VIA ATA controller\n");
    554 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
    555 			}
    556 			break;
    557 		}
    558 		sc->sc_apo_regbase = APO_VIA_REGBASE;
    559 		break;
    560 	case PCI_VENDOR_AMD:
    561 		switch (sc->sc_pp->ide_product) {
    562 		case PCI_PRODUCT_AMD_PBC8111_IDE:
    563 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    564 			break;
    565 		case PCI_PRODUCT_AMD_CS5536_IDE:
    566 		case PCI_PRODUCT_AMD_PBC766_IDE:
    567 		case PCI_PRODUCT_AMD_PBC768_IDE:
    568 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    569 			break;
    570 		default:
    571 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
    572 		}
    573 		sc->sc_apo_regbase = APO_AMD_REGBASE;
    574 		break;
    575 	case PCI_VENDOR_NVIDIA:
    576 		switch (sc->sc_pp->ide_product) {
    577 		case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
    578 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    579 			break;
    580 		case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
    581 		case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133:
    582 		case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
    583 		case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133:
    584 		case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133:
    585 		case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133:
    586 		case PCI_PRODUCT_NVIDIA_MCP04_IDE:
    587 		case PCI_PRODUCT_NVIDIA_MCP55_IDE:
    588 		case PCI_PRODUCT_NVIDIA_MCP61_IDE:
    589 		case PCI_PRODUCT_NVIDIA_MCP65_IDE:
    590 		case PCI_PRODUCT_NVIDIA_MCP67_IDE:
    591 		case PCI_PRODUCT_NVIDIA_MCP73_IDE:
    592 		case PCI_PRODUCT_NVIDIA_MCP77_IDE:
    593 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    594 			break;
    595 		}
    596 		sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
    597 		break;
    598 	default:
    599 		panic("via_chip_map: unknown vendor");
    600 	}
    601 
    602 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    603 	    "bus-master DMA support present");
    604 	pciide_mapreg_dma(sc, pa);
    605 	aprint_verbose("\n");
    606 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    607 	if (sc->sc_dma_ok) {
    608 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
    609 		sc->sc_wdcdev.irqack = pciide_irqack;
    610 		if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0)
    611 			sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
    612 	}
    613 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    614 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    615 	sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel;
    616 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    617 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
    618 	sc->sc_wdcdev.wdc_maxdrives = 2;
    619 
    620 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
    621 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
    622 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
    623 
    624 	wdc_allocate_regs(&sc->sc_wdcdev);
    625 
    626 	ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
    627 	    "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
    628 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
    629 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
    630 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
    631 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
    632 	    DEBUG_PROBE);
    633 
    634 	ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
    635 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    636 	     channel++) {
    637 		cp = &sc->pciide_channels[channel];
    638 		if (pciide_chansetup(sc, channel, interface) == 0)
    639 			continue;
    640 
    641 		if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
    642 			aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    643 			    "%s channel ignored (disabled)\n", cp->name);
    644 			cp->ata_channel.ch_flags |= ATACH_DISABLED;
    645 			continue;
    646 		}
    647 		via_mapchan(pa, cp, interface, pciide_pci_intr);
    648 	}
    649 }
    650 
    651 static void
    652 via_mapchan(const struct pci_attach_args *pa,	struct pciide_channel *cp,
    653     pcireg_t interface, int (*pci_intr)(void *))
    654 {
    655 	struct ata_channel *wdc_cp;
    656 	struct pciide_softc *sc;
    657 	prop_bool_t compat_nat_enable;
    658 
    659 	wdc_cp = &cp->ata_channel;
    660 	sc = CHAN_TO_PCIIDE(&cp->ata_channel);
    661 	compat_nat_enable = prop_dictionary_get(
    662 	    device_properties(sc->sc_wdcdev.sc_atac.atac_dev),
    663 	      "use-compat-native-irq");
    664 
    665 	if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) {
    666 		/* native mode with irq 14/15 requested? */
    667 		if (compat_nat_enable != NULL &&
    668 		    prop_bool_true(compat_nat_enable))
    669 			via_mapregs_compat_native(pa, cp);
    670 		else
    671 			pciide_mapregs_native(pa, cp, pci_intr);
    672 	} else {
    673 		pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel);
    674 		if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0)
    675 			pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel);
    676 	}
    677 	wdcattach(wdc_cp);
    678 }
    679 
    680 /*
    681  * At least under certain (mis)configurations (e.g. on the "Pegasos" board)
    682  * the VT8231-IDE's native mode only works with irq 14/15, and cannot be
    683  * programmed to use a single native PCI irq alone. So we install an interrupt
    684  * handler for each channel, as in compatibility mode.
    685  */
    686 static void
    687 via_mapregs_compat_native(const struct pci_attach_args *pa,
    688     struct pciide_channel *cp)
    689 {
    690 	struct ata_channel *wdc_cp;
    691 	struct pciide_softc *sc;
    692 
    693 	wdc_cp = &cp->ata_channel;
    694 	sc = CHAN_TO_PCIIDE(&cp->ata_channel);
    695 
    696 	/* XXX prevent pciide_mapregs_native from installing a handler */
    697 	if (sc->sc_pci_ih == NULL)
    698 		sc->sc_pci_ih = (void *)~0;
    699 	pciide_mapregs_native(pa, cp, NULL);
    700 
    701 	/* interrupts are fixed to 14/15, as in compatibility mode */
    702 	cp->compat = 1;
    703 	if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) {
    704 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
    705 		cp->ih = pciide_machdep_compat_intr_establish(
    706 		    sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel,
    707 		    pciide_compat_intr, cp);
    708 		if (cp->ih == NULL) {
    709 #endif
    710 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    711 			    "no compatibility interrupt for "
    712 			    "use by %s channel\n", cp->name);
    713 			wdc_cp->ch_flags |= ATACH_DISABLED;
    714 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
    715 		}
    716 		sc->sc_pci_ih = cp->ih;  /* XXX */
    717 #endif
    718 	}
    719 }
    720 
    721 static void
    722 via_setup_channel(struct ata_channel *chp)
    723 {
    724 	u_int32_t udmatim_reg, datatim_reg;
    725 	u_int8_t idedma_ctl;
    726 	int mode, drive, s;
    727 	struct ata_drive_datas *drvp;
    728 	struct atac_softc *atac = chp->ch_atac;
    729 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
    730 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
    731 #ifndef PCIIDE_AMD756_ENABLEDMA
    732 	int rev = PCI_REVISION(
    733 	    pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
    734 #endif
    735 
    736 	idedma_ctl = 0;
    737 	datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
    738 	udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc));
    739 	datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
    740 	udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
    741 
    742 	/* setup DMA if needed */
    743 	pciide_channel_dma_setup(cp);
    744 
    745 	for (drive = 0; drive < 2; drive++) {
    746 		drvp = &chp->ch_drive[drive];
    747 		/* If no drive, skip */
    748 		if (drvp->drive_type == ATA_DRIVET_NONE)
    749 			continue;
    750 		/* add timing values, setup DMA if needed */
    751 		if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 &&
    752 		    (drvp->drive_flags & ATA_DRIVE_UDMA) == 0)) {
    753 			mode = drvp->PIO_mode;
    754 			goto pio;
    755 		}
    756 		if ((atac->atac_cap & ATAC_CAP_UDMA) &&
    757 		    (drvp->drive_flags & ATA_DRIVE_UDMA)) {
    758 			/* use Ultra/DMA */
    759 			s = splbio();
    760 			drvp->drive_flags &= ~ATA_DRIVE_DMA;
    761 			splx(s);
    762 			udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
    763 			    APO_UDMA_EN_MTH(chp->ch_channel, drive);
    764 			switch (PCI_VENDOR(sc->sc_pci_id)) {
    765 			case PCI_VENDOR_VIATECH:
    766 				if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) {
    767 					/* 8233a */
    768 					udmatim_reg |= APO_UDMA_TIME(
    769 					    chp->ch_channel,
    770 					    drive,
    771 					    via_udma133_tim[drvp->UDMA_mode]);
    772 				} else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) {
    773 					/* 686b */
    774 					udmatim_reg |= APO_UDMA_TIME(
    775 					    chp->ch_channel,
    776 					    drive,
    777 					    via_udma100_tim[drvp->UDMA_mode]);
    778 				} else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) {
    779 					/* 596b or 686a */
    780 					udmatim_reg |= APO_UDMA_CLK66(
    781 					    chp->ch_channel);
    782 					udmatim_reg |= APO_UDMA_TIME(
    783 					    chp->ch_channel,
    784 					    drive,
    785 					    via_udma66_tim[drvp->UDMA_mode]);
    786 				} else {
    787 					/* 596a or 586b */
    788 					udmatim_reg |= APO_UDMA_TIME(
    789 					    chp->ch_channel,
    790 					    drive,
    791 					    via_udma33_tim[drvp->UDMA_mode]);
    792 				}
    793 				break;
    794 			case PCI_VENDOR_AMD:
    795 			case PCI_VENDOR_NVIDIA:
    796 				udmatim_reg |= APO_UDMA_TIME(chp->ch_channel,
    797 				    drive, amd7x6_udma_tim[drvp->UDMA_mode]);
    798 				 break;
    799 			}
    800 			/* can use PIO timings, MW DMA unused */
    801 			mode = drvp->PIO_mode;
    802 		} else {
    803 			/* use Multiword DMA, but only if revision is OK */
    804 			s = splbio();
    805 			drvp->drive_flags &= ~ATA_DRIVE_UDMA;
    806 			splx(s);
    807 #ifndef PCIIDE_AMD756_ENABLEDMA
    808 			/*
    809 			 * The workaround doesn't seem to be necessary
    810 			 * with all drives, so it can be disabled by
    811 			 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
    812 			 * triggered.
    813 			 */
    814 			if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD &&
    815 			    sc->sc_pp->ide_product ==
    816 			    PCI_PRODUCT_AMD_PBC756_IDE &&
    817 			    AMD756_CHIPREV_DISABLEDMA(rev)) {
    818 				aprint_normal(
    819 				    "%s:%d:%d: multi-word DMA disabled due "
    820 				    "to chip revision\n",
    821 				    device_xname(
    822 				      sc->sc_wdcdev.sc_atac.atac_dev),
    823 				    chp->ch_channel, drive);
    824 				mode = drvp->PIO_mode;
    825 				s = splbio();
    826 				drvp->drive_flags &= ~ATA_DRIVE_DMA;
    827 				splx(s);
    828 				goto pio;
    829 			}
    830 #endif
    831 			/* mode = min(pio, dma+2) */
    832 			if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
    833 				mode = drvp->PIO_mode;
    834 			else
    835 				mode = drvp->DMA_mode + 2;
    836 		}
    837 		idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    838 
    839 pio:		/* setup PIO mode */
    840 		if (mode <= 2) {
    841 			drvp->DMA_mode = 0;
    842 			drvp->PIO_mode = 0;
    843 			mode = 0;
    844 		} else {
    845 			drvp->PIO_mode = mode;
    846 			drvp->DMA_mode = mode - 2;
    847 		}
    848 		datatim_reg |=
    849 		    APO_DATATIM_PULSE(chp->ch_channel, drive,
    850 			apollo_pio_set[mode]) |
    851 		    APO_DATATIM_RECOV(chp->ch_channel, drive,
    852 			apollo_pio_rec[mode]);
    853 	}
    854 	if (idedma_ctl != 0) {
    855 		/* Add software bits in status register */
    856 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
    857 		    idedma_ctl);
    858 	}
    859 	pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg);
    860 	pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg);
    861 	ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
    862 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
    863 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE);
    864 }
    865 
    866 static int
    867 via_sata_chip_map_common(struct pciide_softc *sc,
    868     const struct pci_attach_args *cpa)
    869 {
    870 	pcireg_t csr;
    871 	int maptype, ret;
    872 	struct pci_attach_args pac, *pa = &pac;
    873 
    874 	pac = *cpa;
    875 
    876 	if (pciide_chipen(sc, pa) == 0)
    877 		return 0;
    878 
    879 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    880 	    "bus-master DMA support present");
    881 	pciide_mapreg_dma(sc, pa);
    882 	aprint_verbose("\n");
    883 
    884 	if (sc->sc_dma_ok) {
    885 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
    886 		sc->sc_wdcdev.irqack = pciide_irqack;
    887 	}
    888 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    889 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    890 	sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    891 
    892 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    893 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
    894 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    895 	sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
    896 	sc->sc_wdcdev.wdc_maxdrives = 2;
    897 
    898 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
    899 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
    900 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
    901 
    902 	wdc_allocate_regs(&sc->sc_wdcdev);
    903 	maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
    904 	    PCI_MAPREG_START + 0x14);
    905 	switch(maptype) {
    906 	case PCI_MAPREG_TYPE_IO:
    907 		ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
    908 		    PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
    909 		    NULL, &sc->sc_ba5_ss);
    910 		break;
    911 	case PCI_MAPREG_MEM_TYPE_32BIT:
    912 		/*
    913 		 * Enable memory-space access if it isn't already there.
    914 		 */
    915 		csr = pci_conf_read(pa->pa_pc, pa->pa_tag,
    916 		    PCI_COMMAND_STATUS_REG);
    917 		if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 &&
    918 		    (pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) {
    919 
    920 			pci_conf_write(pa->pa_pc, pa->pa_tag,
    921 			    PCI_COMMAND_STATUS_REG,
    922 			    csr | PCI_COMMAND_MEM_ENABLE);
    923 		}
    924 
    925 		ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
    926 		    PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
    927 		    0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
    928 		    NULL, &sc->sc_ba5_ss);
    929 		break;
    930 	default:
    931 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    932 		    "couldn't map sata regs, unsupported maptype (0x%x)\n",
    933 		    maptype);
    934 		return 0;
    935 	}
    936 	if (ret != 0) {
    937 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    938 		    "couldn't map sata regs\n");
    939 		return 0;
    940 	}
    941 	return 1;
    942 }
    943 
    944 static void
    945 via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa,
    946     int satareg_shift)
    947 {
    948 	struct pciide_channel *cp;
    949 	struct ata_channel *wdc_cp;
    950 	struct wdc_regs *wdr;
    951 	pcireg_t interface;
    952 	int channel;
    953 
    954 	interface = PCI_INTERFACE(pa->pa_class);
    955 
    956 	if (via_sata_chip_map_common(sc, pa) == 0)
    957 		return;
    958 
    959 	if (interface == 0) {
    960 		ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
    961 		    DEBUG_PROBE);
    962 		interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
    963 		    PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
    964 	}
    965 
    966 	sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
    967 	sc->sc_wdcdev.wdc_maxdrives = 1;
    968 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    969 	     channel++) {
    970 		cp = &sc->pciide_channels[channel];
    971 		if (pciide_chansetup(sc, channel, interface) == 0)
    972 			continue;
    973 		wdc_cp = &cp->ata_channel;
    974 		wdr = CHAN_TO_WDC_REGS(wdc_cp);
    975 		wdr->sata_iot = sc->sc_ba5_st;
    976 		wdr->sata_baseioh = sc->sc_ba5_sh;
    977 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    978 		    (wdc_cp->ch_channel << satareg_shift) + 0x0, 4,
    979 		    &wdr->sata_status) != 0) {
    980 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    981 			    "couldn't map channel %d sata_status regs\n",
    982 			    wdc_cp->ch_channel);
    983 			continue;
    984 		}
    985 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    986 		    (wdc_cp->ch_channel << satareg_shift) + 0x4, 4,
    987 		    &wdr->sata_error) != 0) {
    988 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    989 			    "couldn't map channel %d sata_error regs\n",
    990 			    wdc_cp->ch_channel);
    991 			continue;
    992 		}
    993 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    994 		    (wdc_cp->ch_channel << satareg_shift) + 0x8, 4,
    995 		    &wdr->sata_control) != 0) {
    996 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    997 			    "couldn't map channel %d sata_control regs\n",
    998 			    wdc_cp->ch_channel);
    999 			continue;
   1000 		}
   1001 		pciide_mapchan(pa, cp, interface, pciide_pci_intr);
   1002 	}
   1003 }
   1004 
   1005 static void
   1006 via_sata_chip_map_6(struct pciide_softc *sc, const struct pci_attach_args *pa)
   1007 {
   1008 	via_sata_chip_map(sc, pa, 6);
   1009 }
   1010 
   1011 static void
   1012 via_sata_chip_map_7(struct pciide_softc *sc, const struct pci_attach_args *pa)
   1013 {
   1014 	via_sata_chip_map(sc, pa, 7);
   1015 }
   1016 
   1017 static void
   1018 via_vt6421_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa)
   1019 {
   1020 	struct pciide_channel *pc;
   1021 	int chan, reg;
   1022 	bus_size_t size;
   1023 
   1024 	sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA,
   1025 	    PCI_MAPREG_TYPE_IO, 0, &sc->sc_dma_iot, &sc->sc_dma_ioh,
   1026 	    NULL, &sc->sc_dma_ios) == 0);
   1027 	sc->sc_dmat = pa->pa_dmat;
   1028 	if (sc->sc_dma_ok == 0) {
   1029 		aprint_verbose(", but unused (couldn't map registers)");
   1030 	} else {
   1031 		sc->sc_wdcdev.dma_arg = sc;
   1032 		sc->sc_wdcdev.dma_init = pciide_dma_init;
   1033 		sc->sc_wdcdev.dma_start = pciide_dma_start;
   1034 		sc->sc_wdcdev.dma_finish = pciide_dma_finish;
   1035 	}
   1036 
   1037 	if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
   1038 	    PCIIDE_OPTIONS_NODMA) {
   1039 		aprint_verbose(
   1040 		    ", but unused (forced off by config file)");
   1041 		sc->sc_dma_ok = 0;
   1042 	}
   1043 
   1044 	if (sc->sc_dma_ok == 0)
   1045 		return;
   1046 
   1047 	for (chan = 0; chan < 4; chan++) {
   1048 		pc = &sc->pciide_channels[chan];
   1049 		for (reg = 0; reg < IDEDMA_NREGS; reg++) {
   1050 			size = 4;
   1051 			if (size > (IDEDMA_SCH_OFFSET - reg))
   1052 				size = IDEDMA_SCH_OFFSET - reg;
   1053 			if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh,
   1054 			    IDEDMA_SCH_OFFSET * chan + reg, size,
   1055 			    &pc->dma_iohs[reg]) != 0) {
   1056 				sc->sc_dma_ok = 0;
   1057 				aprint_verbose(", but can't subregion offset "
   1058 				               "%d size %lu",
   1059 					       reg, (u_long)size);
   1060 				return;
   1061 			}
   1062 		}
   1063 	}
   1064 }
   1065 
   1066 static int
   1067 via_vt6421_chansetup(struct pciide_softc *sc, int channel)
   1068 {
   1069 	struct pciide_channel *cp = &sc->pciide_channels[channel];
   1070 
   1071 	sc->wdc_chanarray[channel] = &cp->ata_channel;
   1072 
   1073 	cp->ata_channel.ch_channel = channel;
   1074 	cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
   1075 
   1076 	return 1;
   1077 }
   1078 
   1079 static void
   1080 via_sata_chip_map_new(struct pciide_softc *sc,
   1081     const struct pci_attach_args *pa)
   1082 {
   1083 	struct pciide_channel *cp;
   1084 	struct ata_channel *wdc_cp;
   1085 	struct wdc_regs *wdr;
   1086 	int channel;
   1087 	pci_intr_handle_t intrhandle;
   1088 	const char *intrstr;
   1089 	int i;
   1090 	char intrbuf[PCI_INTRSTR_LEN];
   1091 
   1092 	if (pciide_chipen(sc, pa) == 0)
   1093 		return;
   1094 
   1095 	sc->sc_apo_regbase = APO_VIA_VT6421_REGBASE;
   1096 
   1097 	if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0,
   1098 	    &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) {
   1099 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
   1100 		    "couldn't map SATA regs\n");
   1101 	}
   1102 
   1103 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
   1104 	    "bus-master DMA support present");
   1105 	via_vt6421_mapreg_dma(sc, pa);
   1106 	aprint_verbose("\n");
   1107 
   1108 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
   1109 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
   1110 	if (sc->sc_dma_ok) {
   1111 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
   1112 		sc->sc_wdcdev.irqack = pciide_irqack;
   1113 		sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
   1114 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
   1115 	}
   1116 	sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
   1117 
   1118 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
   1119 	sc->sc_wdcdev.sc_atac.atac_nchannels = 3;
   1120 	sc->sc_wdcdev.wdc_maxdrives = 2;
   1121 
   1122 	wdc_allocate_regs(&sc->sc_wdcdev);
   1123 
   1124 	if (pci_intr_map(pa, &intrhandle) != 0) {
   1125 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
   1126 		    "couldn't map native-PCI interrupt\n");
   1127 		return;
   1128 	}
   1129 	intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf));
   1130 	sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
   1131 	    intrhandle, IPL_BIO, pciide_pci_intr, sc);
   1132 	if (sc->sc_pci_ih == NULL) {
   1133 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
   1134 		    "couldn't establish native-PCI interrupt");
   1135 		if (intrstr != NULL)
   1136 		    aprint_error(" at %s", intrstr);
   1137 		aprint_error("\n");
   1138 		return;
   1139 	}
   1140 	aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
   1141 	    "using %s for native-PCI interrupt\n",
   1142 	    intrstr ? intrstr : "unknown interrupt");
   1143 
   1144 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
   1145 	     channel++) {
   1146 		cp = &sc->pciide_channels[channel];
   1147 		if (via_vt6421_chansetup(sc, channel) == 0)
   1148 			continue;
   1149 		wdc_cp = &cp->ata_channel;
   1150 		wdr = CHAN_TO_WDC_REGS(wdc_cp);
   1151 
   1152 		wdr->sata_iot = sc->sc_ba5_st;
   1153 		wdr->sata_baseioh = sc->sc_ba5_sh;
   1154 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
   1155 		    (wdc_cp->ch_channel << 6) + 0x0, 4,
   1156 		    &wdr->sata_status) != 0) {
   1157 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
   1158 			    "couldn't map channel %d sata_status regs\n",
   1159 			    wdc_cp->ch_channel);
   1160 			continue;
   1161 		}
   1162 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
   1163 		    (wdc_cp->ch_channel << 6) + 0x4, 4,
   1164 		    &wdr->sata_error) != 0) {
   1165 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
   1166 			    "couldn't map channel %d sata_error regs\n",
   1167 			    wdc_cp->ch_channel);
   1168 			continue;
   1169 		}
   1170 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
   1171 		    (wdc_cp->ch_channel << 6) + 0x8, 4,
   1172 		    &wdr->sata_control) != 0) {
   1173 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
   1174 			    "couldn't map channel %d sata_control regs\n",
   1175 			    wdc_cp->ch_channel);
   1176 			continue;
   1177 		}
   1178 
   1179 		if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel),
   1180 		    PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh,
   1181 		    NULL, &wdr->cmd_ios) != 0) {
   1182 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
   1183 			    "couldn't map %s channel regs\n", cp->name);
   1184 		}
   1185 		wdr->ctl_iot = wdr->cmd_iot;
   1186 		for (i = 0; i < WDC_NREG; i++) {
   1187 			if (bus_space_subregion(wdr->cmd_iot,
   1188 			    wdr->cmd_baseioh, i, i == 0 ? 4 : 1,
   1189 			    &wdr->cmd_iohs[i]) != 0) {
   1190 				aprint_error_dev(
   1191 				    sc->sc_wdcdev.sc_atac.atac_dev,
   1192 				    "couldn't subregion %s "
   1193 				    "channel cmd regs\n", cp->name);
   1194 				return;
   1195 			}
   1196 		}
   1197 		if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
   1198 		    WDC_NREG + 2, 1,  &wdr->ctl_ioh) != 0) {
   1199 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
   1200 			    "couldn't map channel %d ctl regs\n", channel);
   1201 			return;
   1202 		}
   1203 		wdc_init_shadow_regs(wdr);
   1204 		wdr->data32iot = wdr->cmd_iot;
   1205 		wdr->data32ioh = wdr->cmd_iohs[wd_data];
   1206 		wdcattach(wdc_cp);
   1207 	}
   1208 }
   1209