viaide.c revision 1.85
1 /* $NetBSD: viaide.c,v 1.85 2017/10/07 16:05:33 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.85 2017/10/07 16:05:33 jdolecek Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/pci/pciide_apollo_reg.h> 39 40 static int via_pcib_match(const struct pci_attach_args *); 41 static void via_chip_map(struct pciide_softc *, 42 const struct pci_attach_args *); 43 static void via_mapchan(const struct pci_attach_args *, 44 struct pciide_channel *, 45 pcireg_t, int (*)(void *)); 46 static void via_mapregs_compat_native(const struct pci_attach_args *, 47 struct pciide_channel *); 48 static int via_sata_chip_map_common(struct pciide_softc *, 49 const struct pci_attach_args *); 50 static void via_sata_chip_map(struct pciide_softc *, 51 const struct pci_attach_args *, int); 52 static void via_sata_chip_map_6(struct pciide_softc *, 53 const struct pci_attach_args *); 54 static void via_sata_chip_map_7(struct pciide_softc *, 55 const struct pci_attach_args *); 56 static void via_sata_chip_map_new(struct pciide_softc *, 57 const struct pci_attach_args *); 58 static void via_setup_channel(struct ata_channel *); 59 60 static int viaide_match(device_t, cfdata_t, void *); 61 static void viaide_attach(device_t, device_t, void *); 62 static const struct pciide_product_desc * 63 viaide_lookup(pcireg_t); 64 static bool viaide_suspend(device_t, const pmf_qual_t *); 65 static bool viaide_resume(device_t, const pmf_qual_t *); 66 67 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 68 viaide_match, viaide_attach, pciide_detach, NULL); 69 70 static const struct pciide_product_desc pciide_amd_products[] = { 71 { PCI_PRODUCT_AMD_PBC756_IDE, 72 0, 73 "AMD AMD756 IDE Controller", 74 via_chip_map 75 }, 76 { PCI_PRODUCT_AMD_PBC766_IDE, 77 0, 78 "AMD AMD766 IDE Controller", 79 via_chip_map 80 }, 81 { PCI_PRODUCT_AMD_PBC768_IDE, 82 0, 83 "AMD AMD768 IDE Controller", 84 via_chip_map 85 }, 86 { PCI_PRODUCT_AMD_PBC8111_IDE, 87 0, 88 "AMD AMD8111 IDE Controller", 89 via_chip_map 90 }, 91 { PCI_PRODUCT_AMD_CS5536_IDE, 92 0, 93 "AMD CS5536 IDE Controller", 94 via_chip_map 95 }, 96 { 0, 97 0, 98 NULL, 99 NULL 100 } 101 }; 102 103 static const struct pciide_product_desc pciide_nvidia_products[] = { 104 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 105 0, 106 "NVIDIA nForce IDE Controller", 107 via_chip_map 108 }, 109 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 110 0, 111 "NVIDIA nForce2 IDE Controller", 112 via_chip_map 113 }, 114 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 115 0, 116 "NVIDIA nForce2 Ultra 400 IDE Controller", 117 via_chip_map 118 }, 119 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 120 0, 121 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 122 via_sata_chip_map_6 123 }, 124 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 125 0, 126 "NVIDIA nForce3 IDE Controller", 127 via_chip_map 128 }, 129 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 130 0, 131 "NVIDIA nForce3 250 IDE Controller", 132 via_chip_map 133 }, 134 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 135 0, 136 "NVIDIA nForce3 250 Serial ATA Controller", 137 via_sata_chip_map_6 138 }, 139 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 140 0, 141 "NVIDIA nForce3 250 Serial ATA Controller", 142 via_sata_chip_map_6 143 }, 144 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 145 0, 146 "NVIDIA nForce4 IDE Controller", 147 via_chip_map 148 }, 149 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 150 0, 151 "NVIDIA nForce4 Serial ATA Controller", 152 via_sata_chip_map_6 153 }, 154 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 155 0, 156 "NVIDIA nForce4 Serial ATA Controller", 157 via_sata_chip_map_6 158 }, 159 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 160 0, 161 "NVIDIA nForce430 IDE Controller", 162 via_chip_map 163 }, 164 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 165 0, 166 "NVIDIA nForce430 Serial ATA Controller", 167 via_sata_chip_map_6 168 }, 169 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 170 0, 171 "NVIDIA nForce430 Serial ATA Controller", 172 via_sata_chip_map_6 173 }, 174 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 175 0, 176 "NVIDIA MCP04 IDE Controller", 177 via_chip_map 178 }, 179 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 180 0, 181 "NVIDIA MCP04 Serial ATA Controller", 182 via_sata_chip_map_6 183 }, 184 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 185 0, 186 "NVIDIA MCP04 Serial ATA Controller", 187 via_sata_chip_map_6 188 }, 189 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 190 0, 191 "NVIDIA MCP55 IDE Controller", 192 via_chip_map 193 }, 194 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 195 0, 196 "NVIDIA MCP55 Serial ATA Controller", 197 via_sata_chip_map_6 198 }, 199 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 200 0, 201 "NVIDIA MCP55 Serial ATA Controller", 202 via_sata_chip_map_6 203 }, 204 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 205 0, 206 "NVIDIA MCP61 IDE Controller", 207 via_chip_map 208 }, 209 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 210 0, 211 "NVIDIA MCP65 IDE Controller", 212 via_chip_map 213 }, 214 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 215 0, 216 "NVIDIA MCP73 IDE Controller", 217 via_chip_map 218 }, 219 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 220 0, 221 "NVIDIA MCP77 IDE Controller", 222 via_chip_map 223 }, 224 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 225 0, 226 "NVIDIA MCP61 Serial ATA Controller", 227 via_sata_chip_map_6 228 }, 229 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 230 0, 231 "NVIDIA MCP61 Serial ATA Controller", 232 via_sata_chip_map_6 233 }, 234 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 235 0, 236 "NVIDIA MCP61 Serial ATA Controller", 237 via_sata_chip_map_6 238 }, 239 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 240 0, 241 "NVIDIA MCP65 Serial ATA Controller", 242 via_sata_chip_map_6 243 }, 244 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 245 0, 246 "NVIDIA MCP65 Serial ATA Controller", 247 via_sata_chip_map_6 248 }, 249 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 250 0, 251 "NVIDIA MCP65 Serial ATA Controller", 252 via_sata_chip_map_6 253 }, 254 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 255 0, 256 "NVIDIA MCP65 Serial ATA Controller", 257 via_sata_chip_map_6 258 }, 259 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 260 0, 261 "NVIDIA MCP67 IDE Controller", 262 via_chip_map, 263 }, 264 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 265 0, 266 "NVIDIA MCP67 Serial ATA Controller", 267 via_sata_chip_map_6, 268 }, 269 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 270 0, 271 "NVIDIA MCP67 Serial ATA Controller", 272 via_sata_chip_map_6, 273 }, 274 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 275 0, 276 "NVIDIA MCP67 Serial ATA Controller", 277 via_sata_chip_map_6, 278 }, 279 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 280 0, 281 "NVIDIA MCP67 Serial ATA Controller", 282 via_sata_chip_map_6, 283 }, 284 { 0, 285 0, 286 NULL, 287 NULL 288 } 289 }; 290 291 static const struct pciide_product_desc pciide_via_products[] = { 292 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 293 0, 294 NULL, 295 via_chip_map, 296 }, 297 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 298 0, 299 NULL, 300 via_chip_map, 301 }, 302 { PCI_PRODUCT_VIATECH_CX700_IDE, 303 0, 304 NULL, 305 via_chip_map, 306 }, 307 { PCI_PRODUCT_VIATECH_CX700M2_IDE, 308 0, 309 NULL, 310 via_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_VX900_IDE, 313 0, 314 NULL, 315 via_chip_map, 316 }, 317 { PCI_PRODUCT_VIATECH_VT6410_RAID, 318 0, 319 NULL, 320 via_chip_map, 321 }, 322 { PCI_PRODUCT_VIATECH_VT6421_RAID, 323 0, 324 "VIA Technologies VT6421 Serial ATA RAID Controller", 325 via_sata_chip_map_new, 326 }, 327 { PCI_PRODUCT_VIATECH_VT8237_SATA, 328 0, 329 "VIA Technologies VT8237 SATA Controller", 330 via_sata_chip_map_7, 331 }, 332 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 333 0, 334 "VIA Technologies VT8237A SATA Controller", 335 via_sata_chip_map_7, 336 }, 337 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, 338 0, 339 "VIA Technologies VT8237A (5337) SATA Controller", 340 via_sata_chip_map_7, 341 }, 342 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 343 0, 344 "VIA Technologies VT8237R SATA Controller", 345 via_sata_chip_map_7, 346 }, 347 { PCI_PRODUCT_VIATECH_VT8237S_SATA, 348 0, 349 "VIA Technologies VT8237S SATA Controller", 350 via_sata_chip_map_7, 351 }, 352 { 0, 353 0, 354 NULL, 355 NULL 356 } 357 }; 358 359 static const struct pciide_product_desc * 360 viaide_lookup(pcireg_t id) 361 { 362 363 switch (PCI_VENDOR(id)) { 364 case PCI_VENDOR_VIATECH: 365 return (pciide_lookup_product(id, pciide_via_products)); 366 367 case PCI_VENDOR_AMD: 368 return (pciide_lookup_product(id, pciide_amd_products)); 369 370 case PCI_VENDOR_NVIDIA: 371 return (pciide_lookup_product(id, pciide_nvidia_products)); 372 } 373 return (NULL); 374 } 375 376 static int 377 viaide_match(device_t parent, cfdata_t match, void *aux) 378 { 379 const struct pci_attach_args *pa = aux; 380 381 if (viaide_lookup(pa->pa_id) != NULL) 382 return (2); 383 return (0); 384 } 385 386 static void 387 viaide_attach(device_t parent, device_t self, void *aux) 388 { 389 const struct pci_attach_args *pa = aux; 390 struct pciide_softc *sc = device_private(self); 391 const struct pciide_product_desc *pp; 392 393 sc->sc_wdcdev.sc_atac.atac_dev = self; 394 395 pp = viaide_lookup(pa->pa_id); 396 if (pp == NULL) 397 panic("viaide_attach"); 398 pciide_common_attach(sc, pa, pp); 399 400 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 401 aprint_error_dev(self, "couldn't establish power handler\n"); 402 } 403 404 static int 405 via_pcib_match(const struct pci_attach_args *pa) 406 { 407 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 408 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 409 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 410 return (1); 411 return 0; 412 } 413 414 static bool 415 viaide_suspend(device_t dv, const pmf_qual_t *qual) 416 { 417 struct pciide_softc *sc = device_private(dv); 418 419 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 420 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 421 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 422 /* This two are VIA-only, but should be ignored by other devices. */ 423 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 424 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 425 426 return true; 427 } 428 429 static bool 430 viaide_resume(device_t dv, const pmf_qual_t *qual) 431 { 432 struct pciide_softc *sc = device_private(dv); 433 434 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 435 sc->sc_pm_reg[0]); 436 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 437 sc->sc_pm_reg[1]); 438 /* This two are VIA-only, but should be ignored by other devices. */ 439 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 440 sc->sc_pm_reg[2]); 441 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 442 sc->sc_pm_reg[3]); 443 444 return true; 445 } 446 447 static void 448 via_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 449 { 450 struct pciide_channel *cp; 451 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 452 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 453 int channel; 454 u_int32_t ideconf; 455 pcireg_t pcib_id, pcib_class; 456 struct pci_attach_args pcib_pa; 457 458 if (pciide_chipen(sc, pa) == 0) 459 return; 460 461 switch (vendor) { 462 case PCI_VENDOR_VIATECH: 463 switch (PCI_PRODUCT(pa->pa_id)) { 464 case PCI_PRODUCT_VIATECH_VT6410_RAID: 465 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 466 "VIA Technologies VT6410 IDE controller\n"); 467 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 468 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 469 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 470 break; 471 case PCI_PRODUCT_VIATECH_VX900_IDE: 472 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 473 "VIA Technologies VX900 ATA133 controller\n"); 474 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 475 break; 476 default: 477 /* 478 * get a PCI tag for the ISA bridge. 479 */ 480 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 481 goto unknown; 482 pcib_id = pcib_pa.pa_id; 483 pcib_class = pcib_pa.pa_class; 484 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 485 "VIA Technologies "); 486 switch (PCI_PRODUCT(pcib_id)) { 487 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 488 aprint_normal("VT82C586 (Apollo VP) "); 489 if(PCI_REVISION(pcib_class) >= 0x02) { 490 aprint_normal("ATA33 controller\n"); 491 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 492 } else { 493 aprint_normal("controller\n"); 494 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 495 } 496 break; 497 case PCI_PRODUCT_VIATECH_VT82C596A: 498 aprint_normal("VT82C596A (Apollo Pro) "); 499 if (PCI_REVISION(pcib_class) >= 0x12) { 500 aprint_normal("ATA66 controller\n"); 501 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 502 } else { 503 aprint_normal("ATA33 controller\n"); 504 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 505 } 506 break; 507 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 508 aprint_normal("VT82C686A (Apollo KX133) "); 509 if (PCI_REVISION(pcib_class) >= 0x40) { 510 aprint_normal("ATA100 controller\n"); 511 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 512 } else { 513 aprint_normal("ATA66 controller\n"); 514 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 515 } 516 break; 517 case PCI_PRODUCT_VIATECH_VT8231: 518 aprint_normal("VT8231 ATA100 controller\n"); 519 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 520 break; 521 case PCI_PRODUCT_VIATECH_VT8233: 522 aprint_normal("VT8233 ATA100 controller\n"); 523 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 524 break; 525 case PCI_PRODUCT_VIATECH_VT8233A: 526 aprint_normal("VT8233A ATA133 controller\n"); 527 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 528 break; 529 case PCI_PRODUCT_VIATECH_VT8235: 530 aprint_normal("VT8235 ATA133 controller\n"); 531 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 532 break; 533 case PCI_PRODUCT_VIATECH_VT8237: 534 aprint_normal("VT8237 ATA133 controller\n"); 535 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 536 break; 537 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 538 aprint_normal("VT8237A ATA133 controller\n"); 539 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 540 break; 541 case PCI_PRODUCT_VIATECH_CX700: 542 aprint_normal("CX700 ATA133 controller\n"); 543 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 544 break; 545 case PCI_PRODUCT_VIATECH_VT8251: 546 aprint_normal("VT8251 ATA133 controller\n"); 547 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 548 break; 549 default: 550 unknown: 551 aprint_normal("unknown VIA ATA controller\n"); 552 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 553 } 554 break; 555 } 556 sc->sc_apo_regbase = APO_VIA_REGBASE; 557 break; 558 case PCI_VENDOR_AMD: 559 switch (sc->sc_pp->ide_product) { 560 case PCI_PRODUCT_AMD_PBC8111_IDE: 561 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 562 break; 563 case PCI_PRODUCT_AMD_CS5536_IDE: 564 case PCI_PRODUCT_AMD_PBC766_IDE: 565 case PCI_PRODUCT_AMD_PBC768_IDE: 566 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 567 break; 568 default: 569 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 570 } 571 sc->sc_apo_regbase = APO_AMD_REGBASE; 572 break; 573 case PCI_VENDOR_NVIDIA: 574 switch (sc->sc_pp->ide_product) { 575 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 576 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 577 break; 578 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 579 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 580 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 581 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 582 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 583 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 584 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 585 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 586 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 587 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 588 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 589 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 590 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 591 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 592 break; 593 } 594 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 595 break; 596 default: 597 panic("via_chip_map: unknown vendor"); 598 } 599 600 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 601 "bus-master DMA support present"); 602 pciide_mapreg_dma(sc, pa); 603 aprint_verbose("\n"); 604 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 605 if (sc->sc_dma_ok) { 606 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 607 sc->sc_wdcdev.irqack = pciide_irqack; 608 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 609 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 610 } 611 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 612 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 613 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 614 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 615 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 616 sc->sc_wdcdev.wdc_maxdrives = 2; 617 618 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 619 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 620 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 621 622 wdc_allocate_regs(&sc->sc_wdcdev); 623 624 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 625 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 626 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 627 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 628 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 629 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 630 DEBUG_PROBE); 631 632 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 633 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 634 channel++) { 635 cp = &sc->pciide_channels[channel]; 636 if (pciide_chansetup(sc, channel, interface) == 0) 637 continue; 638 639 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 640 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 641 "%s channel ignored (disabled)\n", cp->name); 642 cp->ata_channel.ch_flags |= ATACH_DISABLED; 643 continue; 644 } 645 via_mapchan(pa, cp, interface, pciide_pci_intr); 646 } 647 } 648 649 static void 650 via_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp, 651 pcireg_t interface, int (*pci_intr)(void *)) 652 { 653 struct ata_channel *wdc_cp; 654 struct pciide_softc *sc; 655 prop_bool_t compat_nat_enable; 656 657 wdc_cp = &cp->ata_channel; 658 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 659 compat_nat_enable = prop_dictionary_get( 660 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 661 "use-compat-native-irq"); 662 663 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 664 /* native mode with irq 14/15 requested? */ 665 if (compat_nat_enable != NULL && 666 prop_bool_true(compat_nat_enable)) 667 via_mapregs_compat_native(pa, cp); 668 else 669 pciide_mapregs_native(pa, cp, pci_intr); 670 } else { 671 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 672 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 673 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 674 } 675 wdcattach(wdc_cp); 676 } 677 678 /* 679 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 680 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 681 * programmed to use a single native PCI irq alone. So we install an interrupt 682 * handler for each channel, as in compatibility mode. 683 */ 684 static void 685 via_mapregs_compat_native(const struct pci_attach_args *pa, 686 struct pciide_channel *cp) 687 { 688 struct ata_channel *wdc_cp; 689 struct pciide_softc *sc; 690 691 wdc_cp = &cp->ata_channel; 692 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 693 694 /* XXX prevent pciide_mapregs_native from installing a handler */ 695 if (sc->sc_pci_ih == NULL) 696 sc->sc_pci_ih = (void *)~0; 697 pciide_mapregs_native(pa, cp, NULL); 698 699 /* interrupts are fixed to 14/15, as in compatibility mode */ 700 cp->compat = 1; 701 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 702 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 703 cp->ih = pciide_machdep_compat_intr_establish( 704 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 705 pciide_compat_intr, cp); 706 if (cp->ih == NULL) { 707 #endif 708 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 709 "no compatibility interrupt for " 710 "use by %s channel\n", cp->name); 711 wdc_cp->ch_flags |= ATACH_DISABLED; 712 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 713 } 714 sc->sc_pci_ih = cp->ih; /* XXX */ 715 #endif 716 } 717 } 718 719 static void 720 via_setup_channel(struct ata_channel *chp) 721 { 722 u_int32_t udmatim_reg, datatim_reg; 723 u_int8_t idedma_ctl; 724 int mode, drive, s; 725 struct ata_drive_datas *drvp; 726 struct atac_softc *atac = chp->ch_atac; 727 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 728 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 729 #ifndef PCIIDE_AMD756_ENABLEDMA 730 int rev = PCI_REVISION( 731 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 732 #endif 733 734 idedma_ctl = 0; 735 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 736 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 737 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 738 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 739 740 /* setup DMA if needed */ 741 pciide_channel_dma_setup(cp); 742 743 for (drive = 0; drive < 2; drive++) { 744 drvp = &chp->ch_drive[drive]; 745 /* If no drive, skip */ 746 if (drvp->drive_type == ATA_DRIVET_NONE) 747 continue; 748 /* add timing values, setup DMA if needed */ 749 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 750 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0)) { 751 mode = drvp->PIO_mode; 752 goto pio; 753 } 754 if ((atac->atac_cap & ATAC_CAP_UDMA) && 755 (drvp->drive_flags & ATA_DRIVE_UDMA)) { 756 /* use Ultra/DMA */ 757 s = splbio(); 758 drvp->drive_flags &= ~ATA_DRIVE_DMA; 759 splx(s); 760 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 761 APO_UDMA_EN_MTH(chp->ch_channel, drive); 762 switch (PCI_VENDOR(sc->sc_pci_id)) { 763 case PCI_VENDOR_VIATECH: 764 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 765 /* 8233a */ 766 udmatim_reg |= APO_UDMA_TIME( 767 chp->ch_channel, 768 drive, 769 via_udma133_tim[drvp->UDMA_mode]); 770 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 771 /* 686b */ 772 udmatim_reg |= APO_UDMA_TIME( 773 chp->ch_channel, 774 drive, 775 via_udma100_tim[drvp->UDMA_mode]); 776 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 777 /* 596b or 686a */ 778 udmatim_reg |= APO_UDMA_CLK66( 779 chp->ch_channel); 780 udmatim_reg |= APO_UDMA_TIME( 781 chp->ch_channel, 782 drive, 783 via_udma66_tim[drvp->UDMA_mode]); 784 } else { 785 /* 596a or 586b */ 786 udmatim_reg |= APO_UDMA_TIME( 787 chp->ch_channel, 788 drive, 789 via_udma33_tim[drvp->UDMA_mode]); 790 } 791 break; 792 case PCI_VENDOR_AMD: 793 case PCI_VENDOR_NVIDIA: 794 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 795 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 796 break; 797 } 798 /* can use PIO timings, MW DMA unused */ 799 mode = drvp->PIO_mode; 800 } else { 801 /* use Multiword DMA, but only if revision is OK */ 802 s = splbio(); 803 drvp->drive_flags &= ~ATA_DRIVE_UDMA; 804 splx(s); 805 #ifndef PCIIDE_AMD756_ENABLEDMA 806 /* 807 * The workaround doesn't seem to be necessary 808 * with all drives, so it can be disabled by 809 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 810 * triggered. 811 */ 812 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 813 sc->sc_pp->ide_product == 814 PCI_PRODUCT_AMD_PBC756_IDE && 815 AMD756_CHIPREV_DISABLEDMA(rev)) { 816 aprint_normal( 817 "%s:%d:%d: multi-word DMA disabled due " 818 "to chip revision\n", 819 device_xname( 820 sc->sc_wdcdev.sc_atac.atac_dev), 821 chp->ch_channel, drive); 822 mode = drvp->PIO_mode; 823 s = splbio(); 824 drvp->drive_flags &= ~ATA_DRIVE_DMA; 825 splx(s); 826 goto pio; 827 } 828 #endif 829 /* mode = min(pio, dma+2) */ 830 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 831 mode = drvp->PIO_mode; 832 else 833 mode = drvp->DMA_mode + 2; 834 } 835 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 836 837 pio: /* setup PIO mode */ 838 if (mode <= 2) { 839 drvp->DMA_mode = 0; 840 drvp->PIO_mode = 0; 841 mode = 0; 842 } else { 843 drvp->PIO_mode = mode; 844 drvp->DMA_mode = mode - 2; 845 } 846 datatim_reg |= 847 APO_DATATIM_PULSE(chp->ch_channel, drive, 848 apollo_pio_set[mode]) | 849 APO_DATATIM_RECOV(chp->ch_channel, drive, 850 apollo_pio_rec[mode]); 851 } 852 if (idedma_ctl != 0) { 853 /* Add software bits in status register */ 854 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 855 idedma_ctl); 856 } 857 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 858 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 859 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 860 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 861 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 862 } 863 864 static int 865 via_sata_chip_map_common(struct pciide_softc *sc, 866 const struct pci_attach_args *cpa) 867 { 868 pcireg_t csr; 869 int maptype, ret; 870 struct pci_attach_args pac, *pa = &pac; 871 872 pac = *cpa; 873 874 if (pciide_chipen(sc, pa) == 0) 875 return 0; 876 877 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 878 "bus-master DMA support present"); 879 pciide_mapreg_dma(sc, pa); 880 aprint_verbose("\n"); 881 882 if (sc->sc_dma_ok) { 883 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 884 sc->sc_wdcdev.irqack = pciide_irqack; 885 } 886 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 887 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 888 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 889 890 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 891 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 892 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 893 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 894 sc->sc_wdcdev.wdc_maxdrives = 2; 895 896 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 897 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 898 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 899 900 wdc_allocate_regs(&sc->sc_wdcdev); 901 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 902 PCI_MAPREG_START + 0x14); 903 switch(maptype) { 904 case PCI_MAPREG_TYPE_IO: 905 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 906 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 907 NULL, &sc->sc_ba5_ss); 908 break; 909 case PCI_MAPREG_MEM_TYPE_32BIT: 910 /* 911 * Enable memory-space access if it isn't already there. 912 */ 913 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, 914 PCI_COMMAND_STATUS_REG); 915 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 && 916 (pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) { 917 918 pci_conf_write(pa->pa_pc, pa->pa_tag, 919 PCI_COMMAND_STATUS_REG, 920 csr | PCI_COMMAND_MEM_ENABLE); 921 } 922 923 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 924 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 925 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 926 NULL, &sc->sc_ba5_ss); 927 break; 928 default: 929 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 930 "couldn't map sata regs, unsupported maptype (0x%x)\n", 931 maptype); 932 return 0; 933 } 934 if (ret != 0) { 935 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 936 "couldn't map sata regs\n"); 937 return 0; 938 } 939 return 1; 940 } 941 942 static void 943 via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa, 944 int satareg_shift) 945 { 946 struct pciide_channel *cp; 947 struct ata_channel *wdc_cp; 948 struct wdc_regs *wdr; 949 pcireg_t interface; 950 int channel; 951 952 interface = PCI_INTERFACE(pa->pa_class); 953 954 if (via_sata_chip_map_common(sc, pa) == 0) 955 return; 956 957 if (interface == 0) { 958 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 959 DEBUG_PROBE); 960 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 961 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 962 } 963 964 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 965 sc->sc_wdcdev.wdc_maxdrives = 1; 966 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 967 channel++) { 968 cp = &sc->pciide_channels[channel]; 969 if (pciide_chansetup(sc, channel, interface) == 0) 970 continue; 971 wdc_cp = &cp->ata_channel; 972 wdr = CHAN_TO_WDC_REGS(wdc_cp); 973 wdr->sata_iot = sc->sc_ba5_st; 974 wdr->sata_baseioh = sc->sc_ba5_sh; 975 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 976 (wdc_cp->ch_channel << satareg_shift) + 0x0, 4, 977 &wdr->sata_status) != 0) { 978 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 979 "couldn't map channel %d sata_status regs\n", 980 wdc_cp->ch_channel); 981 continue; 982 } 983 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 984 (wdc_cp->ch_channel << satareg_shift) + 0x4, 4, 985 &wdr->sata_error) != 0) { 986 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 987 "couldn't map channel %d sata_error regs\n", 988 wdc_cp->ch_channel); 989 continue; 990 } 991 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 992 (wdc_cp->ch_channel << satareg_shift) + 0x8, 4, 993 &wdr->sata_control) != 0) { 994 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 995 "couldn't map channel %d sata_control regs\n", 996 wdc_cp->ch_channel); 997 continue; 998 } 999 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 1000 } 1001 } 1002 1003 static void 1004 via_sata_chip_map_6(struct pciide_softc *sc, const struct pci_attach_args *pa) 1005 { 1006 via_sata_chip_map(sc, pa, 6); 1007 } 1008 1009 static void 1010 via_sata_chip_map_7(struct pciide_softc *sc, const struct pci_attach_args *pa) 1011 { 1012 via_sata_chip_map(sc, pa, 7); 1013 } 1014 1015 static void 1016 via_vt6421_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 1017 { 1018 struct pciide_channel *pc; 1019 int chan, reg; 1020 bus_size_t size; 1021 1022 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 1023 PCI_MAPREG_TYPE_IO, 0, &sc->sc_dma_iot, &sc->sc_dma_ioh, 1024 NULL, &sc->sc_dma_ios) == 0); 1025 sc->sc_dmat = pa->pa_dmat; 1026 if (sc->sc_dma_ok == 0) { 1027 aprint_verbose(", but unused (couldn't map registers)"); 1028 } else { 1029 sc->sc_wdcdev.dma_arg = sc; 1030 sc->sc_wdcdev.dma_init = pciide_dma_init; 1031 sc->sc_wdcdev.dma_start = pciide_dma_start; 1032 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 1033 } 1034 1035 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 1036 PCIIDE_OPTIONS_NODMA) { 1037 aprint_verbose( 1038 ", but unused (forced off by config file)"); 1039 sc->sc_dma_ok = 0; 1040 } 1041 1042 if (sc->sc_dma_ok == 0) 1043 return; 1044 1045 for (chan = 0; chan < 4; chan++) { 1046 pc = &sc->pciide_channels[chan]; 1047 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 1048 size = 4; 1049 if (size > (IDEDMA_SCH_OFFSET - reg)) 1050 size = IDEDMA_SCH_OFFSET - reg; 1051 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 1052 IDEDMA_SCH_OFFSET * chan + reg, size, 1053 &pc->dma_iohs[reg]) != 0) { 1054 sc->sc_dma_ok = 0; 1055 aprint_verbose(", but can't subregion offset " 1056 "%d size %lu", 1057 reg, (u_long)size); 1058 return; 1059 } 1060 } 1061 } 1062 } 1063 1064 static int 1065 via_vt6421_chansetup(struct pciide_softc *sc, int channel) 1066 { 1067 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1068 1069 sc->wdc_chanarray[channel] = &cp->ata_channel; 1070 1071 cp->ata_channel.ch_channel = channel; 1072 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 1073 cp->ata_channel.ch_queue = ata_queue_alloc(1); 1074 if (cp->ata_channel.ch_queue == NULL) { 1075 aprint_error("%s channel %d: " 1076 "can't allocate memory for command queue", 1077 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel); 1078 return 0; 1079 } 1080 return 1; 1081 } 1082 1083 static void 1084 via_sata_chip_map_new(struct pciide_softc *sc, 1085 const struct pci_attach_args *pa) 1086 { 1087 struct pciide_channel *cp; 1088 struct ata_channel *wdc_cp; 1089 struct wdc_regs *wdr; 1090 int channel; 1091 pci_intr_handle_t intrhandle; 1092 const char *intrstr; 1093 int i; 1094 char intrbuf[PCI_INTRSTR_LEN]; 1095 1096 if (pciide_chipen(sc, pa) == 0) 1097 return; 1098 1099 sc->sc_apo_regbase = APO_VIA_VT6421_REGBASE; 1100 1101 if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0, 1102 &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 1103 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1104 "couldn't map SATA regs\n"); 1105 } 1106 1107 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1108 "bus-master DMA support present"); 1109 via_vt6421_mapreg_dma(sc, pa); 1110 aprint_verbose("\n"); 1111 1112 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 1113 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 1114 if (sc->sc_dma_ok) { 1115 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 1116 sc->sc_wdcdev.irqack = pciide_irqack; 1117 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 1118 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 1119 } 1120 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 1121 1122 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 1123 sc->sc_wdcdev.sc_atac.atac_nchannels = 3; 1124 sc->sc_wdcdev.wdc_maxdrives = 2; 1125 1126 wdc_allocate_regs(&sc->sc_wdcdev); 1127 1128 if (pci_intr_map(pa, &intrhandle) != 0) { 1129 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1130 "couldn't map native-PCI interrupt\n"); 1131 return; 1132 } 1133 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 1134 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 1135 intrhandle, IPL_BIO, pciide_pci_intr, sc); 1136 if (sc->sc_pci_ih == NULL) { 1137 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1138 "couldn't establish native-PCI interrupt"); 1139 if (intrstr != NULL) 1140 aprint_error(" at %s", intrstr); 1141 aprint_error("\n"); 1142 return; 1143 } 1144 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1145 "using %s for native-PCI interrupt\n", 1146 intrstr ? intrstr : "unknown interrupt"); 1147 1148 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1149 channel++) { 1150 cp = &sc->pciide_channels[channel]; 1151 if (via_vt6421_chansetup(sc, channel) == 0) 1152 continue; 1153 wdc_cp = &cp->ata_channel; 1154 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1155 1156 wdr->sata_iot = sc->sc_ba5_st; 1157 wdr->sata_baseioh = sc->sc_ba5_sh; 1158 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1159 (wdc_cp->ch_channel << 6) + 0x0, 4, 1160 &wdr->sata_status) != 0) { 1161 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1162 "couldn't map channel %d sata_status regs\n", 1163 wdc_cp->ch_channel); 1164 continue; 1165 } 1166 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1167 (wdc_cp->ch_channel << 6) + 0x4, 4, 1168 &wdr->sata_error) != 0) { 1169 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1170 "couldn't map channel %d sata_error regs\n", 1171 wdc_cp->ch_channel); 1172 continue; 1173 } 1174 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1175 (wdc_cp->ch_channel << 6) + 0x8, 4, 1176 &wdr->sata_control) != 0) { 1177 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1178 "couldn't map channel %d sata_control regs\n", 1179 wdc_cp->ch_channel); 1180 continue; 1181 } 1182 1183 if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel), 1184 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1185 NULL, &wdr->cmd_ios) != 0) { 1186 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1187 "couldn't map %s channel regs\n", cp->name); 1188 } 1189 wdr->ctl_iot = wdr->cmd_iot; 1190 for (i = 0; i < WDC_NREG; i++) { 1191 if (bus_space_subregion(wdr->cmd_iot, 1192 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1193 &wdr->cmd_iohs[i]) != 0) { 1194 aprint_error_dev( 1195 sc->sc_wdcdev.sc_atac.atac_dev, 1196 "couldn't subregion %s " 1197 "channel cmd regs\n", cp->name); 1198 return; 1199 } 1200 } 1201 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1202 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1203 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1204 "couldn't map channel %d ctl regs\n", channel); 1205 return; 1206 } 1207 wdc_init_shadow_regs(wdr); 1208 wdr->data32iot = wdr->cmd_iot; 1209 wdr->data32ioh = wdr->cmd_iohs[wd_data]; 1210 wdcattach(wdc_cp); 1211 } 1212 } 1213
Indexes created Sun Oct 19 02:09:48 GMT 2025