viaide.c revision 1.86.4.1
1 /* $NetBSD: viaide.c,v 1.86.4.1 2019/06/10 22:07:27 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.86.4.1 2019/06/10 22:07:27 christos Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/pci/pciide_apollo_reg.h> 39 40 static int via_pcib_match(const struct pci_attach_args *); 41 static void via_chip_map(struct pciide_softc *, 42 const struct pci_attach_args *); 43 static void via_mapchan(const struct pci_attach_args *, 44 struct pciide_channel *, 45 pcireg_t, int (*)(void *)); 46 static void via_mapregs_compat_native(const struct pci_attach_args *, 47 struct pciide_channel *); 48 static int via_sata_chip_map_common(struct pciide_softc *, 49 const struct pci_attach_args *); 50 static void via_sata_chip_map(struct pciide_softc *, 51 const struct pci_attach_args *, int); 52 static void via_sata_chip_map_6(struct pciide_softc *, 53 const struct pci_attach_args *); 54 static void via_sata_chip_map_7(struct pciide_softc *, 55 const struct pci_attach_args *); 56 static void via_sata_chip_map_new(struct pciide_softc *, 57 const struct pci_attach_args *); 58 static void via_setup_channel(struct ata_channel *); 59 60 static int viaide_match(device_t, cfdata_t, void *); 61 static void viaide_attach(device_t, device_t, void *); 62 static const struct pciide_product_desc * 63 viaide_lookup(pcireg_t); 64 static bool viaide_suspend(device_t, const pmf_qual_t *); 65 static bool viaide_resume(device_t, const pmf_qual_t *); 66 67 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 68 viaide_match, viaide_attach, pciide_detach, NULL); 69 70 static const struct pciide_product_desc pciide_amd_products[] = { 71 { PCI_PRODUCT_AMD_PBC756_IDE, 72 0, 73 "AMD AMD756 IDE Controller", 74 via_chip_map 75 }, 76 { PCI_PRODUCT_AMD_PBC766_IDE, 77 0, 78 "AMD AMD766 IDE Controller", 79 via_chip_map 80 }, 81 { PCI_PRODUCT_AMD_PBC768_IDE, 82 0, 83 "AMD AMD768 IDE Controller", 84 via_chip_map 85 }, 86 { PCI_PRODUCT_AMD_PBC8111_IDE, 87 0, 88 "AMD AMD8111 IDE Controller", 89 via_chip_map 90 }, 91 { PCI_PRODUCT_AMD_CS5536_IDE, 92 0, 93 "AMD CS5536 IDE Controller", 94 via_chip_map 95 }, 96 { 0, 97 0, 98 NULL, 99 NULL 100 } 101 }; 102 103 static const struct pciide_product_desc pciide_nvidia_products[] = { 104 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 105 0, 106 "NVIDIA nForce IDE Controller", 107 via_chip_map 108 }, 109 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 110 0, 111 "NVIDIA nForce2 IDE Controller", 112 via_chip_map 113 }, 114 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 115 0, 116 "NVIDIA nForce2 Ultra 400 IDE Controller", 117 via_chip_map 118 }, 119 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 120 0, 121 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 122 via_sata_chip_map_6 123 }, 124 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 125 0, 126 "NVIDIA nForce3 IDE Controller", 127 via_chip_map 128 }, 129 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 130 0, 131 "NVIDIA nForce3 250 IDE Controller", 132 via_chip_map 133 }, 134 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 135 0, 136 "NVIDIA nForce3 250 Serial ATA Controller", 137 via_sata_chip_map_6 138 }, 139 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 140 0, 141 "NVIDIA nForce3 250 Serial ATA Controller", 142 via_sata_chip_map_6 143 }, 144 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 145 0, 146 "NVIDIA nForce4 IDE Controller", 147 via_chip_map 148 }, 149 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 150 0, 151 "NVIDIA nForce4 Serial ATA Controller", 152 via_sata_chip_map_6 153 }, 154 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 155 0, 156 "NVIDIA nForce4 Serial ATA Controller", 157 via_sata_chip_map_6 158 }, 159 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 160 0, 161 "NVIDIA nForce430 IDE Controller", 162 via_chip_map 163 }, 164 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 165 0, 166 "NVIDIA nForce430 Serial ATA Controller", 167 via_sata_chip_map_6 168 }, 169 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 170 0, 171 "NVIDIA nForce430 Serial ATA Controller", 172 via_sata_chip_map_6 173 }, 174 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 175 0, 176 "NVIDIA MCP04 IDE Controller", 177 via_chip_map 178 }, 179 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 180 0, 181 "NVIDIA MCP04 Serial ATA Controller", 182 via_sata_chip_map_6 183 }, 184 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 185 0, 186 "NVIDIA MCP04 Serial ATA Controller", 187 via_sata_chip_map_6 188 }, 189 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 190 0, 191 "NVIDIA MCP55 IDE Controller", 192 via_chip_map 193 }, 194 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 195 0, 196 "NVIDIA MCP55 Serial ATA Controller", 197 via_sata_chip_map_6 198 }, 199 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 200 0, 201 "NVIDIA MCP55 Serial ATA Controller", 202 via_sata_chip_map_6 203 }, 204 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 205 0, 206 "NVIDIA MCP61 IDE Controller", 207 via_chip_map 208 }, 209 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 210 0, 211 "NVIDIA MCP65 IDE Controller", 212 via_chip_map 213 }, 214 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 215 0, 216 "NVIDIA MCP73 IDE Controller", 217 via_chip_map 218 }, 219 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 220 0, 221 "NVIDIA MCP77 IDE Controller", 222 via_chip_map 223 }, 224 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 225 0, 226 "NVIDIA MCP61 Serial ATA Controller", 227 via_sata_chip_map_6 228 }, 229 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 230 0, 231 "NVIDIA MCP61 Serial ATA Controller", 232 via_sata_chip_map_6 233 }, 234 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 235 0, 236 "NVIDIA MCP61 Serial ATA Controller", 237 via_sata_chip_map_6 238 }, 239 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 240 0, 241 "NVIDIA MCP65 Serial ATA Controller", 242 via_sata_chip_map_6 243 }, 244 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 245 0, 246 "NVIDIA MCP65 Serial ATA Controller", 247 via_sata_chip_map_6 248 }, 249 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 250 0, 251 "NVIDIA MCP65 Serial ATA Controller", 252 via_sata_chip_map_6 253 }, 254 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 255 0, 256 "NVIDIA MCP65 Serial ATA Controller", 257 via_sata_chip_map_6 258 }, 259 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 260 0, 261 "NVIDIA MCP67 IDE Controller", 262 via_chip_map, 263 }, 264 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 265 0, 266 "NVIDIA MCP67 Serial ATA Controller", 267 via_sata_chip_map_6, 268 }, 269 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 270 0, 271 "NVIDIA MCP67 Serial ATA Controller", 272 via_sata_chip_map_6, 273 }, 274 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 275 0, 276 "NVIDIA MCP67 Serial ATA Controller", 277 via_sata_chip_map_6, 278 }, 279 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 280 0, 281 "NVIDIA MCP67 Serial ATA Controller", 282 via_sata_chip_map_6, 283 }, 284 { 0, 285 0, 286 NULL, 287 NULL 288 } 289 }; 290 291 static const struct pciide_product_desc pciide_via_products[] = { 292 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 293 0, 294 NULL, 295 via_chip_map, 296 }, 297 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 298 0, 299 NULL, 300 via_chip_map, 301 }, 302 { PCI_PRODUCT_VIATECH_CX700_IDE, 303 0, 304 NULL, 305 via_sata_chip_map_new, 306 }, 307 { PCI_PRODUCT_VIATECH_CX700M2_IDE, 308 0, 309 NULL, 310 via_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_VX900_IDE, 313 0, 314 NULL, 315 via_chip_map, 316 }, 317 { PCI_PRODUCT_VIATECH_VT6410_RAID, 318 0, 319 NULL, 320 via_chip_map, 321 }, 322 { PCI_PRODUCT_VIATECH_VT6421_RAID, 323 0, 324 "VIA Technologies VT6421 Serial ATA RAID Controller", 325 via_sata_chip_map_new, 326 }, 327 { PCI_PRODUCT_VIATECH_VT8237_SATA, 328 0, 329 "VIA Technologies VT8237 SATA Controller", 330 via_sata_chip_map_7, 331 }, 332 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 333 0, 334 "VIA Technologies VT8237A SATA Controller", 335 via_sata_chip_map_7, 336 }, 337 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, 338 0, 339 "VIA Technologies VT8237A (5337) SATA Controller", 340 via_sata_chip_map_7, 341 }, 342 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 343 0, 344 "VIA Technologies VT8237R SATA Controller", 345 via_sata_chip_map_7, 346 }, 347 { PCI_PRODUCT_VIATECH_VT8237S_SATA, 348 0, 349 "VIA Technologies VT8237S SATA Controller", 350 via_sata_chip_map_7, 351 }, 352 { PCI_PRODUCT_VIATECH_VT8237S_SATA_RAID, 353 0, 354 "VIA Technologies VT8237S SATA Controller (RAID mode)", 355 via_sata_chip_map_7, 356 }, 357 { 0, 358 0, 359 NULL, 360 NULL 361 } 362 }; 363 364 static const struct pciide_product_desc * 365 viaide_lookup(pcireg_t id) 366 { 367 368 switch (PCI_VENDOR(id)) { 369 case PCI_VENDOR_VIATECH: 370 return (pciide_lookup_product(id, pciide_via_products)); 371 372 case PCI_VENDOR_AMD: 373 return (pciide_lookup_product(id, pciide_amd_products)); 374 375 case PCI_VENDOR_NVIDIA: 376 return (pciide_lookup_product(id, pciide_nvidia_products)); 377 } 378 return (NULL); 379 } 380 381 static int 382 viaide_match(device_t parent, cfdata_t match, void *aux) 383 { 384 const struct pci_attach_args *pa = aux; 385 386 if (viaide_lookup(pa->pa_id) != NULL) 387 return (2); 388 return (0); 389 } 390 391 static void 392 viaide_attach(device_t parent, device_t self, void *aux) 393 { 394 const struct pci_attach_args *pa = aux; 395 struct pciide_softc *sc = device_private(self); 396 const struct pciide_product_desc *pp; 397 398 sc->sc_wdcdev.sc_atac.atac_dev = self; 399 400 pp = viaide_lookup(pa->pa_id); 401 if (pp == NULL) 402 panic("viaide_attach"); 403 pciide_common_attach(sc, pa, pp); 404 405 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 406 aprint_error_dev(self, "couldn't establish power handler\n"); 407 } 408 409 static int 410 via_pcib_match(const struct pci_attach_args *pa) 411 { 412 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 413 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 414 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 415 return (1); 416 return 0; 417 } 418 419 static bool 420 viaide_suspend(device_t dv, const pmf_qual_t *qual) 421 { 422 struct pciide_softc *sc = device_private(dv); 423 424 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 425 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 426 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 427 /* This two are VIA-only, but should be ignored by other devices. */ 428 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 429 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 430 431 return true; 432 } 433 434 static bool 435 viaide_resume(device_t dv, const pmf_qual_t *qual) 436 { 437 struct pciide_softc *sc = device_private(dv); 438 439 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 440 sc->sc_pm_reg[0]); 441 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 442 sc->sc_pm_reg[1]); 443 /* This two are VIA-only, but should be ignored by other devices. */ 444 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 445 sc->sc_pm_reg[2]); 446 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 447 sc->sc_pm_reg[3]); 448 449 return true; 450 } 451 452 static void 453 via_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 454 { 455 struct pciide_channel *cp; 456 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 457 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 458 int channel; 459 u_int32_t ideconf; 460 pcireg_t pcib_id, pcib_class; 461 struct pci_attach_args pcib_pa; 462 463 if (pciide_chipen(sc, pa) == 0) 464 return; 465 466 switch (vendor) { 467 case PCI_VENDOR_VIATECH: 468 switch (PCI_PRODUCT(pa->pa_id)) { 469 case PCI_PRODUCT_VIATECH_VT6410_RAID: 470 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 471 "VIA Technologies VT6410 IDE controller\n"); 472 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 473 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 474 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 475 break; 476 case PCI_PRODUCT_VIATECH_VX900_IDE: 477 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 478 "VIA Technologies VX900 ATA133 controller\n"); 479 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 480 break; 481 default: 482 /* 483 * get a PCI tag for the ISA bridge. 484 */ 485 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 486 goto unknown; 487 pcib_id = pcib_pa.pa_id; 488 pcib_class = pcib_pa.pa_class; 489 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 490 "VIA Technologies "); 491 switch (PCI_PRODUCT(pcib_id)) { 492 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 493 aprint_normal("VT82C586 (Apollo VP) "); 494 if(PCI_REVISION(pcib_class) >= 0x02) { 495 aprint_normal("ATA33 controller\n"); 496 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 497 } else { 498 aprint_normal("controller\n"); 499 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 500 } 501 break; 502 case PCI_PRODUCT_VIATECH_VT82C596A: 503 aprint_normal("VT82C596A (Apollo Pro) "); 504 if (PCI_REVISION(pcib_class) >= 0x12) { 505 aprint_normal("ATA66 controller\n"); 506 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 507 } else { 508 aprint_normal("ATA33 controller\n"); 509 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 510 } 511 break; 512 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 513 aprint_normal("VT82C686A (Apollo KX133) "); 514 if (PCI_REVISION(pcib_class) >= 0x40) { 515 aprint_normal("ATA100 controller\n"); 516 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 517 } else { 518 aprint_normal("ATA66 controller\n"); 519 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 520 } 521 break; 522 case PCI_PRODUCT_VIATECH_VT8231: 523 aprint_normal("VT8231 ATA100 controller\n"); 524 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 525 break; 526 case PCI_PRODUCT_VIATECH_VT8233: 527 aprint_normal("VT8233 ATA100 controller\n"); 528 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 529 break; 530 case PCI_PRODUCT_VIATECH_VT8233A: 531 aprint_normal("VT8233A ATA133 controller\n"); 532 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 533 break; 534 case PCI_PRODUCT_VIATECH_VT8235: 535 aprint_normal("VT8235 ATA133 controller\n"); 536 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 537 break; 538 case PCI_PRODUCT_VIATECH_VT8237: 539 aprint_normal("VT8237 ATA133 controller\n"); 540 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 541 break; 542 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 543 aprint_normal("VT8237A ATA133 controller\n"); 544 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 545 break; 546 case PCI_PRODUCT_VIATECH_CX700: 547 aprint_normal("CX700 ATA133 controller\n"); 548 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 549 break; 550 case PCI_PRODUCT_VIATECH_VT8251: 551 aprint_normal("VT8251 ATA133 controller\n"); 552 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 553 break; 554 case PCI_PRODUCT_VIATECH_VX800: 555 aprint_normal("VT800 ATA133 controller\n"); 556 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 557 break; 558 case PCI_PRODUCT_VIATECH_VX855: 559 aprint_normal("VT855 ATA133 controller\n"); 560 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 561 break; 562 default: 563 unknown: 564 aprint_normal("unknown VIA ATA controller\n"); 565 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 566 } 567 break; 568 } 569 sc->sc_apo_regbase = APO_VIA_REGBASE; 570 break; 571 case PCI_VENDOR_AMD: 572 switch (sc->sc_pp->ide_product) { 573 case PCI_PRODUCT_AMD_PBC8111_IDE: 574 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 575 break; 576 case PCI_PRODUCT_AMD_CS5536_IDE: 577 case PCI_PRODUCT_AMD_PBC766_IDE: 578 case PCI_PRODUCT_AMD_PBC768_IDE: 579 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 580 break; 581 default: 582 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 583 } 584 sc->sc_apo_regbase = APO_AMD_REGBASE; 585 break; 586 case PCI_VENDOR_NVIDIA: 587 switch (sc->sc_pp->ide_product) { 588 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 589 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 590 break; 591 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 592 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 593 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 594 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 595 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 596 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 597 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 598 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 599 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 600 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 601 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 602 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 603 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 604 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 605 break; 606 } 607 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 608 break; 609 default: 610 panic("via_chip_map: unknown vendor"); 611 } 612 613 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 614 "bus-master DMA support present"); 615 pciide_mapreg_dma(sc, pa); 616 aprint_verbose("\n"); 617 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 618 if (sc->sc_dma_ok) { 619 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 620 sc->sc_wdcdev.irqack = pciide_irqack; 621 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 622 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 623 } 624 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 625 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 626 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 627 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 628 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 629 sc->sc_wdcdev.wdc_maxdrives = 2; 630 631 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 632 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 633 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 634 635 wdc_allocate_regs(&sc->sc_wdcdev); 636 637 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 638 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 639 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 640 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 641 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 642 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 643 DEBUG_PROBE); 644 645 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 646 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 647 channel++) { 648 cp = &sc->pciide_channels[channel]; 649 if (pciide_chansetup(sc, channel, interface) == 0) 650 continue; 651 652 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 653 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 654 "%s channel ignored (disabled)\n", cp->name); 655 cp->ata_channel.ch_flags |= ATACH_DISABLED; 656 continue; 657 } 658 via_mapchan(pa, cp, interface, pciide_pci_intr); 659 } 660 } 661 662 static void 663 via_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp, 664 pcireg_t interface, int (*pci_intr)(void *)) 665 { 666 struct ata_channel *wdc_cp; 667 struct pciide_softc *sc; 668 prop_bool_t compat_nat_enable; 669 670 wdc_cp = &cp->ata_channel; 671 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 672 compat_nat_enable = prop_dictionary_get( 673 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 674 "use-compat-native-irq"); 675 676 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 677 /* native mode with irq 14/15 requested? */ 678 if (compat_nat_enable != NULL && 679 prop_bool_true(compat_nat_enable)) 680 via_mapregs_compat_native(pa, cp); 681 else 682 pciide_mapregs_native(pa, cp, pci_intr); 683 } else { 684 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 685 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 686 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 687 } 688 wdcattach(wdc_cp); 689 } 690 691 /* 692 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 693 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 694 * programmed to use a single native PCI irq alone. So we install an interrupt 695 * handler for each channel, as in compatibility mode. 696 */ 697 static void 698 via_mapregs_compat_native(const struct pci_attach_args *pa, 699 struct pciide_channel *cp) 700 { 701 struct ata_channel *wdc_cp; 702 struct pciide_softc *sc; 703 704 wdc_cp = &cp->ata_channel; 705 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 706 707 /* XXX prevent pciide_mapregs_native from installing a handler */ 708 if (sc->sc_pci_ih == NULL) 709 sc->sc_pci_ih = (void *)~0; 710 pciide_mapregs_native(pa, cp, NULL); 711 712 /* interrupts are fixed to 14/15, as in compatibility mode */ 713 cp->compat = 1; 714 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 715 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 716 cp->ih = pciide_machdep_compat_intr_establish( 717 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 718 pciide_compat_intr, cp); 719 if (cp->ih == NULL) { 720 #endif 721 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 722 "no compatibility interrupt for " 723 "use by %s channel\n", cp->name); 724 wdc_cp->ch_flags |= ATACH_DISABLED; 725 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 726 } 727 sc->sc_pci_ih = cp->ih; /* XXX */ 728 #endif 729 } 730 } 731 732 static void 733 via_setup_channel(struct ata_channel *chp) 734 { 735 u_int32_t udmatim_reg, datatim_reg; 736 u_int8_t idedma_ctl; 737 int mode, drive, s; 738 struct ata_drive_datas *drvp; 739 struct atac_softc *atac = chp->ch_atac; 740 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 741 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 742 #ifndef PCIIDE_AMD756_ENABLEDMA 743 int rev = PCI_REVISION( 744 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 745 #endif 746 747 idedma_ctl = 0; 748 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 749 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 750 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 751 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 752 753 /* setup DMA if needed */ 754 pciide_channel_dma_setup(cp); 755 756 for (drive = 0; drive < 2; drive++) { 757 drvp = &chp->ch_drive[drive]; 758 /* If no drive, skip */ 759 if (drvp->drive_type == ATA_DRIVET_NONE) 760 continue; 761 /* add timing values, setup DMA if needed */ 762 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 763 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0)) { 764 mode = drvp->PIO_mode; 765 goto pio; 766 } 767 if ((atac->atac_cap & ATAC_CAP_UDMA) && 768 (drvp->drive_flags & ATA_DRIVE_UDMA)) { 769 /* use Ultra/DMA */ 770 s = splbio(); 771 drvp->drive_flags &= ~ATA_DRIVE_DMA; 772 splx(s); 773 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 774 APO_UDMA_EN_MTH(chp->ch_channel, drive); 775 switch (PCI_VENDOR(sc->sc_pci_id)) { 776 case PCI_VENDOR_VIATECH: 777 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 778 /* 8233a */ 779 udmatim_reg |= APO_UDMA_TIME( 780 chp->ch_channel, 781 drive, 782 via_udma133_tim[drvp->UDMA_mode]); 783 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 784 /* 686b */ 785 udmatim_reg |= APO_UDMA_TIME( 786 chp->ch_channel, 787 drive, 788 via_udma100_tim[drvp->UDMA_mode]); 789 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 790 /* 596b or 686a */ 791 udmatim_reg |= APO_UDMA_CLK66( 792 chp->ch_channel); 793 udmatim_reg |= APO_UDMA_TIME( 794 chp->ch_channel, 795 drive, 796 via_udma66_tim[drvp->UDMA_mode]); 797 } else { 798 /* 596a or 586b */ 799 udmatim_reg |= APO_UDMA_TIME( 800 chp->ch_channel, 801 drive, 802 via_udma33_tim[drvp->UDMA_mode]); 803 } 804 break; 805 case PCI_VENDOR_AMD: 806 case PCI_VENDOR_NVIDIA: 807 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 808 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 809 break; 810 } 811 /* can use PIO timings, MW DMA unused */ 812 mode = drvp->PIO_mode; 813 } else { 814 /* use Multiword DMA, but only if revision is OK */ 815 s = splbio(); 816 drvp->drive_flags &= ~ATA_DRIVE_UDMA; 817 splx(s); 818 #ifndef PCIIDE_AMD756_ENABLEDMA 819 /* 820 * The workaround doesn't seem to be necessary 821 * with all drives, so it can be disabled by 822 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 823 * triggered. 824 */ 825 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 826 sc->sc_pp->ide_product == 827 PCI_PRODUCT_AMD_PBC756_IDE && 828 AMD756_CHIPREV_DISABLEDMA(rev)) { 829 aprint_normal( 830 "%s:%d:%d: multi-word DMA disabled due " 831 "to chip revision\n", 832 device_xname( 833 sc->sc_wdcdev.sc_atac.atac_dev), 834 chp->ch_channel, drive); 835 mode = drvp->PIO_mode; 836 s = splbio(); 837 drvp->drive_flags &= ~ATA_DRIVE_DMA; 838 splx(s); 839 goto pio; 840 } 841 #endif 842 /* mode = min(pio, dma+2) */ 843 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 844 mode = drvp->PIO_mode; 845 else 846 mode = drvp->DMA_mode + 2; 847 } 848 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 849 850 pio: /* setup PIO mode */ 851 if (mode <= 2) { 852 drvp->DMA_mode = 0; 853 drvp->PIO_mode = 0; 854 mode = 0; 855 } else { 856 drvp->PIO_mode = mode; 857 drvp->DMA_mode = mode - 2; 858 } 859 datatim_reg |= 860 APO_DATATIM_PULSE(chp->ch_channel, drive, 861 apollo_pio_set[mode]) | 862 APO_DATATIM_RECOV(chp->ch_channel, drive, 863 apollo_pio_rec[mode]); 864 } 865 if (idedma_ctl != 0) { 866 /* Add software bits in status register */ 867 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 868 idedma_ctl); 869 } 870 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 871 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 872 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 873 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 874 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 875 } 876 877 static int 878 via_sata_chip_map_common(struct pciide_softc *sc, 879 const struct pci_attach_args *cpa) 880 { 881 pcireg_t csr; 882 int maptype, ret; 883 struct pci_attach_args pac, *pa = &pac; 884 885 pac = *cpa; 886 887 if (pciide_chipen(sc, pa) == 0) 888 return 0; 889 890 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 891 "bus-master DMA support present"); 892 pciide_mapreg_dma(sc, pa); 893 aprint_verbose("\n"); 894 895 if (sc->sc_dma_ok) { 896 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 897 sc->sc_wdcdev.irqack = pciide_irqack; 898 } 899 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 900 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 901 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 902 903 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 904 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 905 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 906 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 907 sc->sc_wdcdev.wdc_maxdrives = 2; 908 909 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 910 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 911 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 912 913 wdc_allocate_regs(&sc->sc_wdcdev); 914 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 915 PCI_MAPREG_START + 0x14); 916 switch(maptype) { 917 case PCI_MAPREG_TYPE_IO: 918 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 919 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 920 NULL, &sc->sc_ba5_ss); 921 break; 922 case PCI_MAPREG_MEM_TYPE_32BIT: 923 /* 924 * Enable memory-space access if it isn't already there. 925 */ 926 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, 927 PCI_COMMAND_STATUS_REG); 928 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 && 929 (pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) { 930 931 pci_conf_write(pa->pa_pc, pa->pa_tag, 932 PCI_COMMAND_STATUS_REG, 933 csr | PCI_COMMAND_MEM_ENABLE); 934 } 935 936 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 937 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 938 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 939 NULL, &sc->sc_ba5_ss); 940 break; 941 default: 942 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 943 "couldn't map sata regs, unsupported maptype (0x%x)\n", 944 maptype); 945 return 0; 946 } 947 if (ret != 0) { 948 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 949 "couldn't map sata regs\n"); 950 return 0; 951 } 952 return 1; 953 } 954 955 static void 956 via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa, 957 int satareg_shift) 958 { 959 struct pciide_channel *cp; 960 struct ata_channel *wdc_cp; 961 struct wdc_regs *wdr; 962 pcireg_t interface; 963 int channel; 964 965 interface = PCI_INTERFACE(pa->pa_class); 966 967 if (via_sata_chip_map_common(sc, pa) == 0) 968 return; 969 970 if (interface == 0) { 971 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 972 DEBUG_PROBE); 973 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 974 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 975 } 976 977 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 978 sc->sc_wdcdev.wdc_maxdrives = 1; 979 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 980 channel++) { 981 cp = &sc->pciide_channels[channel]; 982 if (pciide_chansetup(sc, channel, interface) == 0) 983 continue; 984 wdc_cp = &cp->ata_channel; 985 wdr = CHAN_TO_WDC_REGS(wdc_cp); 986 wdr->sata_iot = sc->sc_ba5_st; 987 wdr->sata_baseioh = sc->sc_ba5_sh; 988 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 989 (wdc_cp->ch_channel << satareg_shift) + 0x0, 4, 990 &wdr->sata_status) != 0) { 991 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 992 "couldn't map channel %d sata_status regs\n", 993 wdc_cp->ch_channel); 994 continue; 995 } 996 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 997 (wdc_cp->ch_channel << satareg_shift) + 0x4, 4, 998 &wdr->sata_error) != 0) { 999 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1000 "couldn't map channel %d sata_error regs\n", 1001 wdc_cp->ch_channel); 1002 continue; 1003 } 1004 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1005 (wdc_cp->ch_channel << satareg_shift) + 0x8, 4, 1006 &wdr->sata_control) != 0) { 1007 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1008 "couldn't map channel %d sata_control regs\n", 1009 wdc_cp->ch_channel); 1010 continue; 1011 } 1012 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 1013 } 1014 } 1015 1016 static void 1017 via_sata_chip_map_6(struct pciide_softc *sc, const struct pci_attach_args *pa) 1018 { 1019 via_sata_chip_map(sc, pa, 6); 1020 } 1021 1022 static void 1023 via_sata_chip_map_7(struct pciide_softc *sc, const struct pci_attach_args *pa) 1024 { 1025 via_sata_chip_map(sc, pa, 7); 1026 } 1027 1028 static void 1029 via_vt6421_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 1030 { 1031 struct pciide_channel *pc; 1032 int chan, reg; 1033 bus_size_t size; 1034 1035 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 1036 PCI_MAPREG_TYPE_IO, 0, &sc->sc_dma_iot, &sc->sc_dma_ioh, 1037 NULL, &sc->sc_dma_ios) == 0); 1038 sc->sc_dmat = pa->pa_dmat; 1039 if (sc->sc_dma_ok == 0) { 1040 aprint_verbose(", but unused (couldn't map registers)"); 1041 } else { 1042 sc->sc_wdcdev.dma_arg = sc; 1043 sc->sc_wdcdev.dma_init = pciide_dma_init; 1044 sc->sc_wdcdev.dma_start = pciide_dma_start; 1045 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 1046 } 1047 1048 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 1049 PCIIDE_OPTIONS_NODMA) { 1050 aprint_verbose( 1051 ", but unused (forced off by config file)"); 1052 sc->sc_dma_ok = 0; 1053 } 1054 1055 if (sc->sc_dma_ok == 0) 1056 return; 1057 1058 for (chan = 0; chan < 4; chan++) { 1059 pc = &sc->pciide_channels[chan]; 1060 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 1061 size = 4; 1062 if (size > (IDEDMA_SCH_OFFSET - reg)) 1063 size = IDEDMA_SCH_OFFSET - reg; 1064 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 1065 IDEDMA_SCH_OFFSET * chan + reg, size, 1066 &pc->dma_iohs[reg]) != 0) { 1067 sc->sc_dma_ok = 0; 1068 aprint_verbose(", but can't subregion offset " 1069 "%d size %lu", 1070 reg, (u_long)size); 1071 return; 1072 } 1073 } 1074 } 1075 } 1076 1077 static int 1078 via_vt6421_chansetup(struct pciide_softc *sc, int channel) 1079 { 1080 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1081 1082 sc->wdc_chanarray[channel] = &cp->ata_channel; 1083 1084 cp->ata_channel.ch_channel = channel; 1085 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 1086 1087 return 1; 1088 } 1089 1090 static void 1091 via_sata_chip_map_new(struct pciide_softc *sc, 1092 const struct pci_attach_args *pa) 1093 { 1094 struct pciide_channel *cp; 1095 struct ata_channel *wdc_cp; 1096 struct wdc_regs *wdr; 1097 int channel; 1098 pci_intr_handle_t intrhandle; 1099 const char *intrstr; 1100 int i; 1101 char intrbuf[PCI_INTRSTR_LEN]; 1102 1103 if (pciide_chipen(sc, pa) == 0) 1104 return; 1105 1106 sc->sc_apo_regbase = APO_VIA_VT6421_REGBASE; 1107 1108 if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0, 1109 &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 1110 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1111 "couldn't map SATA regs\n"); 1112 } 1113 1114 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1115 "bus-master DMA support present"); 1116 via_vt6421_mapreg_dma(sc, pa); 1117 aprint_verbose("\n"); 1118 1119 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 1120 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 1121 if (sc->sc_dma_ok) { 1122 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 1123 sc->sc_wdcdev.irqack = pciide_irqack; 1124 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 1125 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 1126 } 1127 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 1128 1129 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 1130 sc->sc_wdcdev.sc_atac.atac_nchannels = 3; 1131 sc->sc_wdcdev.wdc_maxdrives = 2; 1132 1133 wdc_allocate_regs(&sc->sc_wdcdev); 1134 1135 if (pci_intr_map(pa, &intrhandle) != 0) { 1136 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1137 "couldn't map native-PCI interrupt\n"); 1138 return; 1139 } 1140 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 1141 sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc, 1142 intrhandle, IPL_BIO, pciide_pci_intr, sc, 1143 device_xname(sc->sc_wdcdev.sc_atac.atac_dev)); 1144 if (sc->sc_pci_ih == NULL) { 1145 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1146 "couldn't establish native-PCI interrupt"); 1147 if (intrstr != NULL) 1148 aprint_error(" at %s", intrstr); 1149 aprint_error("\n"); 1150 return; 1151 } 1152 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1153 "using %s for native-PCI interrupt\n", 1154 intrstr ? intrstr : "unknown interrupt"); 1155 1156 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1157 channel++) { 1158 cp = &sc->pciide_channels[channel]; 1159 if (via_vt6421_chansetup(sc, channel) == 0) 1160 continue; 1161 wdc_cp = &cp->ata_channel; 1162 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1163 1164 wdr->sata_iot = sc->sc_ba5_st; 1165 wdr->sata_baseioh = sc->sc_ba5_sh; 1166 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1167 (wdc_cp->ch_channel << 6) + 0x0, 4, 1168 &wdr->sata_status) != 0) { 1169 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1170 "couldn't map channel %d sata_status regs\n", 1171 wdc_cp->ch_channel); 1172 continue; 1173 } 1174 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1175 (wdc_cp->ch_channel << 6) + 0x4, 4, 1176 &wdr->sata_error) != 0) { 1177 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1178 "couldn't map channel %d sata_error regs\n", 1179 wdc_cp->ch_channel); 1180 continue; 1181 } 1182 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1183 (wdc_cp->ch_channel << 6) + 0x8, 4, 1184 &wdr->sata_control) != 0) { 1185 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1186 "couldn't map channel %d sata_control regs\n", 1187 wdc_cp->ch_channel); 1188 continue; 1189 } 1190 1191 if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel), 1192 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1193 NULL, &wdr->cmd_ios) != 0) { 1194 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1195 "couldn't map %s channel regs\n", cp->name); 1196 } 1197 wdr->ctl_iot = wdr->cmd_iot; 1198 for (i = 0; i < WDC_NREG; i++) { 1199 if (bus_space_subregion(wdr->cmd_iot, 1200 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1201 &wdr->cmd_iohs[i]) != 0) { 1202 aprint_error_dev( 1203 sc->sc_wdcdev.sc_atac.atac_dev, 1204 "couldn't subregion %s " 1205 "channel cmd regs\n", cp->name); 1206 return; 1207 } 1208 } 1209 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1210 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1211 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1212 "couldn't map channel %d ctl regs\n", channel); 1213 return; 1214 } 1215 wdc_init_shadow_regs(wdr); 1216 wdr->data32iot = wdr->cmd_iot; 1217 wdr->data32ioh = wdr->cmd_iohs[wd_data]; 1218 wdcattach(wdc_cp); 1219 } 1220 } 1221
Indexes created Sun Oct 19 02:09:48 GMT 2025