viaide.c revision 1.88 1 /* $NetBSD: viaide.c,v 1.88 2019/06/01 08:20:14 jdolecek Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.88 2019/06/01 08:20:14 jdolecek Exp $");
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33
34 #include <dev/pci/pcivar.h>
35 #include <dev/pci/pcidevs.h>
36 #include <dev/pci/pciidereg.h>
37 #include <dev/pci/pciidevar.h>
38 #include <dev/pci/pciide_apollo_reg.h>
39
40 static int via_pcib_match(const struct pci_attach_args *);
41 static void via_chip_map(struct pciide_softc *,
42 const struct pci_attach_args *);
43 static void via_mapchan(const struct pci_attach_args *,
44 struct pciide_channel *,
45 pcireg_t, int (*)(void *));
46 static void via_mapregs_compat_native(const struct pci_attach_args *,
47 struct pciide_channel *);
48 static int via_sata_chip_map_common(struct pciide_softc *,
49 const struct pci_attach_args *);
50 static void via_sata_chip_map(struct pciide_softc *,
51 const struct pci_attach_args *, int);
52 static void via_sata_chip_map_6(struct pciide_softc *,
53 const struct pci_attach_args *);
54 static void via_sata_chip_map_7(struct pciide_softc *,
55 const struct pci_attach_args *);
56 static void via_sata_chip_map_new(struct pciide_softc *,
57 const struct pci_attach_args *);
58 static void via_setup_channel(struct ata_channel *);
59
60 static int viaide_match(device_t, cfdata_t, void *);
61 static void viaide_attach(device_t, device_t, void *);
62 static const struct pciide_product_desc *
63 viaide_lookup(pcireg_t);
64 static bool viaide_suspend(device_t, const pmf_qual_t *);
65 static bool viaide_resume(device_t, const pmf_qual_t *);
66
67 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc),
68 viaide_match, viaide_attach, pciide_detach, NULL);
69
70 static const struct pciide_product_desc pciide_amd_products[] = {
71 { PCI_PRODUCT_AMD_PBC756_IDE,
72 0,
73 "AMD AMD756 IDE Controller",
74 via_chip_map
75 },
76 { PCI_PRODUCT_AMD_PBC766_IDE,
77 0,
78 "AMD AMD766 IDE Controller",
79 via_chip_map
80 },
81 { PCI_PRODUCT_AMD_PBC768_IDE,
82 0,
83 "AMD AMD768 IDE Controller",
84 via_chip_map
85 },
86 { PCI_PRODUCT_AMD_PBC8111_IDE,
87 0,
88 "AMD AMD8111 IDE Controller",
89 via_chip_map
90 },
91 { PCI_PRODUCT_AMD_CS5536_IDE,
92 0,
93 "AMD CS5536 IDE Controller",
94 via_chip_map
95 },
96 { 0,
97 0,
98 NULL,
99 NULL
100 }
101 };
102
103 static const struct pciide_product_desc pciide_nvidia_products[] = {
104 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100,
105 0,
106 "NVIDIA nForce IDE Controller",
107 via_chip_map
108 },
109 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133,
110 0,
111 "NVIDIA nForce2 IDE Controller",
112 via_chip_map
113 },
114 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133,
115 0,
116 "NVIDIA nForce2 Ultra 400 IDE Controller",
117 via_chip_map
118 },
119 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA,
120 0,
121 "NVIDIA nForce2 Ultra 400 Serial ATA Controller",
122 via_sata_chip_map_6
123 },
124 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133,
125 0,
126 "NVIDIA nForce3 IDE Controller",
127 via_chip_map
128 },
129 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133,
130 0,
131 "NVIDIA nForce3 250 IDE Controller",
132 via_chip_map
133 },
134 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA,
135 0,
136 "NVIDIA nForce3 250 Serial ATA Controller",
137 via_sata_chip_map_6
138 },
139 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2,
140 0,
141 "NVIDIA nForce3 250 Serial ATA Controller",
142 via_sata_chip_map_6
143 },
144 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133,
145 0,
146 "NVIDIA nForce4 IDE Controller",
147 via_chip_map
148 },
149 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1,
150 0,
151 "NVIDIA nForce4 Serial ATA Controller",
152 via_sata_chip_map_6
153 },
154 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2,
155 0,
156 "NVIDIA nForce4 Serial ATA Controller",
157 via_sata_chip_map_6
158 },
159 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133,
160 0,
161 "NVIDIA nForce430 IDE Controller",
162 via_chip_map
163 },
164 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1,
165 0,
166 "NVIDIA nForce430 Serial ATA Controller",
167 via_sata_chip_map_6
168 },
169 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2,
170 0,
171 "NVIDIA nForce430 Serial ATA Controller",
172 via_sata_chip_map_6
173 },
174 { PCI_PRODUCT_NVIDIA_MCP04_IDE,
175 0,
176 "NVIDIA MCP04 IDE Controller",
177 via_chip_map
178 },
179 { PCI_PRODUCT_NVIDIA_MCP04_SATA,
180 0,
181 "NVIDIA MCP04 Serial ATA Controller",
182 via_sata_chip_map_6
183 },
184 { PCI_PRODUCT_NVIDIA_MCP04_SATA2,
185 0,
186 "NVIDIA MCP04 Serial ATA Controller",
187 via_sata_chip_map_6
188 },
189 { PCI_PRODUCT_NVIDIA_MCP55_IDE,
190 0,
191 "NVIDIA MCP55 IDE Controller",
192 via_chip_map
193 },
194 { PCI_PRODUCT_NVIDIA_MCP55_SATA,
195 0,
196 "NVIDIA MCP55 Serial ATA Controller",
197 via_sata_chip_map_6
198 },
199 { PCI_PRODUCT_NVIDIA_MCP55_SATA2,
200 0,
201 "NVIDIA MCP55 Serial ATA Controller",
202 via_sata_chip_map_6
203 },
204 { PCI_PRODUCT_NVIDIA_MCP61_IDE,
205 0,
206 "NVIDIA MCP61 IDE Controller",
207 via_chip_map
208 },
209 { PCI_PRODUCT_NVIDIA_MCP65_IDE,
210 0,
211 "NVIDIA MCP65 IDE Controller",
212 via_chip_map
213 },
214 { PCI_PRODUCT_NVIDIA_MCP73_IDE,
215 0,
216 "NVIDIA MCP73 IDE Controller",
217 via_chip_map
218 },
219 { PCI_PRODUCT_NVIDIA_MCP77_IDE,
220 0,
221 "NVIDIA MCP77 IDE Controller",
222 via_chip_map
223 },
224 { PCI_PRODUCT_NVIDIA_MCP61_SATA,
225 0,
226 "NVIDIA MCP61 Serial ATA Controller",
227 via_sata_chip_map_6
228 },
229 { PCI_PRODUCT_NVIDIA_MCP61_SATA2,
230 0,
231 "NVIDIA MCP61 Serial ATA Controller",
232 via_sata_chip_map_6
233 },
234 { PCI_PRODUCT_NVIDIA_MCP61_SATA3,
235 0,
236 "NVIDIA MCP61 Serial ATA Controller",
237 via_sata_chip_map_6
238 },
239 { PCI_PRODUCT_NVIDIA_MCP65_SATA,
240 0,
241 "NVIDIA MCP65 Serial ATA Controller",
242 via_sata_chip_map_6
243 },
244 { PCI_PRODUCT_NVIDIA_MCP65_SATA2,
245 0,
246 "NVIDIA MCP65 Serial ATA Controller",
247 via_sata_chip_map_6
248 },
249 { PCI_PRODUCT_NVIDIA_MCP65_SATA3,
250 0,
251 "NVIDIA MCP65 Serial ATA Controller",
252 via_sata_chip_map_6
253 },
254 { PCI_PRODUCT_NVIDIA_MCP65_SATA4,
255 0,
256 "NVIDIA MCP65 Serial ATA Controller",
257 via_sata_chip_map_6
258 },
259 { PCI_PRODUCT_NVIDIA_MCP67_IDE,
260 0,
261 "NVIDIA MCP67 IDE Controller",
262 via_chip_map,
263 },
264 { PCI_PRODUCT_NVIDIA_MCP67_SATA,
265 0,
266 "NVIDIA MCP67 Serial ATA Controller",
267 via_sata_chip_map_6,
268 },
269 { PCI_PRODUCT_NVIDIA_MCP67_SATA2,
270 0,
271 "NVIDIA MCP67 Serial ATA Controller",
272 via_sata_chip_map_6,
273 },
274 { PCI_PRODUCT_NVIDIA_MCP67_SATA3,
275 0,
276 "NVIDIA MCP67 Serial ATA Controller",
277 via_sata_chip_map_6,
278 },
279 { PCI_PRODUCT_NVIDIA_MCP67_SATA4,
280 0,
281 "NVIDIA MCP67 Serial ATA Controller",
282 via_sata_chip_map_6,
283 },
284 { 0,
285 0,
286 NULL,
287 NULL
288 }
289 };
290
291 static const struct pciide_product_desc pciide_via_products[] = {
292 { PCI_PRODUCT_VIATECH_VT82C586_IDE,
293 0,
294 NULL,
295 via_chip_map,
296 },
297 { PCI_PRODUCT_VIATECH_VT82C586A_IDE,
298 0,
299 NULL,
300 via_chip_map,
301 },
302 { PCI_PRODUCT_VIATECH_CX700_IDE,
303 0,
304 NULL,
305 via_chip_map,
306 },
307 { PCI_PRODUCT_VIATECH_CX700M2_IDE,
308 0,
309 NULL,
310 via_chip_map,
311 },
312 { PCI_PRODUCT_VIATECH_VX800,
313 0,
314 "VIA Technologies VX800 SATA Controller",
315 via_sata_chip_map_new,
316 },
317 { PCI_PRODUCT_VIATECH_VX855,
318 0,
319 NULL,
320 via_sata_chip_map_new,
321 },
322 { PCI_PRODUCT_VIATECH_VX900_IDE,
323 0,
324 NULL,
325 via_chip_map,
326 },
327 { PCI_PRODUCT_VIATECH_VT6410_RAID,
328 0,
329 NULL,
330 via_chip_map,
331 },
332 { PCI_PRODUCT_VIATECH_VT6421_RAID,
333 0,
334 "VIA Technologies VT6421 Serial ATA RAID Controller",
335 via_sata_chip_map_new,
336 },
337 { PCI_PRODUCT_VIATECH_VT8237_SATA,
338 0,
339 "VIA Technologies VT8237 SATA Controller",
340 via_sata_chip_map_7,
341 },
342 { PCI_PRODUCT_VIATECH_VT8237A_SATA,
343 0,
344 "VIA Technologies VT8237A SATA Controller",
345 via_sata_chip_map_7,
346 },
347 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2,
348 0,
349 "VIA Technologies VT8237A (5337) SATA Controller",
350 via_sata_chip_map_7,
351 },
352 { PCI_PRODUCT_VIATECH_VT8237R_SATA,
353 0,
354 "VIA Technologies VT8237R SATA Controller",
355 via_sata_chip_map_7,
356 },
357 { PCI_PRODUCT_VIATECH_VT8237S_SATA,
358 0,
359 "VIA Technologies VT8237S SATA Controller",
360 via_sata_chip_map_7,
361 },
362 { PCI_PRODUCT_VIATECH_VT8237S_SATA_RAID,
363 0,
364 "VIA Technologies VT8237S SATA Controller (RAID mode)",
365 via_sata_chip_map_7,
366 },
367 { 0,
368 0,
369 NULL,
370 NULL
371 }
372 };
373
374 static const struct pciide_product_desc *
375 viaide_lookup(pcireg_t id)
376 {
377
378 switch (PCI_VENDOR(id)) {
379 case PCI_VENDOR_VIATECH:
380 return (pciide_lookup_product(id, pciide_via_products));
381
382 case PCI_VENDOR_AMD:
383 return (pciide_lookup_product(id, pciide_amd_products));
384
385 case PCI_VENDOR_NVIDIA:
386 return (pciide_lookup_product(id, pciide_nvidia_products));
387 }
388 return (NULL);
389 }
390
391 static int
392 viaide_match(device_t parent, cfdata_t match, void *aux)
393 {
394 const struct pci_attach_args *pa = aux;
395
396 if (viaide_lookup(pa->pa_id) != NULL)
397 return (2);
398 return (0);
399 }
400
401 static void
402 viaide_attach(device_t parent, device_t self, void *aux)
403 {
404 const struct pci_attach_args *pa = aux;
405 struct pciide_softc *sc = device_private(self);
406 const struct pciide_product_desc *pp;
407
408 sc->sc_wdcdev.sc_atac.atac_dev = self;
409
410 pp = viaide_lookup(pa->pa_id);
411 if (pp == NULL)
412 panic("viaide_attach");
413 pciide_common_attach(sc, pa, pp);
414
415 if (!pmf_device_register(self, viaide_suspend, viaide_resume))
416 aprint_error_dev(self, "couldn't establish power handler\n");
417 }
418
419 static int
420 via_pcib_match(const struct pci_attach_args *pa)
421 {
422 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
423 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
424 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH)
425 return (1);
426 return 0;
427 }
428
429 static bool
430 viaide_suspend(device_t dv, const pmf_qual_t *qual)
431 {
432 struct pciide_softc *sc = device_private(dv);
433
434 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
435 /* APO_DATATIM(sc) includes APO_UDMA(sc) */
436 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
437 /* This two are VIA-only, but should be ignored by other devices. */
438 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc));
439 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc));
440
441 return true;
442 }
443
444 static bool
445 viaide_resume(device_t dv, const pmf_qual_t *qual)
446 {
447 struct pciide_softc *sc = device_private(dv);
448
449 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc),
450 sc->sc_pm_reg[0]);
451 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc),
452 sc->sc_pm_reg[1]);
453 /* This two are VIA-only, but should be ignored by other devices. */
454 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc),
455 sc->sc_pm_reg[2]);
456 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc),
457 sc->sc_pm_reg[3]);
458
459 return true;
460 }
461
462 static void
463 via_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
464 {
465 struct pciide_channel *cp;
466 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
467 pcireg_t vendor = PCI_VENDOR(pa->pa_id);
468 int channel;
469 u_int32_t ideconf;
470 pcireg_t pcib_id, pcib_class;
471 struct pci_attach_args pcib_pa;
472
473 if (pciide_chipen(sc, pa) == 0)
474 return;
475
476 switch (vendor) {
477 case PCI_VENDOR_VIATECH:
478 switch (PCI_PRODUCT(pa->pa_id)) {
479 case PCI_PRODUCT_VIATECH_VT6410_RAID:
480 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
481 "VIA Technologies VT6410 IDE controller\n");
482 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
483 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
484 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
485 break;
486 case PCI_PRODUCT_VIATECH_VX900_IDE:
487 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
488 "VIA Technologies VX900 ATA133 controller\n");
489 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
490 break;
491 default:
492 /*
493 * get a PCI tag for the ISA bridge.
494 */
495 if (pci_find_device(&pcib_pa, via_pcib_match) == 0)
496 goto unknown;
497 pcib_id = pcib_pa.pa_id;
498 pcib_class = pcib_pa.pa_class;
499 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
500 "VIA Technologies ");
501 switch (PCI_PRODUCT(pcib_id)) {
502 case PCI_PRODUCT_VIATECH_VT82C586_ISA:
503 aprint_normal("VT82C586 (Apollo VP) ");
504 if(PCI_REVISION(pcib_class) >= 0x02) {
505 aprint_normal("ATA33 controller\n");
506 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
507 } else {
508 aprint_normal("controller\n");
509 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
510 }
511 break;
512 case PCI_PRODUCT_VIATECH_VT82C596A:
513 aprint_normal("VT82C596A (Apollo Pro) ");
514 if (PCI_REVISION(pcib_class) >= 0x12) {
515 aprint_normal("ATA66 controller\n");
516 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
517 } else {
518 aprint_normal("ATA33 controller\n");
519 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
520 }
521 break;
522 case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
523 aprint_normal("VT82C686A (Apollo KX133) ");
524 if (PCI_REVISION(pcib_class) >= 0x40) {
525 aprint_normal("ATA100 controller\n");
526 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
527 } else {
528 aprint_normal("ATA66 controller\n");
529 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
530 }
531 break;
532 case PCI_PRODUCT_VIATECH_VT8231:
533 aprint_normal("VT8231 ATA100 controller\n");
534 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
535 break;
536 case PCI_PRODUCT_VIATECH_VT8233:
537 aprint_normal("VT8233 ATA100 controller\n");
538 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
539 break;
540 case PCI_PRODUCT_VIATECH_VT8233A:
541 aprint_normal("VT8233A ATA133 controller\n");
542 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
543 break;
544 case PCI_PRODUCT_VIATECH_VT8235:
545 aprint_normal("VT8235 ATA133 controller\n");
546 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
547 break;
548 case PCI_PRODUCT_VIATECH_VT8237:
549 aprint_normal("VT8237 ATA133 controller\n");
550 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
551 break;
552 case PCI_PRODUCT_VIATECH_VT8237A_ISA:
553 aprint_normal("VT8237A ATA133 controller\n");
554 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
555 break;
556 case PCI_PRODUCT_VIATECH_CX700:
557 aprint_normal("CX700 ATA133 controller\n");
558 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
559 break;
560 case PCI_PRODUCT_VIATECH_VT8251:
561 aprint_normal("VT8251 ATA133 controller\n");
562 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
563 break;
564 case PCI_PRODUCT_VIATECH_VX800:
565 aprint_normal("VT800 ATA133 controller\n");
566 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
567 break;
568 case PCI_PRODUCT_VIATECH_VX855:
569 aprint_normal("VT855 ATA133 controller\n");
570 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
571 break;
572 default:
573 unknown:
574 aprint_normal("unknown VIA ATA controller\n");
575 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
576 }
577 break;
578 }
579 sc->sc_apo_regbase = APO_VIA_REGBASE;
580 break;
581 case PCI_VENDOR_AMD:
582 switch (sc->sc_pp->ide_product) {
583 case PCI_PRODUCT_AMD_PBC8111_IDE:
584 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
585 break;
586 case PCI_PRODUCT_AMD_CS5536_IDE:
587 case PCI_PRODUCT_AMD_PBC766_IDE:
588 case PCI_PRODUCT_AMD_PBC768_IDE:
589 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
590 break;
591 default:
592 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
593 }
594 sc->sc_apo_regbase = APO_AMD_REGBASE;
595 break;
596 case PCI_VENDOR_NVIDIA:
597 switch (sc->sc_pp->ide_product) {
598 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
599 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
600 break;
601 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
602 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133:
603 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
604 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133:
605 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133:
606 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133:
607 case PCI_PRODUCT_NVIDIA_MCP04_IDE:
608 case PCI_PRODUCT_NVIDIA_MCP55_IDE:
609 case PCI_PRODUCT_NVIDIA_MCP61_IDE:
610 case PCI_PRODUCT_NVIDIA_MCP65_IDE:
611 case PCI_PRODUCT_NVIDIA_MCP67_IDE:
612 case PCI_PRODUCT_NVIDIA_MCP73_IDE:
613 case PCI_PRODUCT_NVIDIA_MCP77_IDE:
614 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
615 break;
616 }
617 sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
618 break;
619 default:
620 panic("via_chip_map: unknown vendor");
621 }
622
623 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
624 "bus-master DMA support present");
625 pciide_mapreg_dma(sc, pa);
626 aprint_verbose("\n");
627 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
628 if (sc->sc_dma_ok) {
629 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
630 sc->sc_wdcdev.irqack = pciide_irqack;
631 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0)
632 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
633 }
634 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
635 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
636 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel;
637 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
638 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
639 sc->sc_wdcdev.wdc_maxdrives = 2;
640
641 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
642 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
643 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
644
645 wdc_allocate_regs(&sc->sc_wdcdev);
646
647 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
648 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
649 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
650 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
651 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
652 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
653 DEBUG_PROBE);
654
655 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
656 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
657 channel++) {
658 cp = &sc->pciide_channels[channel];
659 if (pciide_chansetup(sc, channel, interface) == 0)
660 continue;
661
662 if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
663 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
664 "%s channel ignored (disabled)\n", cp->name);
665 cp->ata_channel.ch_flags |= ATACH_DISABLED;
666 continue;
667 }
668 via_mapchan(pa, cp, interface, pciide_pci_intr);
669 }
670 }
671
672 static void
673 via_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp,
674 pcireg_t interface, int (*pci_intr)(void *))
675 {
676 struct ata_channel *wdc_cp;
677 struct pciide_softc *sc;
678 prop_bool_t compat_nat_enable;
679
680 wdc_cp = &cp->ata_channel;
681 sc = CHAN_TO_PCIIDE(&cp->ata_channel);
682 compat_nat_enable = prop_dictionary_get(
683 device_properties(sc->sc_wdcdev.sc_atac.atac_dev),
684 "use-compat-native-irq");
685
686 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) {
687 /* native mode with irq 14/15 requested? */
688 if (compat_nat_enable != NULL &&
689 prop_bool_true(compat_nat_enable))
690 via_mapregs_compat_native(pa, cp);
691 else
692 pciide_mapregs_native(pa, cp, pci_intr);
693 } else {
694 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel);
695 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0)
696 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel);
697 }
698 wdcattach(wdc_cp);
699 }
700
701 /*
702 * At least under certain (mis)configurations (e.g. on the "Pegasos" board)
703 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be
704 * programmed to use a single native PCI irq alone. So we install an interrupt
705 * handler for each channel, as in compatibility mode.
706 */
707 static void
708 via_mapregs_compat_native(const struct pci_attach_args *pa,
709 struct pciide_channel *cp)
710 {
711 struct ata_channel *wdc_cp;
712 struct pciide_softc *sc;
713
714 wdc_cp = &cp->ata_channel;
715 sc = CHAN_TO_PCIIDE(&cp->ata_channel);
716
717 /* XXX prevent pciide_mapregs_native from installing a handler */
718 if (sc->sc_pci_ih == NULL)
719 sc->sc_pci_ih = (void *)~0;
720 pciide_mapregs_native(pa, cp, NULL);
721
722 /* interrupts are fixed to 14/15, as in compatibility mode */
723 cp->compat = 1;
724 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) {
725 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
726 cp->ih = pciide_machdep_compat_intr_establish(
727 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel,
728 pciide_compat_intr, cp);
729 if (cp->ih == NULL) {
730 #endif
731 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
732 "no compatibility interrupt for "
733 "use by %s channel\n", cp->name);
734 wdc_cp->ch_flags |= ATACH_DISABLED;
735 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
736 }
737 sc->sc_pci_ih = cp->ih; /* XXX */
738 #endif
739 }
740 }
741
742 static void
743 via_setup_channel(struct ata_channel *chp)
744 {
745 u_int32_t udmatim_reg, datatim_reg;
746 u_int8_t idedma_ctl;
747 int mode, drive, s;
748 struct ata_drive_datas *drvp;
749 struct atac_softc *atac = chp->ch_atac;
750 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
751 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
752 #ifndef PCIIDE_AMD756_ENABLEDMA
753 int rev = PCI_REVISION(
754 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
755 #endif
756
757 idedma_ctl = 0;
758 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
759 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc));
760 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
761 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
762
763 /* setup DMA if needed */
764 pciide_channel_dma_setup(cp);
765
766 for (drive = 0; drive < 2; drive++) {
767 drvp = &chp->ch_drive[drive];
768 /* If no drive, skip */
769 if (drvp->drive_type == ATA_DRIVET_NONE)
770 continue;
771 /* add timing values, setup DMA if needed */
772 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 &&
773 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0)) {
774 mode = drvp->PIO_mode;
775 goto pio;
776 }
777 if ((atac->atac_cap & ATAC_CAP_UDMA) &&
778 (drvp->drive_flags & ATA_DRIVE_UDMA)) {
779 /* use Ultra/DMA */
780 s = splbio();
781 drvp->drive_flags &= ~ATA_DRIVE_DMA;
782 splx(s);
783 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
784 APO_UDMA_EN_MTH(chp->ch_channel, drive);
785 switch (PCI_VENDOR(sc->sc_pci_id)) {
786 case PCI_VENDOR_VIATECH:
787 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) {
788 /* 8233a */
789 udmatim_reg |= APO_UDMA_TIME(
790 chp->ch_channel,
791 drive,
792 via_udma133_tim[drvp->UDMA_mode]);
793 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) {
794 /* 686b */
795 udmatim_reg |= APO_UDMA_TIME(
796 chp->ch_channel,
797 drive,
798 via_udma100_tim[drvp->UDMA_mode]);
799 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) {
800 /* 596b or 686a */
801 udmatim_reg |= APO_UDMA_CLK66(
802 chp->ch_channel);
803 udmatim_reg |= APO_UDMA_TIME(
804 chp->ch_channel,
805 drive,
806 via_udma66_tim[drvp->UDMA_mode]);
807 } else {
808 /* 596a or 586b */
809 udmatim_reg |= APO_UDMA_TIME(
810 chp->ch_channel,
811 drive,
812 via_udma33_tim[drvp->UDMA_mode]);
813 }
814 break;
815 case PCI_VENDOR_AMD:
816 case PCI_VENDOR_NVIDIA:
817 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel,
818 drive, amd7x6_udma_tim[drvp->UDMA_mode]);
819 break;
820 }
821 /* can use PIO timings, MW DMA unused */
822 mode = drvp->PIO_mode;
823 } else {
824 /* use Multiword DMA, but only if revision is OK */
825 s = splbio();
826 drvp->drive_flags &= ~ATA_DRIVE_UDMA;
827 splx(s);
828 #ifndef PCIIDE_AMD756_ENABLEDMA
829 /*
830 * The workaround doesn't seem to be necessary
831 * with all drives, so it can be disabled by
832 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
833 * triggered.
834 */
835 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD &&
836 sc->sc_pp->ide_product ==
837 PCI_PRODUCT_AMD_PBC756_IDE &&
838 AMD756_CHIPREV_DISABLEDMA(rev)) {
839 aprint_normal(
840 "%s:%d:%d: multi-word DMA disabled due "
841 "to chip revision\n",
842 device_xname(
843 sc->sc_wdcdev.sc_atac.atac_dev),
844 chp->ch_channel, drive);
845 mode = drvp->PIO_mode;
846 s = splbio();
847 drvp->drive_flags &= ~ATA_DRIVE_DMA;
848 splx(s);
849 goto pio;
850 }
851 #endif
852 /* mode = min(pio, dma+2) */
853 if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
854 mode = drvp->PIO_mode;
855 else
856 mode = drvp->DMA_mode + 2;
857 }
858 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
859
860 pio: /* setup PIO mode */
861 if (mode <= 2) {
862 drvp->DMA_mode = 0;
863 drvp->PIO_mode = 0;
864 mode = 0;
865 } else {
866 drvp->PIO_mode = mode;
867 drvp->DMA_mode = mode - 2;
868 }
869 datatim_reg |=
870 APO_DATATIM_PULSE(chp->ch_channel, drive,
871 apollo_pio_set[mode]) |
872 APO_DATATIM_RECOV(chp->ch_channel, drive,
873 apollo_pio_rec[mode]);
874 }
875 if (idedma_ctl != 0) {
876 /* Add software bits in status register */
877 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
878 idedma_ctl);
879 }
880 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg);
881 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg);
882 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
883 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
884 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE);
885 }
886
887 static int
888 via_sata_chip_map_common(struct pciide_softc *sc,
889 const struct pci_attach_args *cpa)
890 {
891 pcireg_t csr;
892 int maptype, ret;
893 struct pci_attach_args pac, *pa = &pac;
894
895 pac = *cpa;
896
897 if (pciide_chipen(sc, pa) == 0)
898 return 0;
899
900 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
901 "bus-master DMA support present");
902 pciide_mapreg_dma(sc, pa);
903 aprint_verbose("\n");
904
905 if (sc->sc_dma_ok) {
906 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
907 sc->sc_wdcdev.irqack = pciide_irqack;
908 }
909 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
910 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
911 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
912
913 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
914 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
915 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
916 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
917 sc->sc_wdcdev.wdc_maxdrives = 2;
918
919 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
920 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
921 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
922
923 wdc_allocate_regs(&sc->sc_wdcdev);
924 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
925 PCI_MAPREG_START + 0x14);
926 switch(maptype) {
927 case PCI_MAPREG_TYPE_IO:
928 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
929 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
930 NULL, &sc->sc_ba5_ss);
931 break;
932 case PCI_MAPREG_MEM_TYPE_32BIT:
933 /*
934 * Enable memory-space access if it isn't already there.
935 */
936 csr = pci_conf_read(pa->pa_pc, pa->pa_tag,
937 PCI_COMMAND_STATUS_REG);
938 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 &&
939 (pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) {
940
941 pci_conf_write(pa->pa_pc, pa->pa_tag,
942 PCI_COMMAND_STATUS_REG,
943 csr | PCI_COMMAND_MEM_ENABLE);
944 }
945
946 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
947 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
948 0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
949 NULL, &sc->sc_ba5_ss);
950 break;
951 default:
952 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
953 "couldn't map sata regs, unsupported maptype (0x%x)\n",
954 maptype);
955 return 0;
956 }
957 if (ret != 0) {
958 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
959 "couldn't map sata regs\n");
960 return 0;
961 }
962 return 1;
963 }
964
965 static void
966 via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa,
967 int satareg_shift)
968 {
969 struct pciide_channel *cp;
970 struct ata_channel *wdc_cp;
971 struct wdc_regs *wdr;
972 pcireg_t interface;
973 int channel;
974
975 interface = PCI_INTERFACE(pa->pa_class);
976
977 if (via_sata_chip_map_common(sc, pa) == 0)
978 return;
979
980 if (interface == 0) {
981 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
982 DEBUG_PROBE);
983 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
984 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
985 }
986
987 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
988 sc->sc_wdcdev.wdc_maxdrives = 1;
989 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
990 channel++) {
991 cp = &sc->pciide_channels[channel];
992 if (pciide_chansetup(sc, channel, interface) == 0)
993 continue;
994 wdc_cp = &cp->ata_channel;
995 wdr = CHAN_TO_WDC_REGS(wdc_cp);
996 wdr->sata_iot = sc->sc_ba5_st;
997 wdr->sata_baseioh = sc->sc_ba5_sh;
998 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
999 (wdc_cp->ch_channel << satareg_shift) + 0x0, 4,
1000 &wdr->sata_status) != 0) {
1001 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1002 "couldn't map channel %d sata_status regs\n",
1003 wdc_cp->ch_channel);
1004 continue;
1005 }
1006 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
1007 (wdc_cp->ch_channel << satareg_shift) + 0x4, 4,
1008 &wdr->sata_error) != 0) {
1009 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1010 "couldn't map channel %d sata_error regs\n",
1011 wdc_cp->ch_channel);
1012 continue;
1013 }
1014 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
1015 (wdc_cp->ch_channel << satareg_shift) + 0x8, 4,
1016 &wdr->sata_control) != 0) {
1017 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1018 "couldn't map channel %d sata_control regs\n",
1019 wdc_cp->ch_channel);
1020 continue;
1021 }
1022 pciide_mapchan(pa, cp, interface, pciide_pci_intr);
1023 }
1024 }
1025
1026 static void
1027 via_sata_chip_map_6(struct pciide_softc *sc, const struct pci_attach_args *pa)
1028 {
1029 via_sata_chip_map(sc, pa, 6);
1030 }
1031
1032 static void
1033 via_sata_chip_map_7(struct pciide_softc *sc, const struct pci_attach_args *pa)
1034 {
1035 via_sata_chip_map(sc, pa, 7);
1036 }
1037
1038 static void
1039 via_vt6421_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa)
1040 {
1041 struct pciide_channel *pc;
1042 int chan, reg;
1043 bus_size_t size;
1044
1045 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA,
1046 PCI_MAPREG_TYPE_IO, 0, &sc->sc_dma_iot, &sc->sc_dma_ioh,
1047 NULL, &sc->sc_dma_ios) == 0);
1048 sc->sc_dmat = pa->pa_dmat;
1049 if (sc->sc_dma_ok == 0) {
1050 aprint_verbose(", but unused (couldn't map registers)");
1051 } else {
1052 sc->sc_wdcdev.dma_arg = sc;
1053 sc->sc_wdcdev.dma_init = pciide_dma_init;
1054 sc->sc_wdcdev.dma_start = pciide_dma_start;
1055 sc->sc_wdcdev.dma_finish = pciide_dma_finish;
1056 }
1057
1058 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
1059 PCIIDE_OPTIONS_NODMA) {
1060 aprint_verbose(
1061 ", but unused (forced off by config file)");
1062 sc->sc_dma_ok = 0;
1063 }
1064
1065 if (sc->sc_dma_ok == 0)
1066 return;
1067
1068 for (chan = 0; chan < 4; chan++) {
1069 pc = &sc->pciide_channels[chan];
1070 for (reg = 0; reg < IDEDMA_NREGS; reg++) {
1071 size = 4;
1072 if (size > (IDEDMA_SCH_OFFSET - reg))
1073 size = IDEDMA_SCH_OFFSET - reg;
1074 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh,
1075 IDEDMA_SCH_OFFSET * chan + reg, size,
1076 &pc->dma_iohs[reg]) != 0) {
1077 sc->sc_dma_ok = 0;
1078 aprint_verbose(", but can't subregion offset "
1079 "%d size %lu",
1080 reg, (u_long)size);
1081 return;
1082 }
1083 }
1084 }
1085 }
1086
1087 static int
1088 via_vt6421_chansetup(struct pciide_softc *sc, int channel)
1089 {
1090 struct pciide_channel *cp = &sc->pciide_channels[channel];
1091
1092 sc->wdc_chanarray[channel] = &cp->ata_channel;
1093
1094 cp->ata_channel.ch_channel = channel;
1095 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
1096
1097 return 1;
1098 }
1099
1100 static void
1101 via_sata_chip_map_new(struct pciide_softc *sc,
1102 const struct pci_attach_args *pa)
1103 {
1104 struct pciide_channel *cp;
1105 struct ata_channel *wdc_cp;
1106 struct wdc_regs *wdr;
1107 int channel;
1108 pci_intr_handle_t intrhandle;
1109 const char *intrstr;
1110 int i;
1111 char intrbuf[PCI_INTRSTR_LEN];
1112
1113 if (pciide_chipen(sc, pa) == 0)
1114 return;
1115
1116 sc->sc_apo_regbase = APO_VIA_VT6421_REGBASE;
1117
1118 if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0,
1119 &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) {
1120 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1121 "couldn't map SATA regs\n");
1122 }
1123
1124 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1125 "bus-master DMA support present");
1126 via_vt6421_mapreg_dma(sc, pa);
1127 aprint_verbose("\n");
1128
1129 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
1130 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
1131 if (sc->sc_dma_ok) {
1132 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
1133 sc->sc_wdcdev.irqack = pciide_irqack;
1134 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
1135 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
1136 }
1137 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
1138
1139 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
1140 sc->sc_wdcdev.sc_atac.atac_nchannels = 3;
1141 sc->sc_wdcdev.wdc_maxdrives = 2;
1142
1143 wdc_allocate_regs(&sc->sc_wdcdev);
1144
1145 if (pci_intr_map(pa, &intrhandle) != 0) {
1146 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1147 "couldn't map native-PCI interrupt\n");
1148 return;
1149 }
1150 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf));
1151 sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc,
1152 intrhandle, IPL_BIO, pciide_pci_intr, sc,
1153 device_xname(sc->sc_wdcdev.sc_atac.atac_dev));
1154 if (sc->sc_pci_ih == NULL) {
1155 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1156 "couldn't establish native-PCI interrupt");
1157 if (intrstr != NULL)
1158 aprint_error(" at %s", intrstr);
1159 aprint_error("\n");
1160 return;
1161 }
1162 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1163 "using %s for native-PCI interrupt\n",
1164 intrstr ? intrstr : "unknown interrupt");
1165
1166 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
1167 channel++) {
1168 cp = &sc->pciide_channels[channel];
1169 if (via_vt6421_chansetup(sc, channel) == 0)
1170 continue;
1171 wdc_cp = &cp->ata_channel;
1172 wdr = CHAN_TO_WDC_REGS(wdc_cp);
1173
1174 wdr->sata_iot = sc->sc_ba5_st;
1175 wdr->sata_baseioh = sc->sc_ba5_sh;
1176 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
1177 (wdc_cp->ch_channel << 6) + 0x0, 4,
1178 &wdr->sata_status) != 0) {
1179 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1180 "couldn't map channel %d sata_status regs\n",
1181 wdc_cp->ch_channel);
1182 continue;
1183 }
1184 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
1185 (wdc_cp->ch_channel << 6) + 0x4, 4,
1186 &wdr->sata_error) != 0) {
1187 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1188 "couldn't map channel %d sata_error regs\n",
1189 wdc_cp->ch_channel);
1190 continue;
1191 }
1192 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
1193 (wdc_cp->ch_channel << 6) + 0x8, 4,
1194 &wdr->sata_control) != 0) {
1195 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1196 "couldn't map channel %d sata_control regs\n",
1197 wdc_cp->ch_channel);
1198 continue;
1199 }
1200
1201 if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel),
1202 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh,
1203 NULL, &wdr->cmd_ios) != 0) {
1204 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1205 "couldn't map %s channel regs\n", cp->name);
1206 }
1207 wdr->ctl_iot = wdr->cmd_iot;
1208 for (i = 0; i < WDC_NREG; i++) {
1209 if (bus_space_subregion(wdr->cmd_iot,
1210 wdr->cmd_baseioh, i, i == 0 ? 4 : 1,
1211 &wdr->cmd_iohs[i]) != 0) {
1212 aprint_error_dev(
1213 sc->sc_wdcdev.sc_atac.atac_dev,
1214 "couldn't subregion %s "
1215 "channel cmd regs\n", cp->name);
1216 return;
1217 }
1218 }
1219 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
1220 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) {
1221 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1222 "couldn't map channel %d ctl regs\n", channel);
1223 return;
1224 }
1225 wdc_init_shadow_regs(wdr);
1226 wdr->data32iot = wdr->cmd_iot;
1227 wdr->data32ioh = wdr->cmd_iohs[wd_data];
1228 wdcattach(wdc_cp);
1229 }
1230 }
1231