viaide.c revision 1.89.34.1
1 /* $NetBSD: viaide.c,v 1.89.34.1 2025/08/02 05:57:00 perseant Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.89.34.1 2025/08/02 05:57:00 perseant Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/pci/pciide_apollo_reg.h> 39 40 static int via_pcib_match(const struct pci_attach_args *); 41 static void via_chip_map(struct pciide_softc *, 42 const struct pci_attach_args *); 43 static void via_mapchan(const struct pci_attach_args *, 44 struct pciide_channel *, 45 pcireg_t, int (*)(void *)); 46 static void via_mapregs_compat_native(const struct pci_attach_args *, 47 struct pciide_channel *); 48 static int via_sata_chip_map_common(struct pciide_softc *, 49 const struct pci_attach_args *); 50 static void via_sata_chip_map(struct pciide_softc *, 51 const struct pci_attach_args *, int); 52 static void via_sata_chip_map_6(struct pciide_softc *, 53 const struct pci_attach_args *); 54 static void via_sata_chip_map_7(struct pciide_softc *, 55 const struct pci_attach_args *); 56 static void via_sata_chip_map_new(struct pciide_softc *, 57 const struct pci_attach_args *); 58 static void via_setup_channel(struct ata_channel *); 59 60 static int viaide_match(device_t, cfdata_t, void *); 61 static void viaide_attach(device_t, device_t, void *); 62 static const struct pciide_product_desc * 63 viaide_lookup(pcireg_t); 64 static bool viaide_suspend(device_t, const pmf_qual_t *); 65 static bool viaide_resume(device_t, const pmf_qual_t *); 66 67 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 68 viaide_match, viaide_attach, pciide_detach, NULL); 69 70 static const struct pciide_product_desc pciide_amd_products[] = { 71 { PCI_PRODUCT_AMD_PBC756_IDE, 72 0, 73 "AMD AMD756 IDE Controller", 74 via_chip_map 75 }, 76 { PCI_PRODUCT_AMD_PBC766_IDE, 77 0, 78 "AMD AMD766 IDE Controller", 79 via_chip_map 80 }, 81 { PCI_PRODUCT_AMD_PBC768_IDE, 82 0, 83 "AMD AMD768 IDE Controller", 84 via_chip_map 85 }, 86 { PCI_PRODUCT_AMD_PBC8111_IDE, 87 0, 88 "AMD AMD8111 IDE Controller", 89 via_chip_map 90 }, 91 { PCI_PRODUCT_AMD_CS5536_IDE, 92 0, 93 "AMD CS5536 IDE Controller", 94 via_chip_map 95 }, 96 { 0, 97 0, 98 NULL, 99 NULL 100 } 101 }; 102 103 static const struct pciide_product_desc pciide_nvidia_products[] = { 104 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 105 0, 106 "NVIDIA nForce IDE Controller", 107 via_chip_map 108 }, 109 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 110 0, 111 "NVIDIA nForce2 IDE Controller", 112 via_chip_map 113 }, 114 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 115 0, 116 "NVIDIA nForce2 Ultra 400 IDE Controller", 117 via_chip_map 118 }, 119 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 120 0, 121 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 122 via_sata_chip_map_6 123 }, 124 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 125 0, 126 "NVIDIA nForce3 IDE Controller", 127 via_chip_map 128 }, 129 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 130 0, 131 "NVIDIA nForce3 250 IDE Controller", 132 via_chip_map 133 }, 134 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 135 0, 136 "NVIDIA nForce3 250 Serial ATA Controller", 137 via_sata_chip_map_6 138 }, 139 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 140 0, 141 "NVIDIA nForce3 250 Serial ATA Controller", 142 via_sata_chip_map_6 143 }, 144 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 145 0, 146 "NVIDIA nForce4 IDE Controller", 147 via_chip_map 148 }, 149 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 150 0, 151 "NVIDIA nForce4 Serial ATA Controller", 152 via_sata_chip_map_6 153 }, 154 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 155 0, 156 "NVIDIA nForce4 Serial ATA Controller", 157 via_sata_chip_map_6 158 }, 159 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 160 0, 161 "NVIDIA nForce430 IDE Controller", 162 via_chip_map 163 }, 164 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 165 0, 166 "NVIDIA nForce430 Serial ATA Controller", 167 via_sata_chip_map_6 168 }, 169 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 170 0, 171 "NVIDIA nForce430 Serial ATA Controller", 172 via_sata_chip_map_6 173 }, 174 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 175 0, 176 "NVIDIA MCP04 IDE Controller", 177 via_chip_map 178 }, 179 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 180 0, 181 "NVIDIA MCP04 Serial ATA Controller", 182 via_sata_chip_map_6 183 }, 184 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 185 0, 186 "NVIDIA MCP04 Serial ATA Controller", 187 via_sata_chip_map_6 188 }, 189 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 190 0, 191 "NVIDIA MCP55 IDE Controller", 192 via_chip_map 193 }, 194 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 195 0, 196 "NVIDIA MCP55 Serial ATA Controller", 197 via_sata_chip_map_6 198 }, 199 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 200 0, 201 "NVIDIA MCP55 Serial ATA Controller", 202 via_sata_chip_map_6 203 }, 204 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 205 0, 206 "NVIDIA MCP61 IDE Controller", 207 via_chip_map 208 }, 209 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 210 0, 211 "NVIDIA MCP65 IDE Controller", 212 via_chip_map 213 }, 214 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 215 0, 216 "NVIDIA MCP73 IDE Controller", 217 via_chip_map 218 }, 219 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 220 0, 221 "NVIDIA MCP77 IDE Controller", 222 via_chip_map 223 }, 224 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 225 0, 226 "NVIDIA MCP61 Serial ATA Controller", 227 via_sata_chip_map_6 228 }, 229 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 230 0, 231 "NVIDIA MCP61 Serial ATA Controller", 232 via_sata_chip_map_6 233 }, 234 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 235 0, 236 "NVIDIA MCP61 Serial ATA Controller", 237 via_sata_chip_map_6 238 }, 239 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 240 0, 241 "NVIDIA MCP65 Serial ATA Controller", 242 via_sata_chip_map_6 243 }, 244 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 245 0, 246 "NVIDIA MCP65 Serial ATA Controller", 247 via_sata_chip_map_6 248 }, 249 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 250 0, 251 "NVIDIA MCP65 Serial ATA Controller", 252 via_sata_chip_map_6 253 }, 254 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 255 0, 256 "NVIDIA MCP65 Serial ATA Controller", 257 via_sata_chip_map_6 258 }, 259 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 260 0, 261 "NVIDIA MCP67 IDE Controller", 262 via_chip_map, 263 }, 264 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 265 0, 266 "NVIDIA MCP67 Serial ATA Controller", 267 via_sata_chip_map_6, 268 }, 269 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 270 0, 271 "NVIDIA MCP67 Serial ATA Controller", 272 via_sata_chip_map_6, 273 }, 274 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 275 0, 276 "NVIDIA MCP67 Serial ATA Controller", 277 via_sata_chip_map_6, 278 }, 279 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 280 0, 281 "NVIDIA MCP67 Serial ATA Controller", 282 via_sata_chip_map_6, 283 }, 284 { 0, 285 0, 286 NULL, 287 NULL 288 } 289 }; 290 291 static const struct pciide_product_desc pciide_via_products[] = { 292 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 293 0, 294 NULL, 295 via_chip_map, 296 }, 297 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 298 0, 299 NULL, 300 via_chip_map, 301 }, 302 { PCI_PRODUCT_VIATECH_CX700_IDE, 303 0, 304 "VIA Technologies CX700(M2)/VX700/VX800 SATA/IDE RAID Controller", 305 via_chip_map, 306 }, 307 { PCI_PRODUCT_VIATECH_CX700M2_IDE, 308 0, 309 NULL, 310 via_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_VX900_IDE, 313 0, 314 "VIA Technologies VX900/VX11 SATA controller", 315 via_chip_map, 316 }, 317 { PCI_PRODUCT_VIATECH_VX900_RAID, 318 0, 319 "VIA Technologies VX900/VX11 SATA controller (RAID mode)", 320 via_chip_map, 321 }, 322 { PCI_PRODUCT_VIATECH_VT6410_RAID, 323 0, 324 "VIA Technologies VT6410 IDE controller", 325 via_chip_map, 326 }, 327 { PCI_PRODUCT_VIATECH_VT6415_IDE, 328 0, 329 "VIA Technologies VT6415/VT6330 IDE controller", 330 via_chip_map, 331 }, 332 { PCI_PRODUCT_VIATECH_VT6421_RAID, 333 0, 334 "VIA Technologies VT6421 Serial ATA RAID Controller", 335 via_sata_chip_map_new, 336 }, 337 { PCI_PRODUCT_VIATECH_VT8237_SATA, 338 0, 339 "VIA Technologies VT8237 SATA Controller", 340 via_sata_chip_map_7, 341 }, 342 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 343 0, 344 "VIA Technologies VT8237A SATA Controller", 345 via_sata_chip_map_7, 346 }, 347 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, 348 0, 349 "VIA Technologies VT8237A (5337) SATA Controller", 350 via_sata_chip_map_7, 351 }, 352 /* 353 * The 0x3349 PCI ID may be reused in all modes (IDE, RAID, AHCI). 354 * ahcisata(4) will attach if AHCI mode is selected in the BIOS. 355 * Newer CE revision southbridges use it only in RAID mode. 356 */ 357 { PCI_PRODUCT_VIATECH_VT8251_SATA, 358 0, 359 "VIA Technologies VT8251 SATA Controller", 360 via_chip_map, 361 }, 362 /* 363 * The 0x5287 PCI ID is used only in IDE mode for newer 364 * VT8251 southbridge (CE) revisions. 365 */ 366 { PCI_PRODUCT_VIATECH_VT8251_SATA_2, 367 0, 368 "VIA Technologies VT8251 (5287) SATA Controller", 369 via_chip_map, 370 }, 371 { PCI_PRODUCT_VIATECH_VT8237S_SATA, 372 0, 373 "VIA Technologies VT8237S SATA Controller", 374 via_sata_chip_map_7, 375 }, 376 { PCI_PRODUCT_VIATECH_VT8237S_SATA_RAID, 377 0, 378 "VIA Technologies VT8237S SATA Controller (RAID mode)", 379 via_sata_chip_map_7, 380 }, 381 { PCI_PRODUCT_VIATECH_VT8261_SATA, 382 0, 383 "VIA Technologies VT8261 SATA Controller", 384 via_chip_map, 385 }, 386 { PCI_PRODUCT_VIATECH_VT8261_RAID, 387 0, 388 "VIA Technologies VT8261 SATA Controller (RAID mode)", 389 via_chip_map, 390 }, 391 { 0, 392 0, 393 NULL, 394 NULL 395 } 396 }; 397 398 static const struct pciide_product_desc * 399 viaide_lookup(pcireg_t id) 400 { 401 402 switch (PCI_VENDOR(id)) { 403 case PCI_VENDOR_VIATECH: 404 return (pciide_lookup_product(id, pciide_via_products)); 405 406 case PCI_VENDOR_AMD: 407 return (pciide_lookup_product(id, pciide_amd_products)); 408 409 case PCI_VENDOR_NVIDIA: 410 return (pciide_lookup_product(id, pciide_nvidia_products)); 411 } 412 return (NULL); 413 } 414 415 static int 416 viaide_match(device_t parent, cfdata_t match, void *aux) 417 { 418 const struct pci_attach_args *pa = aux; 419 420 if (viaide_lookup(pa->pa_id) != NULL) 421 return (2); 422 return (0); 423 } 424 425 static void 426 viaide_attach(device_t parent, device_t self, void *aux) 427 { 428 const struct pci_attach_args *pa = aux; 429 struct pciide_softc *sc = device_private(self); 430 const struct pciide_product_desc *pp; 431 432 sc->sc_wdcdev.sc_atac.atac_dev = self; 433 434 pp = viaide_lookup(pa->pa_id); 435 if (pp == NULL) 436 panic("viaide_attach"); 437 pciide_common_attach(sc, pa, pp); 438 439 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 440 aprint_error_dev(self, "couldn't establish power handler\n"); 441 } 442 443 static int 444 via_pcib_match(const struct pci_attach_args *pa) 445 { 446 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 447 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 448 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 449 return (1); 450 return 0; 451 } 452 453 static bool 454 viaide_suspend(device_t dv, const pmf_qual_t *qual) 455 { 456 struct pciide_softc *sc = device_private(dv); 457 458 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 459 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 460 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 461 /* This two are VIA-only, but should be ignored by other devices. */ 462 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 463 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 464 465 return true; 466 } 467 468 static bool 469 viaide_resume(device_t dv, const pmf_qual_t *qual) 470 { 471 struct pciide_softc *sc = device_private(dv); 472 473 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 474 sc->sc_pm_reg[0]); 475 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 476 sc->sc_pm_reg[1]); 477 /* This two are VIA-only, but should be ignored by other devices. */ 478 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 479 sc->sc_pm_reg[2]); 480 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 481 sc->sc_pm_reg[3]); 482 483 return true; 484 } 485 486 static void 487 via_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 488 { 489 struct pciide_channel *cp; 490 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 491 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 492 int channel; 493 u_int32_t ideconf; 494 int no_ideconf = 0; 495 int single_channel = 0; 496 pcireg_t pcib_id, pcib_class; 497 struct pci_attach_args pcib_pa; 498 499 if (pciide_chipen(sc, pa) == 0) 500 return; 501 502 switch (vendor) { 503 case PCI_VENDOR_VIATECH: 504 switch (PCI_PRODUCT(pa->pa_id)) { 505 case PCI_PRODUCT_VIATECH_VT6415_IDE: 506 /* VT6415 is a single channel IDE controller. */ 507 single_channel = 1; 508 /* FALLTHROUGH */ 509 case PCI_PRODUCT_VIATECH_VT6410_RAID: 510 /* 511 * VT6415 uses an unknown offset of the enable chip 512 * register, enable bits needs to be simulated. 513 * 514 * Some add-in VT6410 controllers have both channels 515 * disabled by default. These require explicit enabling 516 * during initialization. 517 */ 518 no_ideconf = 1; 519 /* FALLTHROUGH */ 520 case PCI_PRODUCT_VIATECH_CX700_IDE: 521 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 522 break; 523 case PCI_PRODUCT_VIATECH_VT8251_SATA: 524 /* FALLTHROUGH */ 525 case PCI_PRODUCT_VIATECH_VT8251_SATA_2: 526 /* FALLTHROUGH */ 527 case PCI_PRODUCT_VIATECH_VT8261_SATA: 528 /* FALLTHROUGH */ 529 case PCI_PRODUCT_VIATECH_VT8261_RAID: 530 /* FALLTHROUGH */ 531 case PCI_PRODUCT_VIATECH_VX900_IDE: 532 /* FALLTHROUGH */ 533 case PCI_PRODUCT_VIATECH_VX900_RAID: 534 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 535 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 536 break; 537 default: 538 /* 539 * VIA integrated IDE controllers share the same PCI ID 540 * between different southbridges and chipsets. 541 * To determine their DMA capabilities, get a PCI tag 542 * for the ISA bridge. 543 */ 544 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 545 goto unknown; 546 pcib_id = pcib_pa.pa_id; 547 pcib_class = pcib_pa.pa_class; 548 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 549 "VIA Technologies "); 550 switch (PCI_PRODUCT(pcib_id)) { 551 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 552 aprint_normal("VT82C586 (Apollo VP) "); 553 if(PCI_REVISION(pcib_class) >= 0x02) { 554 aprint_normal("ATA33 controller\n"); 555 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 556 } else { 557 aprint_normal("controller\n"); 558 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 559 } 560 break; 561 case PCI_PRODUCT_VIATECH_VT82C596A: 562 aprint_normal("VT82C596A (Apollo Pro) "); 563 if (PCI_REVISION(pcib_class) >= 0x12) { 564 aprint_normal("ATA66 controller\n"); 565 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 566 } else { 567 aprint_normal("ATA33 controller\n"); 568 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 569 } 570 break; 571 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 572 aprint_normal("VT82C686A (Apollo KX133) "); 573 if (PCI_REVISION(pcib_class) >= 0x40) { 574 aprint_normal("ATA100 controller\n"); 575 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 576 } else { 577 aprint_normal("ATA66 controller\n"); 578 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 579 } 580 break; 581 case PCI_PRODUCT_VIATECH_VT8231: 582 aprint_normal("VT8231 ATA100 controller\n"); 583 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 584 break; 585 case PCI_PRODUCT_VIATECH_VT8233: 586 aprint_normal("VT8233 ATA100 controller\n"); 587 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 588 break; 589 case PCI_PRODUCT_VIATECH_VT8233A: 590 aprint_normal("VT8233A ATA133 controller\n"); 591 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 592 break; 593 case PCI_PRODUCT_VIATECH_VT8235: 594 aprint_normal("VT8235 ATA133 controller\n"); 595 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 596 break; 597 case PCI_PRODUCT_VIATECH_VT8237: 598 aprint_normal("VT8237 ATA133 controller\n"); 599 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 600 break; 601 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 602 aprint_normal("VT8237A ATA133 controller\n"); 603 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 604 break; 605 case PCI_PRODUCT_VIATECH_VT8237S_ISA: 606 aprint_normal("VT8237S ATA133 controller\n"); 607 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 608 break; 609 case PCI_PRODUCT_VIATECH_CX700: 610 aprint_normal("CX700 ATA133 controller\n"); 611 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 612 break; 613 case PCI_PRODUCT_VIATECH_VT8251: 614 aprint_normal("VT8251 ATA133 controller\n"); 615 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 616 break; 617 case PCI_PRODUCT_VIATECH_VT8261: 618 aprint_normal("VT8261 ATA133 controller\n"); 619 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 620 break; 621 case PCI_PRODUCT_VIATECH_VX800: 622 aprint_normal("VX800 ATA133 controller\n"); 623 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 624 break; 625 case PCI_PRODUCT_VIATECH_VX855: 626 aprint_normal("VX855 ATA133 controller\n"); 627 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 628 break; 629 default: 630 unknown: 631 aprint_normal("unknown VIA ATA controller\n"); 632 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 633 } 634 break; 635 } 636 sc->sc_apo_regbase = APO_VIA_REGBASE; 637 break; 638 case PCI_VENDOR_AMD: 639 switch (sc->sc_pp->ide_product) { 640 case PCI_PRODUCT_AMD_PBC8111_IDE: 641 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 642 break; 643 case PCI_PRODUCT_AMD_CS5536_IDE: 644 case PCI_PRODUCT_AMD_PBC766_IDE: 645 case PCI_PRODUCT_AMD_PBC768_IDE: 646 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 647 break; 648 default: 649 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 650 } 651 sc->sc_apo_regbase = APO_AMD_REGBASE; 652 break; 653 case PCI_VENDOR_NVIDIA: 654 switch (sc->sc_pp->ide_product) { 655 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 656 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 657 break; 658 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 659 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 660 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 661 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 662 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 663 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 664 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 665 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 666 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 667 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 668 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 669 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 670 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 671 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 672 break; 673 } 674 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 675 break; 676 default: 677 panic("via_chip_map: unknown vendor"); 678 } 679 680 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 681 "bus-master DMA support present"); 682 pciide_mapreg_dma(sc, pa); 683 aprint_verbose("\n"); 684 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 685 if (sc->sc_dma_ok) { 686 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 687 sc->sc_wdcdev.irqack = pciide_irqack; 688 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 689 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 690 } 691 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 692 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 693 if (sc->sc_wdcdev.sc_atac.atac_set_modes == NULL) 694 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 695 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 696 if (single_channel) 697 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 698 else 699 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 700 sc->sc_wdcdev.wdc_maxdrives = 2; 701 702 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 703 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 704 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 705 if (interface == 0) { 706 ATADEBUG_PRINT(("via_chip_map interface == 0\n"), 707 DEBUG_PROBE); 708 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 709 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 710 } 711 } 712 713 wdc_allocate_regs(&sc->sc_wdcdev); 714 715 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 716 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 717 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 718 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 719 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 720 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 721 DEBUG_PROBE); 722 723 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 724 if ((ideconf & APO_IDECONF_ALWAYS_EN) == 0 && no_ideconf) { 725 ideconf |= APO_IDECONF_ALWAYS_EN; 726 /* 727 * VT6410 requires writing chip enable register bits to enable 728 * the channels. It can be distinguished from VT6415 because 729 * its ideconf register returns a non-zero value (contains 730 * other IDE configuration bits). 731 * 732 * VT6415 returns zero at this offset and likely uses it for 733 * a different purpose or leaves it unused. Bits are simulated 734 * without writing, until the actual offset will be known. 735 */ 736 if (ideconf != APO_IDECONF_ALWAYS_EN) { 737 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 738 ideconf); 739 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, 740 APO_IDECONF(sc)); 741 } 742 } 743 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 744 channel++) { 745 cp = &sc->pciide_channels[channel]; 746 if (pciide_chansetup(sc, channel, interface) == 0) 747 continue; 748 749 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 750 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 751 "%s channel ignored (disabled)\n", cp->name); 752 cp->ata_channel.ch_flags |= ATACH_DISABLED; 753 continue; 754 } 755 via_mapchan(pa, cp, interface, pciide_pci_intr); 756 } 757 } 758 759 static void 760 via_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp, 761 pcireg_t interface, int (*pci_intr)(void *)) 762 { 763 struct ata_channel *wdc_cp; 764 struct pciide_softc *sc; 765 prop_bool_t compat_nat_enable; 766 767 wdc_cp = &cp->ata_channel; 768 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 769 compat_nat_enable = prop_dictionary_get( 770 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 771 "use-compat-native-irq"); 772 773 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 774 /* native mode with irq 14/15 requested? */ 775 if (compat_nat_enable != NULL && 776 prop_bool_true(compat_nat_enable)) 777 via_mapregs_compat_native(pa, cp); 778 else 779 pciide_mapregs_native(pa, cp, pci_intr); 780 } else { 781 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 782 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 783 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 784 } 785 wdcattach(wdc_cp); 786 } 787 788 /* 789 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 790 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 791 * programmed to use a single native PCI irq alone. So we install an interrupt 792 * handler for each channel, as in compatibility mode. 793 */ 794 static void 795 via_mapregs_compat_native(const struct pci_attach_args *pa, 796 struct pciide_channel *cp) 797 { 798 struct ata_channel *wdc_cp; 799 struct pciide_softc *sc; 800 801 wdc_cp = &cp->ata_channel; 802 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 803 804 /* XXX prevent pciide_mapregs_native from installing a handler */ 805 if (sc->sc_pci_ih == NULL) 806 sc->sc_pci_ih = (void *)~0; 807 pciide_mapregs_native(pa, cp, NULL); 808 809 /* interrupts are fixed to 14/15, as in compatibility mode */ 810 cp->compat = 1; 811 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 812 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 813 cp->ih = pciide_machdep_compat_intr_establish( 814 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 815 pciide_compat_intr, cp); 816 if (cp->ih == NULL) { 817 #endif 818 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 819 "no compatibility interrupt for " 820 "use by %s channel\n", cp->name); 821 wdc_cp->ch_flags |= ATACH_DISABLED; 822 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 823 } 824 sc->sc_pci_ih = cp->ih; /* XXX */ 825 #endif 826 } 827 } 828 829 static void 830 via_setup_channel(struct ata_channel *chp) 831 { 832 u_int32_t udmatim_reg, datatim_reg; 833 u_int8_t idedma_ctl; 834 int mode, drive, s; 835 struct ata_drive_datas *drvp; 836 struct atac_softc *atac = chp->ch_atac; 837 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 838 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 839 #ifndef PCIIDE_AMD756_ENABLEDMA 840 int rev = PCI_REVISION( 841 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 842 #endif 843 844 idedma_ctl = 0; 845 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 846 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 847 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 848 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 849 850 /* setup DMA if needed */ 851 pciide_channel_dma_setup(cp); 852 853 for (drive = 0; drive < 2; drive++) { 854 drvp = &chp->ch_drive[drive]; 855 /* If no drive, skip */ 856 if (drvp->drive_type == ATA_DRIVET_NONE) 857 continue; 858 /* add timing values, setup DMA if needed */ 859 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 860 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0)) { 861 mode = drvp->PIO_mode; 862 goto pio; 863 } 864 if ((atac->atac_cap & ATAC_CAP_UDMA) && 865 (drvp->drive_flags & ATA_DRIVE_UDMA)) { 866 /* use Ultra/DMA */ 867 s = splbio(); 868 drvp->drive_flags &= ~ATA_DRIVE_DMA; 869 splx(s); 870 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 871 APO_UDMA_EN_MTH(chp->ch_channel, drive); 872 switch (PCI_VENDOR(sc->sc_pci_id)) { 873 case PCI_VENDOR_VIATECH: 874 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 875 /* 8233a */ 876 udmatim_reg |= APO_UDMA_TIME( 877 chp->ch_channel, 878 drive, 879 via_udma133_tim[drvp->UDMA_mode]); 880 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 881 /* 686b */ 882 udmatim_reg |= APO_UDMA_TIME( 883 chp->ch_channel, 884 drive, 885 via_udma100_tim[drvp->UDMA_mode]); 886 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 887 /* 596b or 686a */ 888 udmatim_reg |= APO_UDMA_CLK66( 889 chp->ch_channel); 890 udmatim_reg |= APO_UDMA_TIME( 891 chp->ch_channel, 892 drive, 893 via_udma66_tim[drvp->UDMA_mode]); 894 } else { 895 /* 596a or 586b */ 896 udmatim_reg |= APO_UDMA_TIME( 897 chp->ch_channel, 898 drive, 899 via_udma33_tim[drvp->UDMA_mode]); 900 } 901 break; 902 case PCI_VENDOR_AMD: 903 case PCI_VENDOR_NVIDIA: 904 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 905 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 906 break; 907 } 908 /* can use PIO timings, MW DMA unused */ 909 mode = drvp->PIO_mode; 910 } else { 911 /* use Multiword DMA, but only if revision is OK */ 912 s = splbio(); 913 drvp->drive_flags &= ~ATA_DRIVE_UDMA; 914 splx(s); 915 #ifndef PCIIDE_AMD756_ENABLEDMA 916 /* 917 * The workaround doesn't seem to be necessary 918 * with all drives, so it can be disabled by 919 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 920 * triggered. 921 */ 922 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 923 sc->sc_pp->ide_product == 924 PCI_PRODUCT_AMD_PBC756_IDE && 925 AMD756_CHIPREV_DISABLEDMA(rev)) { 926 aprint_normal( 927 "%s:%d:%d: multi-word DMA disabled due " 928 "to chip revision\n", 929 device_xname( 930 sc->sc_wdcdev.sc_atac.atac_dev), 931 chp->ch_channel, drive); 932 mode = drvp->PIO_mode; 933 s = splbio(); 934 drvp->drive_flags &= ~ATA_DRIVE_DMA; 935 splx(s); 936 goto pio; 937 } 938 #endif 939 /* mode = min(pio, dma+2) */ 940 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 941 mode = drvp->PIO_mode; 942 else 943 mode = drvp->DMA_mode + 2; 944 } 945 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 946 947 pio: /* setup PIO mode */ 948 if (mode <= 2) { 949 drvp->DMA_mode = 0; 950 drvp->PIO_mode = 0; 951 mode = 0; 952 } else { 953 drvp->PIO_mode = mode; 954 drvp->DMA_mode = mode - 2; 955 } 956 datatim_reg |= 957 APO_DATATIM_PULSE(chp->ch_channel, drive, 958 apollo_pio_set[mode]) | 959 APO_DATATIM_RECOV(chp->ch_channel, drive, 960 apollo_pio_rec[mode]); 961 } 962 if (idedma_ctl != 0) { 963 /* Add software bits in status register */ 964 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 965 idedma_ctl); 966 } 967 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 968 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 969 ATADEBUG_PRINT(("%s: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 970 __func__, 971 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 972 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 973 } 974 975 static int 976 via_sata_chip_map_common(struct pciide_softc *sc, 977 const struct pci_attach_args *cpa) 978 { 979 pcireg_t csr; 980 int maptype, ret; 981 struct pci_attach_args pac, *pa = &pac; 982 983 pac = *cpa; 984 985 if (pciide_chipen(sc, pa) == 0) 986 return 0; 987 988 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 989 "bus-master DMA support present"); 990 pciide_mapreg_dma(sc, pa); 991 aprint_verbose("\n"); 992 993 if (sc->sc_dma_ok) { 994 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 995 sc->sc_wdcdev.irqack = pciide_irqack; 996 } 997 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 998 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 999 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 1000 1001 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 1002 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 1003 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 1004 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 1005 sc->sc_wdcdev.wdc_maxdrives = 2; 1006 1007 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 1008 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 1009 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 1010 1011 wdc_allocate_regs(&sc->sc_wdcdev); 1012 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 1013 PCI_MAPREG_START + 0x14); 1014 switch(maptype) { 1015 case PCI_MAPREG_TYPE_IO: 1016 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 1017 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 1018 NULL, &sc->sc_ba5_ss); 1019 break; 1020 case PCI_MAPREG_MEM_TYPE_32BIT: 1021 /* 1022 * Enable memory-space access if it isn't already there. 1023 */ 1024 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, 1025 PCI_COMMAND_STATUS_REG); 1026 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 && 1027 (pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) { 1028 1029 pci_conf_write(pa->pa_pc, pa->pa_tag, 1030 PCI_COMMAND_STATUS_REG, 1031 csr | PCI_COMMAND_MEM_ENABLE); 1032 } 1033 1034 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 1035 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1036 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 1037 NULL, &sc->sc_ba5_ss); 1038 break; 1039 default: 1040 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1041 "couldn't map sata regs, unsupported maptype (0x%x)\n", 1042 maptype); 1043 return 0; 1044 } 1045 if (ret != 0) { 1046 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1047 "couldn't map sata regs\n"); 1048 return 0; 1049 } 1050 return 1; 1051 } 1052 1053 static void 1054 via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa, 1055 int satareg_shift) 1056 { 1057 struct pciide_channel *cp; 1058 struct ata_channel *wdc_cp; 1059 struct wdc_regs *wdr; 1060 pcireg_t interface; 1061 int channel; 1062 1063 interface = PCI_INTERFACE(pa->pa_class); 1064 1065 if (via_sata_chip_map_common(sc, pa) == 0) 1066 return; 1067 1068 if (interface == 0) { 1069 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 1070 DEBUG_PROBE); 1071 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 1072 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 1073 } 1074 1075 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 1076 sc->sc_wdcdev.wdc_maxdrives = 1; 1077 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1078 channel++) { 1079 cp = &sc->pciide_channels[channel]; 1080 if (pciide_chansetup(sc, channel, interface) == 0) 1081 continue; 1082 wdc_cp = &cp->ata_channel; 1083 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1084 wdr->sata_iot = sc->sc_ba5_st; 1085 wdr->sata_baseioh = sc->sc_ba5_sh; 1086 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1087 (wdc_cp->ch_channel << satareg_shift) + 0x0, 4, 1088 &wdr->sata_status) != 0) { 1089 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1090 "couldn't map channel %d sata_status regs\n", 1091 wdc_cp->ch_channel); 1092 continue; 1093 } 1094 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1095 (wdc_cp->ch_channel << satareg_shift) + 0x4, 4, 1096 &wdr->sata_error) != 0) { 1097 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1098 "couldn't map channel %d sata_error regs\n", 1099 wdc_cp->ch_channel); 1100 continue; 1101 } 1102 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1103 (wdc_cp->ch_channel << satareg_shift) + 0x8, 4, 1104 &wdr->sata_control) != 0) { 1105 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1106 "couldn't map channel %d sata_control regs\n", 1107 wdc_cp->ch_channel); 1108 continue; 1109 } 1110 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 1111 } 1112 } 1113 1114 static void 1115 via_sata_chip_map_6(struct pciide_softc *sc, const struct pci_attach_args *pa) 1116 { 1117 via_sata_chip_map(sc, pa, 6); 1118 } 1119 1120 static void 1121 via_sata_chip_map_7(struct pciide_softc *sc, const struct pci_attach_args *pa) 1122 { 1123 via_sata_chip_map(sc, pa, 7); 1124 } 1125 1126 static void 1127 via_vt6421_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 1128 { 1129 struct pciide_channel *pc; 1130 int chan, reg; 1131 bus_size_t size; 1132 1133 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 1134 PCI_MAPREG_TYPE_IO, 0, &sc->sc_dma_iot, &sc->sc_dma_ioh, 1135 NULL, &sc->sc_dma_ios) == 0); 1136 sc->sc_dmat = pa->pa_dmat; 1137 if (sc->sc_dma_ok == 0) { 1138 aprint_verbose(", but unused (couldn't map registers)"); 1139 } else { 1140 sc->sc_wdcdev.dma_arg = sc; 1141 sc->sc_wdcdev.dma_init = pciide_dma_init; 1142 sc->sc_wdcdev.dma_start = pciide_dma_start; 1143 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 1144 } 1145 1146 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 1147 PCIIDE_OPTIONS_NODMA) { 1148 aprint_verbose( 1149 ", but unused (forced off by config file)"); 1150 sc->sc_dma_ok = 0; 1151 } 1152 1153 if (sc->sc_dma_ok == 0) 1154 return; 1155 1156 for (chan = 0; chan < 4; chan++) { 1157 pc = &sc->pciide_channels[chan]; 1158 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 1159 size = 4; 1160 if (size > (IDEDMA_SCH_OFFSET - reg)) 1161 size = IDEDMA_SCH_OFFSET - reg; 1162 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 1163 IDEDMA_SCH_OFFSET * chan + reg, size, 1164 &pc->dma_iohs[reg]) != 0) { 1165 sc->sc_dma_ok = 0; 1166 aprint_verbose(", but can't subregion offset " 1167 "%d size %lu", 1168 reg, (u_long)size); 1169 return; 1170 } 1171 } 1172 } 1173 } 1174 1175 static int 1176 via_vt6421_chansetup(struct pciide_softc *sc, int channel) 1177 { 1178 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1179 1180 sc->wdc_chanarray[channel] = &cp->ata_channel; 1181 1182 cp->ata_channel.ch_channel = channel; 1183 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 1184 1185 return 1; 1186 } 1187 1188 static void 1189 via_sata_chip_map_new(struct pciide_softc *sc, 1190 const struct pci_attach_args *pa) 1191 { 1192 struct pciide_channel *cp; 1193 struct ata_channel *wdc_cp; 1194 struct wdc_regs *wdr; 1195 int channel; 1196 pci_intr_handle_t intrhandle; 1197 const char *intrstr; 1198 int i; 1199 char intrbuf[PCI_INTRSTR_LEN]; 1200 1201 if (pciide_chipen(sc, pa) == 0) 1202 return; 1203 1204 sc->sc_apo_regbase = APO_VIA_VT6421_REGBASE; 1205 1206 if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0, 1207 &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 1208 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1209 "couldn't map SATA regs\n"); 1210 } 1211 1212 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1213 "bus-master DMA support present"); 1214 via_vt6421_mapreg_dma(sc, pa); 1215 aprint_verbose("\n"); 1216 1217 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 1218 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 1219 if (sc->sc_dma_ok) { 1220 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 1221 sc->sc_wdcdev.irqack = pciide_irqack; 1222 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 1223 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 1224 } 1225 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 1226 1227 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 1228 sc->sc_wdcdev.sc_atac.atac_nchannels = 3; 1229 sc->sc_wdcdev.wdc_maxdrives = 2; 1230 1231 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 1232 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 1233 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 1234 1235 wdc_allocate_regs(&sc->sc_wdcdev); 1236 1237 if (pci_intr_map(pa, &intrhandle) != 0) { 1238 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1239 "couldn't map native-PCI interrupt\n"); 1240 return; 1241 } 1242 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 1243 sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc, 1244 intrhandle, IPL_BIO, pciide_pci_intr, sc, 1245 device_xname(sc->sc_wdcdev.sc_atac.atac_dev)); 1246 if (sc->sc_pci_ih == NULL) { 1247 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1248 "couldn't establish native-PCI interrupt"); 1249 if (intrstr != NULL) 1250 aprint_error(" at %s", intrstr); 1251 aprint_error("\n"); 1252 return; 1253 } 1254 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1255 "using %s for native-PCI interrupt\n", 1256 intrstr ? intrstr : "unknown interrupt"); 1257 1258 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1259 channel++) { 1260 cp = &sc->pciide_channels[channel]; 1261 if (via_vt6421_chansetup(sc, channel) == 0) 1262 continue; 1263 wdc_cp = &cp->ata_channel; 1264 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1265 1266 wdr->sata_iot = sc->sc_ba5_st; 1267 wdr->sata_baseioh = sc->sc_ba5_sh; 1268 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1269 (wdc_cp->ch_channel << 6) + 0x0, 4, 1270 &wdr->sata_status) != 0) { 1271 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1272 "couldn't map channel %d sata_status regs\n", 1273 wdc_cp->ch_channel); 1274 continue; 1275 } 1276 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1277 (wdc_cp->ch_channel << 6) + 0x4, 4, 1278 &wdr->sata_error) != 0) { 1279 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1280 "couldn't map channel %d sata_error regs\n", 1281 wdc_cp->ch_channel); 1282 continue; 1283 } 1284 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1285 (wdc_cp->ch_channel << 6) + 0x8, 4, 1286 &wdr->sata_control) != 0) { 1287 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1288 "couldn't map channel %d sata_control regs\n", 1289 wdc_cp->ch_channel); 1290 continue; 1291 } 1292 1293 if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel), 1294 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1295 NULL, &wdr->cmd_ios) != 0) { 1296 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1297 "couldn't map %s channel regs\n", cp->name); 1298 } 1299 wdr->ctl_iot = wdr->cmd_iot; 1300 for (i = 0; i < WDC_NREG; i++) { 1301 if (bus_space_subregion(wdr->cmd_iot, 1302 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1303 &wdr->cmd_iohs[i]) != 0) { 1304 aprint_error_dev( 1305 sc->sc_wdcdev.sc_atac.atac_dev, 1306 "couldn't subregion %s " 1307 "channel cmd regs\n", cp->name); 1308 return; 1309 } 1310 } 1311 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1312 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1313 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1314 "couldn't map channel %d ctl regs\n", channel); 1315 return; 1316 } 1317 wdc_init_shadow_regs(wdr); 1318 wdr->data32iot = wdr->cmd_iot; 1319 wdr->data32ioh = wdr->cmd_iohs[wd_data]; 1320 wdcattach(wdc_cp); 1321 } 1322 } 1323
Indexes created Sat Oct 18 17:09:52 GMT 2025