viaide.c revision 1.95
1 /* $NetBSD: viaide.c,v 1.95 2025/04/03 15:35:54 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.95 2025/04/03 15:35:54 andvar Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/pci/pciide_apollo_reg.h> 39 40 static int via_pcib_match(const struct pci_attach_args *); 41 static void via_chip_map(struct pciide_softc *, 42 const struct pci_attach_args *); 43 static void via_mapchan(const struct pci_attach_args *, 44 struct pciide_channel *, 45 pcireg_t, int (*)(void *)); 46 static void via_mapregs_compat_native(const struct pci_attach_args *, 47 struct pciide_channel *); 48 static int via_sata_chip_map_common(struct pciide_softc *, 49 const struct pci_attach_args *); 50 static void via_sata_chip_map(struct pciide_softc *, 51 const struct pci_attach_args *, int); 52 static void via_sata_chip_map_6(struct pciide_softc *, 53 const struct pci_attach_args *); 54 static void via_sata_chip_map_7(struct pciide_softc *, 55 const struct pci_attach_args *); 56 static void via_sata_chip_map_new(struct pciide_softc *, 57 const struct pci_attach_args *); 58 static void via_setup_channel(struct ata_channel *); 59 60 static int viaide_match(device_t, cfdata_t, void *); 61 static void viaide_attach(device_t, device_t, void *); 62 static const struct pciide_product_desc * 63 viaide_lookup(pcireg_t); 64 static bool viaide_suspend(device_t, const pmf_qual_t *); 65 static bool viaide_resume(device_t, const pmf_qual_t *); 66 67 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 68 viaide_match, viaide_attach, pciide_detach, NULL); 69 70 static const struct pciide_product_desc pciide_amd_products[] = { 71 { PCI_PRODUCT_AMD_PBC756_IDE, 72 0, 73 "AMD AMD756 IDE Controller", 74 via_chip_map 75 }, 76 { PCI_PRODUCT_AMD_PBC766_IDE, 77 0, 78 "AMD AMD766 IDE Controller", 79 via_chip_map 80 }, 81 { PCI_PRODUCT_AMD_PBC768_IDE, 82 0, 83 "AMD AMD768 IDE Controller", 84 via_chip_map 85 }, 86 { PCI_PRODUCT_AMD_PBC8111_IDE, 87 0, 88 "AMD AMD8111 IDE Controller", 89 via_chip_map 90 }, 91 { PCI_PRODUCT_AMD_CS5536_IDE, 92 0, 93 "AMD CS5536 IDE Controller", 94 via_chip_map 95 }, 96 { 0, 97 0, 98 NULL, 99 NULL 100 } 101 }; 102 103 static const struct pciide_product_desc pciide_nvidia_products[] = { 104 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 105 0, 106 "NVIDIA nForce IDE Controller", 107 via_chip_map 108 }, 109 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 110 0, 111 "NVIDIA nForce2 IDE Controller", 112 via_chip_map 113 }, 114 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 115 0, 116 "NVIDIA nForce2 Ultra 400 IDE Controller", 117 via_chip_map 118 }, 119 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 120 0, 121 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 122 via_sata_chip_map_6 123 }, 124 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 125 0, 126 "NVIDIA nForce3 IDE Controller", 127 via_chip_map 128 }, 129 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 130 0, 131 "NVIDIA nForce3 250 IDE Controller", 132 via_chip_map 133 }, 134 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 135 0, 136 "NVIDIA nForce3 250 Serial ATA Controller", 137 via_sata_chip_map_6 138 }, 139 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 140 0, 141 "NVIDIA nForce3 250 Serial ATA Controller", 142 via_sata_chip_map_6 143 }, 144 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 145 0, 146 "NVIDIA nForce4 IDE Controller", 147 via_chip_map 148 }, 149 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 150 0, 151 "NVIDIA nForce4 Serial ATA Controller", 152 via_sata_chip_map_6 153 }, 154 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 155 0, 156 "NVIDIA nForce4 Serial ATA Controller", 157 via_sata_chip_map_6 158 }, 159 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 160 0, 161 "NVIDIA nForce430 IDE Controller", 162 via_chip_map 163 }, 164 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 165 0, 166 "NVIDIA nForce430 Serial ATA Controller", 167 via_sata_chip_map_6 168 }, 169 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 170 0, 171 "NVIDIA nForce430 Serial ATA Controller", 172 via_sata_chip_map_6 173 }, 174 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 175 0, 176 "NVIDIA MCP04 IDE Controller", 177 via_chip_map 178 }, 179 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 180 0, 181 "NVIDIA MCP04 Serial ATA Controller", 182 via_sata_chip_map_6 183 }, 184 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 185 0, 186 "NVIDIA MCP04 Serial ATA Controller", 187 via_sata_chip_map_6 188 }, 189 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 190 0, 191 "NVIDIA MCP55 IDE Controller", 192 via_chip_map 193 }, 194 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 195 0, 196 "NVIDIA MCP55 Serial ATA Controller", 197 via_sata_chip_map_6 198 }, 199 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 200 0, 201 "NVIDIA MCP55 Serial ATA Controller", 202 via_sata_chip_map_6 203 }, 204 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 205 0, 206 "NVIDIA MCP61 IDE Controller", 207 via_chip_map 208 }, 209 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 210 0, 211 "NVIDIA MCP65 IDE Controller", 212 via_chip_map 213 }, 214 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 215 0, 216 "NVIDIA MCP73 IDE Controller", 217 via_chip_map 218 }, 219 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 220 0, 221 "NVIDIA MCP77 IDE Controller", 222 via_chip_map 223 }, 224 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 225 0, 226 "NVIDIA MCP61 Serial ATA Controller", 227 via_sata_chip_map_6 228 }, 229 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 230 0, 231 "NVIDIA MCP61 Serial ATA Controller", 232 via_sata_chip_map_6 233 }, 234 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 235 0, 236 "NVIDIA MCP61 Serial ATA Controller", 237 via_sata_chip_map_6 238 }, 239 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 240 0, 241 "NVIDIA MCP65 Serial ATA Controller", 242 via_sata_chip_map_6 243 }, 244 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 245 0, 246 "NVIDIA MCP65 Serial ATA Controller", 247 via_sata_chip_map_6 248 }, 249 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 250 0, 251 "NVIDIA MCP65 Serial ATA Controller", 252 via_sata_chip_map_6 253 }, 254 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 255 0, 256 "NVIDIA MCP65 Serial ATA Controller", 257 via_sata_chip_map_6 258 }, 259 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 260 0, 261 "NVIDIA MCP67 IDE Controller", 262 via_chip_map, 263 }, 264 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 265 0, 266 "NVIDIA MCP67 Serial ATA Controller", 267 via_sata_chip_map_6, 268 }, 269 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 270 0, 271 "NVIDIA MCP67 Serial ATA Controller", 272 via_sata_chip_map_6, 273 }, 274 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 275 0, 276 "NVIDIA MCP67 Serial ATA Controller", 277 via_sata_chip_map_6, 278 }, 279 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 280 0, 281 "NVIDIA MCP67 Serial ATA Controller", 282 via_sata_chip_map_6, 283 }, 284 { 0, 285 0, 286 NULL, 287 NULL 288 } 289 }; 290 291 static const struct pciide_product_desc pciide_via_products[] = { 292 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 293 0, 294 NULL, 295 via_chip_map, 296 }, 297 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 298 0, 299 NULL, 300 via_chip_map, 301 }, 302 { PCI_PRODUCT_VIATECH_CX700_IDE, 303 0, 304 "VIA Technologies CX700(M2)/VX700/VX800 SATA/IDE RAID Controller", 305 via_chip_map, 306 }, 307 { PCI_PRODUCT_VIATECH_CX700M2_IDE, 308 0, 309 NULL, 310 via_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_VX900_IDE, 313 0, 314 "VIA Technologies VX900 SATA controller", 315 via_chip_map, 316 }, 317 { PCI_PRODUCT_VIATECH_VT6410_RAID, 318 0, 319 "VIA Technologies VT6410 IDE controller", 320 via_chip_map, 321 }, 322 { PCI_PRODUCT_VIATECH_VT6415_IDE, 323 0, 324 "VIA Technologies VT6415/VT6330 IDE controller", 325 via_chip_map, 326 }, 327 { PCI_PRODUCT_VIATECH_VT6421_RAID, 328 0, 329 "VIA Technologies VT6421 Serial ATA RAID Controller", 330 via_sata_chip_map_new, 331 }, 332 { PCI_PRODUCT_VIATECH_VT8237_SATA, 333 0, 334 "VIA Technologies VT8237 SATA Controller", 335 via_sata_chip_map_7, 336 }, 337 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 338 0, 339 "VIA Technologies VT8237A SATA Controller", 340 via_sata_chip_map_7, 341 }, 342 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, 343 0, 344 "VIA Technologies VT8237A (5337) SATA Controller", 345 via_sata_chip_map_7, 346 }, 347 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 348 0, 349 "VIA Technologies VT8237R SATA Controller", 350 via_sata_chip_map_7, 351 }, 352 { PCI_PRODUCT_VIATECH_VT8237S_SATA, 353 0, 354 "VIA Technologies VT8237S SATA Controller", 355 via_sata_chip_map_7, 356 }, 357 { PCI_PRODUCT_VIATECH_VT8237S_SATA_RAID, 358 0, 359 "VIA Technologies VT8237S SATA Controller (RAID mode)", 360 via_sata_chip_map_7, 361 }, 362 { PCI_PRODUCT_VIATECH_VT8261_SATA, 363 0, 364 "VIA Technologies VT8261 SATA Controller", 365 via_chip_map, 366 }, 367 { PCI_PRODUCT_VIATECH_VT8261_RAID, 368 0, 369 "VIA Technologies VT8261 SATA Controller (RAID mode)", 370 via_sata_chip_map_7, 371 }, 372 { 0, 373 0, 374 NULL, 375 NULL 376 } 377 }; 378 379 static const struct pciide_product_desc * 380 viaide_lookup(pcireg_t id) 381 { 382 383 switch (PCI_VENDOR(id)) { 384 case PCI_VENDOR_VIATECH: 385 return (pciide_lookup_product(id, pciide_via_products)); 386 387 case PCI_VENDOR_AMD: 388 return (pciide_lookup_product(id, pciide_amd_products)); 389 390 case PCI_VENDOR_NVIDIA: 391 return (pciide_lookup_product(id, pciide_nvidia_products)); 392 } 393 return (NULL); 394 } 395 396 static int 397 viaide_match(device_t parent, cfdata_t match, void *aux) 398 { 399 const struct pci_attach_args *pa = aux; 400 401 if (viaide_lookup(pa->pa_id) != NULL) 402 return (2); 403 return (0); 404 } 405 406 static void 407 viaide_attach(device_t parent, device_t self, void *aux) 408 { 409 const struct pci_attach_args *pa = aux; 410 struct pciide_softc *sc = device_private(self); 411 const struct pciide_product_desc *pp; 412 413 sc->sc_wdcdev.sc_atac.atac_dev = self; 414 415 pp = viaide_lookup(pa->pa_id); 416 if (pp == NULL) 417 panic("viaide_attach"); 418 pciide_common_attach(sc, pa, pp); 419 420 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 421 aprint_error_dev(self, "couldn't establish power handler\n"); 422 } 423 424 static int 425 via_pcib_match(const struct pci_attach_args *pa) 426 { 427 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 428 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 429 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 430 return (1); 431 return 0; 432 } 433 434 static bool 435 viaide_suspend(device_t dv, const pmf_qual_t *qual) 436 { 437 struct pciide_softc *sc = device_private(dv); 438 439 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 440 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 441 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 442 /* This two are VIA-only, but should be ignored by other devices. */ 443 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 444 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 445 446 return true; 447 } 448 449 static bool 450 viaide_resume(device_t dv, const pmf_qual_t *qual) 451 { 452 struct pciide_softc *sc = device_private(dv); 453 454 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 455 sc->sc_pm_reg[0]); 456 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 457 sc->sc_pm_reg[1]); 458 /* This two are VIA-only, but should be ignored by other devices. */ 459 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 460 sc->sc_pm_reg[2]); 461 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 462 sc->sc_pm_reg[3]); 463 464 return true; 465 } 466 467 static void 468 via_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 469 { 470 struct pciide_channel *cp; 471 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 472 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 473 int channel; 474 u_int32_t ideconf; 475 int no_ideconf = 0; 476 int single_channel = 0; 477 pcireg_t pcib_id, pcib_class; 478 struct pci_attach_args pcib_pa; 479 480 if (pciide_chipen(sc, pa) == 0) 481 return; 482 483 switch (vendor) { 484 case PCI_VENDOR_VIATECH: 485 switch (PCI_PRODUCT(pa->pa_id)) { 486 case PCI_PRODUCT_VIATECH_VT6415_IDE: 487 /* VT6415 is a single channel IDE controller. */ 488 single_channel = 1; 489 /* FALLTHROUGH */ 490 case PCI_PRODUCT_VIATECH_VT6410_RAID: 491 /* 492 * The chip enable register of the VT6410/VT6415 493 * controllers may not be set by the hardware. 494 * Treat their channels as always enabled. 495 */ 496 no_ideconf = 1; 497 /* FALLTHROUGH */ 498 case PCI_PRODUCT_VIATECH_CX700_IDE: 499 /* FALLTHROUGH */ 500 case PCI_PRODUCT_VIATECH_VT8261_SATA: 501 /* FALLTHROUGH */ 502 case PCI_PRODUCT_VIATECH_VX900_IDE: 503 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 504 break; 505 default: 506 /* 507 * get a PCI tag for the ISA bridge. 508 */ 509 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 510 goto unknown; 511 pcib_id = pcib_pa.pa_id; 512 pcib_class = pcib_pa.pa_class; 513 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 514 "VIA Technologies "); 515 switch (PCI_PRODUCT(pcib_id)) { 516 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 517 aprint_normal("VT82C586 (Apollo VP) "); 518 if(PCI_REVISION(pcib_class) >= 0x02) { 519 aprint_normal("ATA33 controller\n"); 520 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 521 } else { 522 aprint_normal("controller\n"); 523 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 524 } 525 break; 526 case PCI_PRODUCT_VIATECH_VT82C596A: 527 aprint_normal("VT82C596A (Apollo Pro) "); 528 if (PCI_REVISION(pcib_class) >= 0x12) { 529 aprint_normal("ATA66 controller\n"); 530 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 531 } else { 532 aprint_normal("ATA33 controller\n"); 533 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 534 } 535 break; 536 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 537 aprint_normal("VT82C686A (Apollo KX133) "); 538 if (PCI_REVISION(pcib_class) >= 0x40) { 539 aprint_normal("ATA100 controller\n"); 540 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 541 } else { 542 aprint_normal("ATA66 controller\n"); 543 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 544 } 545 break; 546 case PCI_PRODUCT_VIATECH_VT8231: 547 aprint_normal("VT8231 ATA100 controller\n"); 548 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 549 break; 550 case PCI_PRODUCT_VIATECH_VT8233: 551 aprint_normal("VT8233 ATA100 controller\n"); 552 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 553 break; 554 case PCI_PRODUCT_VIATECH_VT8233A: 555 aprint_normal("VT8233A ATA133 controller\n"); 556 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 557 break; 558 case PCI_PRODUCT_VIATECH_VT8235: 559 aprint_normal("VT8235 ATA133 controller\n"); 560 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 561 break; 562 case PCI_PRODUCT_VIATECH_VT8237: 563 aprint_normal("VT8237 ATA133 controller\n"); 564 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 565 break; 566 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 567 aprint_normal("VT8237A ATA133 controller\n"); 568 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 569 break; 570 case PCI_PRODUCT_VIATECH_VT8237S_ISA: 571 aprint_normal("VT8237S ATA133 controller\n"); 572 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 573 break; 574 case PCI_PRODUCT_VIATECH_CX700: 575 aprint_normal("CX700 ATA133 controller\n"); 576 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 577 break; 578 case PCI_PRODUCT_VIATECH_VT8251: 579 aprint_normal("VT8251 ATA133 controller\n"); 580 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 581 break; 582 case PCI_PRODUCT_VIATECH_VT8261: 583 aprint_normal("VT8261 ATA133 controller\n"); 584 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 585 break; 586 case PCI_PRODUCT_VIATECH_VX800: 587 aprint_normal("VX800 ATA133 controller\n"); 588 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 589 break; 590 case PCI_PRODUCT_VIATECH_VX855: 591 aprint_normal("VX855 ATA133 controller\n"); 592 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 593 break; 594 default: 595 unknown: 596 aprint_normal("unknown VIA ATA controller\n"); 597 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 598 } 599 break; 600 } 601 sc->sc_apo_regbase = APO_VIA_REGBASE; 602 break; 603 case PCI_VENDOR_AMD: 604 switch (sc->sc_pp->ide_product) { 605 case PCI_PRODUCT_AMD_PBC8111_IDE: 606 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 607 break; 608 case PCI_PRODUCT_AMD_CS5536_IDE: 609 case PCI_PRODUCT_AMD_PBC766_IDE: 610 case PCI_PRODUCT_AMD_PBC768_IDE: 611 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 612 break; 613 default: 614 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 615 } 616 sc->sc_apo_regbase = APO_AMD_REGBASE; 617 break; 618 case PCI_VENDOR_NVIDIA: 619 switch (sc->sc_pp->ide_product) { 620 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 621 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 622 break; 623 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 624 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 625 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 626 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 627 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 628 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 629 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 630 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 631 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 632 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 633 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 634 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 635 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 636 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 637 break; 638 } 639 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 640 break; 641 default: 642 panic("via_chip_map: unknown vendor"); 643 } 644 645 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 646 "bus-master DMA support present"); 647 pciide_mapreg_dma(sc, pa); 648 aprint_verbose("\n"); 649 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 650 if (sc->sc_dma_ok) { 651 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 652 sc->sc_wdcdev.irqack = pciide_irqack; 653 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 654 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 655 } 656 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 657 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 658 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 659 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 660 if (single_channel) 661 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 662 else 663 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 664 sc->sc_wdcdev.wdc_maxdrives = 2; 665 666 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 667 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 668 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 669 if (interface == 0) { 670 ATADEBUG_PRINT(("via_chip_map interface == 0\n"), 671 DEBUG_PROBE); 672 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 673 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 674 } 675 } 676 677 wdc_allocate_regs(&sc->sc_wdcdev); 678 679 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 680 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 681 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 682 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 683 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 684 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 685 DEBUG_PROBE); 686 687 if (no_ideconf) 688 ideconf = APO_IDECONF_ALWAYS_EN; 689 else 690 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 691 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 692 channel++) { 693 cp = &sc->pciide_channels[channel]; 694 if (pciide_chansetup(sc, channel, interface) == 0) 695 continue; 696 697 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 698 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 699 "%s channel ignored (disabled)\n", cp->name); 700 cp->ata_channel.ch_flags |= ATACH_DISABLED; 701 continue; 702 } 703 via_mapchan(pa, cp, interface, pciide_pci_intr); 704 } 705 } 706 707 static void 708 via_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp, 709 pcireg_t interface, int (*pci_intr)(void *)) 710 { 711 struct ata_channel *wdc_cp; 712 struct pciide_softc *sc; 713 prop_bool_t compat_nat_enable; 714 715 wdc_cp = &cp->ata_channel; 716 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 717 compat_nat_enable = prop_dictionary_get( 718 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 719 "use-compat-native-irq"); 720 721 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 722 /* native mode with irq 14/15 requested? */ 723 if (compat_nat_enable != NULL && 724 prop_bool_true(compat_nat_enable)) 725 via_mapregs_compat_native(pa, cp); 726 else 727 pciide_mapregs_native(pa, cp, pci_intr); 728 } else { 729 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 730 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 731 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 732 } 733 wdcattach(wdc_cp); 734 } 735 736 /* 737 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 738 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 739 * programmed to use a single native PCI irq alone. So we install an interrupt 740 * handler for each channel, as in compatibility mode. 741 */ 742 static void 743 via_mapregs_compat_native(const struct pci_attach_args *pa, 744 struct pciide_channel *cp) 745 { 746 struct ata_channel *wdc_cp; 747 struct pciide_softc *sc; 748 749 wdc_cp = &cp->ata_channel; 750 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 751 752 /* XXX prevent pciide_mapregs_native from installing a handler */ 753 if (sc->sc_pci_ih == NULL) 754 sc->sc_pci_ih = (void *)~0; 755 pciide_mapregs_native(pa, cp, NULL); 756 757 /* interrupts are fixed to 14/15, as in compatibility mode */ 758 cp->compat = 1; 759 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 760 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 761 cp->ih = pciide_machdep_compat_intr_establish( 762 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 763 pciide_compat_intr, cp); 764 if (cp->ih == NULL) { 765 #endif 766 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 767 "no compatibility interrupt for " 768 "use by %s channel\n", cp->name); 769 wdc_cp->ch_flags |= ATACH_DISABLED; 770 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 771 } 772 sc->sc_pci_ih = cp->ih; /* XXX */ 773 #endif 774 } 775 } 776 777 static void 778 via_setup_channel(struct ata_channel *chp) 779 { 780 u_int32_t udmatim_reg, datatim_reg; 781 u_int8_t idedma_ctl; 782 int mode, drive, s; 783 struct ata_drive_datas *drvp; 784 struct atac_softc *atac = chp->ch_atac; 785 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 786 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 787 #ifndef PCIIDE_AMD756_ENABLEDMA 788 int rev = PCI_REVISION( 789 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 790 #endif 791 792 idedma_ctl = 0; 793 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 794 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 795 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 796 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 797 798 /* setup DMA if needed */ 799 pciide_channel_dma_setup(cp); 800 801 for (drive = 0; drive < 2; drive++) { 802 drvp = &chp->ch_drive[drive]; 803 /* If no drive, skip */ 804 if (drvp->drive_type == ATA_DRIVET_NONE) 805 continue; 806 /* add timing values, setup DMA if needed */ 807 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 808 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0)) { 809 mode = drvp->PIO_mode; 810 goto pio; 811 } 812 if ((atac->atac_cap & ATAC_CAP_UDMA) && 813 (drvp->drive_flags & ATA_DRIVE_UDMA)) { 814 /* use Ultra/DMA */ 815 s = splbio(); 816 drvp->drive_flags &= ~ATA_DRIVE_DMA; 817 splx(s); 818 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 819 APO_UDMA_EN_MTH(chp->ch_channel, drive); 820 switch (PCI_VENDOR(sc->sc_pci_id)) { 821 case PCI_VENDOR_VIATECH: 822 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 823 /* 8233a */ 824 udmatim_reg |= APO_UDMA_TIME( 825 chp->ch_channel, 826 drive, 827 via_udma133_tim[drvp->UDMA_mode]); 828 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 829 /* 686b */ 830 udmatim_reg |= APO_UDMA_TIME( 831 chp->ch_channel, 832 drive, 833 via_udma100_tim[drvp->UDMA_mode]); 834 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 835 /* 596b or 686a */ 836 udmatim_reg |= APO_UDMA_CLK66( 837 chp->ch_channel); 838 udmatim_reg |= APO_UDMA_TIME( 839 chp->ch_channel, 840 drive, 841 via_udma66_tim[drvp->UDMA_mode]); 842 } else { 843 /* 596a or 586b */ 844 udmatim_reg |= APO_UDMA_TIME( 845 chp->ch_channel, 846 drive, 847 via_udma33_tim[drvp->UDMA_mode]); 848 } 849 break; 850 case PCI_VENDOR_AMD: 851 case PCI_VENDOR_NVIDIA: 852 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 853 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 854 break; 855 } 856 /* can use PIO timings, MW DMA unused */ 857 mode = drvp->PIO_mode; 858 } else { 859 /* use Multiword DMA, but only if revision is OK */ 860 s = splbio(); 861 drvp->drive_flags &= ~ATA_DRIVE_UDMA; 862 splx(s); 863 #ifndef PCIIDE_AMD756_ENABLEDMA 864 /* 865 * The workaround doesn't seem to be necessary 866 * with all drives, so it can be disabled by 867 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 868 * triggered. 869 */ 870 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 871 sc->sc_pp->ide_product == 872 PCI_PRODUCT_AMD_PBC756_IDE && 873 AMD756_CHIPREV_DISABLEDMA(rev)) { 874 aprint_normal( 875 "%s:%d:%d: multi-word DMA disabled due " 876 "to chip revision\n", 877 device_xname( 878 sc->sc_wdcdev.sc_atac.atac_dev), 879 chp->ch_channel, drive); 880 mode = drvp->PIO_mode; 881 s = splbio(); 882 drvp->drive_flags &= ~ATA_DRIVE_DMA; 883 splx(s); 884 goto pio; 885 } 886 #endif 887 /* mode = min(pio, dma+2) */ 888 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 889 mode = drvp->PIO_mode; 890 else 891 mode = drvp->DMA_mode + 2; 892 } 893 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 894 895 pio: /* setup PIO mode */ 896 if (mode <= 2) { 897 drvp->DMA_mode = 0; 898 drvp->PIO_mode = 0; 899 mode = 0; 900 } else { 901 drvp->PIO_mode = mode; 902 drvp->DMA_mode = mode - 2; 903 } 904 datatim_reg |= 905 APO_DATATIM_PULSE(chp->ch_channel, drive, 906 apollo_pio_set[mode]) | 907 APO_DATATIM_RECOV(chp->ch_channel, drive, 908 apollo_pio_rec[mode]); 909 } 910 if (idedma_ctl != 0) { 911 /* Add software bits in status register */ 912 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 913 idedma_ctl); 914 } 915 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 916 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 917 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 918 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 919 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 920 } 921 922 static int 923 via_sata_chip_map_common(struct pciide_softc *sc, 924 const struct pci_attach_args *cpa) 925 { 926 pcireg_t csr; 927 int maptype, ret; 928 struct pci_attach_args pac, *pa = &pac; 929 930 pac = *cpa; 931 932 if (pciide_chipen(sc, pa) == 0) 933 return 0; 934 935 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 936 "bus-master DMA support present"); 937 pciide_mapreg_dma(sc, pa); 938 aprint_verbose("\n"); 939 940 if (sc->sc_dma_ok) { 941 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 942 sc->sc_wdcdev.irqack = pciide_irqack; 943 } 944 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 945 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 946 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 947 948 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 949 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 950 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 951 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 952 sc->sc_wdcdev.wdc_maxdrives = 2; 953 954 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 955 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 956 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 957 958 wdc_allocate_regs(&sc->sc_wdcdev); 959 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 960 PCI_MAPREG_START + 0x14); 961 switch(maptype) { 962 case PCI_MAPREG_TYPE_IO: 963 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 964 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 965 NULL, &sc->sc_ba5_ss); 966 break; 967 case PCI_MAPREG_MEM_TYPE_32BIT: 968 /* 969 * Enable memory-space access if it isn't already there. 970 */ 971 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, 972 PCI_COMMAND_STATUS_REG); 973 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 && 974 (pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) { 975 976 pci_conf_write(pa->pa_pc, pa->pa_tag, 977 PCI_COMMAND_STATUS_REG, 978 csr | PCI_COMMAND_MEM_ENABLE); 979 } 980 981 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 982 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 983 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 984 NULL, &sc->sc_ba5_ss); 985 break; 986 default: 987 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 988 "couldn't map sata regs, unsupported maptype (0x%x)\n", 989 maptype); 990 return 0; 991 } 992 if (ret != 0) { 993 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 994 "couldn't map sata regs\n"); 995 return 0; 996 } 997 return 1; 998 } 999 1000 static void 1001 via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa, 1002 int satareg_shift) 1003 { 1004 struct pciide_channel *cp; 1005 struct ata_channel *wdc_cp; 1006 struct wdc_regs *wdr; 1007 pcireg_t interface; 1008 int channel; 1009 1010 interface = PCI_INTERFACE(pa->pa_class); 1011 1012 if (via_sata_chip_map_common(sc, pa) == 0) 1013 return; 1014 1015 if (interface == 0) { 1016 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 1017 DEBUG_PROBE); 1018 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 1019 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 1020 } 1021 1022 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 1023 sc->sc_wdcdev.wdc_maxdrives = 1; 1024 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1025 channel++) { 1026 cp = &sc->pciide_channels[channel]; 1027 if (pciide_chansetup(sc, channel, interface) == 0) 1028 continue; 1029 wdc_cp = &cp->ata_channel; 1030 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1031 wdr->sata_iot = sc->sc_ba5_st; 1032 wdr->sata_baseioh = sc->sc_ba5_sh; 1033 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1034 (wdc_cp->ch_channel << satareg_shift) + 0x0, 4, 1035 &wdr->sata_status) != 0) { 1036 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1037 "couldn't map channel %d sata_status regs\n", 1038 wdc_cp->ch_channel); 1039 continue; 1040 } 1041 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1042 (wdc_cp->ch_channel << satareg_shift) + 0x4, 4, 1043 &wdr->sata_error) != 0) { 1044 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1045 "couldn't map channel %d sata_error regs\n", 1046 wdc_cp->ch_channel); 1047 continue; 1048 } 1049 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1050 (wdc_cp->ch_channel << satareg_shift) + 0x8, 4, 1051 &wdr->sata_control) != 0) { 1052 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1053 "couldn't map channel %d sata_control regs\n", 1054 wdc_cp->ch_channel); 1055 continue; 1056 } 1057 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 1058 } 1059 } 1060 1061 static void 1062 via_sata_chip_map_6(struct pciide_softc *sc, const struct pci_attach_args *pa) 1063 { 1064 via_sata_chip_map(sc, pa, 6); 1065 } 1066 1067 static void 1068 via_sata_chip_map_7(struct pciide_softc *sc, const struct pci_attach_args *pa) 1069 { 1070 via_sata_chip_map(sc, pa, 7); 1071 } 1072 1073 static void 1074 via_vt6421_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 1075 { 1076 struct pciide_channel *pc; 1077 int chan, reg; 1078 bus_size_t size; 1079 1080 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 1081 PCI_MAPREG_TYPE_IO, 0, &sc->sc_dma_iot, &sc->sc_dma_ioh, 1082 NULL, &sc->sc_dma_ios) == 0); 1083 sc->sc_dmat = pa->pa_dmat; 1084 if (sc->sc_dma_ok == 0) { 1085 aprint_verbose(", but unused (couldn't map registers)"); 1086 } else { 1087 sc->sc_wdcdev.dma_arg = sc; 1088 sc->sc_wdcdev.dma_init = pciide_dma_init; 1089 sc->sc_wdcdev.dma_start = pciide_dma_start; 1090 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 1091 } 1092 1093 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 1094 PCIIDE_OPTIONS_NODMA) { 1095 aprint_verbose( 1096 ", but unused (forced off by config file)"); 1097 sc->sc_dma_ok = 0; 1098 } 1099 1100 if (sc->sc_dma_ok == 0) 1101 return; 1102 1103 for (chan = 0; chan < 4; chan++) { 1104 pc = &sc->pciide_channels[chan]; 1105 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 1106 size = 4; 1107 if (size > (IDEDMA_SCH_OFFSET - reg)) 1108 size = IDEDMA_SCH_OFFSET - reg; 1109 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 1110 IDEDMA_SCH_OFFSET * chan + reg, size, 1111 &pc->dma_iohs[reg]) != 0) { 1112 sc->sc_dma_ok = 0; 1113 aprint_verbose(", but can't subregion offset " 1114 "%d size %lu", 1115 reg, (u_long)size); 1116 return; 1117 } 1118 } 1119 } 1120 } 1121 1122 static int 1123 via_vt6421_chansetup(struct pciide_softc *sc, int channel) 1124 { 1125 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1126 1127 sc->wdc_chanarray[channel] = &cp->ata_channel; 1128 1129 cp->ata_channel.ch_channel = channel; 1130 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 1131 1132 return 1; 1133 } 1134 1135 static void 1136 via_sata_chip_map_new(struct pciide_softc *sc, 1137 const struct pci_attach_args *pa) 1138 { 1139 struct pciide_channel *cp; 1140 struct ata_channel *wdc_cp; 1141 struct wdc_regs *wdr; 1142 int channel; 1143 pci_intr_handle_t intrhandle; 1144 const char *intrstr; 1145 int i; 1146 char intrbuf[PCI_INTRSTR_LEN]; 1147 1148 if (pciide_chipen(sc, pa) == 0) 1149 return; 1150 1151 sc->sc_apo_regbase = APO_VIA_VT6421_REGBASE; 1152 1153 if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0, 1154 &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 1155 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1156 "couldn't map SATA regs\n"); 1157 } 1158 1159 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1160 "bus-master DMA support present"); 1161 via_vt6421_mapreg_dma(sc, pa); 1162 aprint_verbose("\n"); 1163 1164 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 1165 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 1166 if (sc->sc_dma_ok) { 1167 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 1168 sc->sc_wdcdev.irqack = pciide_irqack; 1169 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 1170 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 1171 } 1172 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 1173 1174 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 1175 sc->sc_wdcdev.sc_atac.atac_nchannels = 3; 1176 sc->sc_wdcdev.wdc_maxdrives = 2; 1177 1178 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 1179 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 1180 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 1181 1182 wdc_allocate_regs(&sc->sc_wdcdev); 1183 1184 if (pci_intr_map(pa, &intrhandle) != 0) { 1185 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1186 "couldn't map native-PCI interrupt\n"); 1187 return; 1188 } 1189 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 1190 sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc, 1191 intrhandle, IPL_BIO, pciide_pci_intr, sc, 1192 device_xname(sc->sc_wdcdev.sc_atac.atac_dev)); 1193 if (sc->sc_pci_ih == NULL) { 1194 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1195 "couldn't establish native-PCI interrupt"); 1196 if (intrstr != NULL) 1197 aprint_error(" at %s", intrstr); 1198 aprint_error("\n"); 1199 return; 1200 } 1201 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1202 "using %s for native-PCI interrupt\n", 1203 intrstr ? intrstr : "unknown interrupt"); 1204 1205 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1206 channel++) { 1207 cp = &sc->pciide_channels[channel]; 1208 if (via_vt6421_chansetup(sc, channel) == 0) 1209 continue; 1210 wdc_cp = &cp->ata_channel; 1211 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1212 1213 wdr->sata_iot = sc->sc_ba5_st; 1214 wdr->sata_baseioh = sc->sc_ba5_sh; 1215 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1216 (wdc_cp->ch_channel << 6) + 0x0, 4, 1217 &wdr->sata_status) != 0) { 1218 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1219 "couldn't map channel %d sata_status regs\n", 1220 wdc_cp->ch_channel); 1221 continue; 1222 } 1223 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1224 (wdc_cp->ch_channel << 6) + 0x4, 4, 1225 &wdr->sata_error) != 0) { 1226 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1227 "couldn't map channel %d sata_error regs\n", 1228 wdc_cp->ch_channel); 1229 continue; 1230 } 1231 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1232 (wdc_cp->ch_channel << 6) + 0x8, 4, 1233 &wdr->sata_control) != 0) { 1234 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1235 "couldn't map channel %d sata_control regs\n", 1236 wdc_cp->ch_channel); 1237 continue; 1238 } 1239 1240 if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel), 1241 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1242 NULL, &wdr->cmd_ios) != 0) { 1243 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1244 "couldn't map %s channel regs\n", cp->name); 1245 } 1246 wdr->ctl_iot = wdr->cmd_iot; 1247 for (i = 0; i < WDC_NREG; i++) { 1248 if (bus_space_subregion(wdr->cmd_iot, 1249 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1250 &wdr->cmd_iohs[i]) != 0) { 1251 aprint_error_dev( 1252 sc->sc_wdcdev.sc_atac.atac_dev, 1253 "couldn't subregion %s " 1254 "channel cmd regs\n", cp->name); 1255 return; 1256 } 1257 } 1258 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1259 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1260 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1261 "couldn't map channel %d ctl regs\n", channel); 1262 return; 1263 } 1264 wdc_init_shadow_regs(wdr); 1265 wdr->data32iot = wdr->cmd_iot; 1266 wdr->data32ioh = wdr->cmd_iohs[wd_data]; 1267 wdcattach(wdc_cp); 1268 } 1269 } 1270
Indexes created Wed Oct 22 13:09:56 GMT 2025