viaide.c revision 1.97
1 /* $NetBSD: viaide.c,v 1.97 2025/04/20 09:44:40 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.97 2025/04/20 09:44:40 andvar Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/pci/pciide_apollo_reg.h> 39 40 static int via_pcib_match(const struct pci_attach_args *); 41 static void via_chip_map(struct pciide_softc *, 42 const struct pci_attach_args *); 43 static void via_mapchan(const struct pci_attach_args *, 44 struct pciide_channel *, 45 pcireg_t, int (*)(void *)); 46 static void via_mapregs_compat_native(const struct pci_attach_args *, 47 struct pciide_channel *); 48 static int via_sata_chip_map_common(struct pciide_softc *, 49 const struct pci_attach_args *); 50 static void via_sata_chip_map(struct pciide_softc *, 51 const struct pci_attach_args *, int); 52 static void via_sata_chip_map_6(struct pciide_softc *, 53 const struct pci_attach_args *); 54 static void via_sata_chip_map_7(struct pciide_softc *, 55 const struct pci_attach_args *); 56 static void via_sata_chip_map_new(struct pciide_softc *, 57 const struct pci_attach_args *); 58 static void via_setup_channel(struct ata_channel *); 59 60 static int viaide_match(device_t, cfdata_t, void *); 61 static void viaide_attach(device_t, device_t, void *); 62 static const struct pciide_product_desc * 63 viaide_lookup(pcireg_t); 64 static bool viaide_suspend(device_t, const pmf_qual_t *); 65 static bool viaide_resume(device_t, const pmf_qual_t *); 66 67 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 68 viaide_match, viaide_attach, pciide_detach, NULL); 69 70 static const struct pciide_product_desc pciide_amd_products[] = { 71 { PCI_PRODUCT_AMD_PBC756_IDE, 72 0, 73 "AMD AMD756 IDE Controller", 74 via_chip_map 75 }, 76 { PCI_PRODUCT_AMD_PBC766_IDE, 77 0, 78 "AMD AMD766 IDE Controller", 79 via_chip_map 80 }, 81 { PCI_PRODUCT_AMD_PBC768_IDE, 82 0, 83 "AMD AMD768 IDE Controller", 84 via_chip_map 85 }, 86 { PCI_PRODUCT_AMD_PBC8111_IDE, 87 0, 88 "AMD AMD8111 IDE Controller", 89 via_chip_map 90 }, 91 { PCI_PRODUCT_AMD_CS5536_IDE, 92 0, 93 "AMD CS5536 IDE Controller", 94 via_chip_map 95 }, 96 { 0, 97 0, 98 NULL, 99 NULL 100 } 101 }; 102 103 static const struct pciide_product_desc pciide_nvidia_products[] = { 104 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 105 0, 106 "NVIDIA nForce IDE Controller", 107 via_chip_map 108 }, 109 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 110 0, 111 "NVIDIA nForce2 IDE Controller", 112 via_chip_map 113 }, 114 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 115 0, 116 "NVIDIA nForce2 Ultra 400 IDE Controller", 117 via_chip_map 118 }, 119 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 120 0, 121 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 122 via_sata_chip_map_6 123 }, 124 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 125 0, 126 "NVIDIA nForce3 IDE Controller", 127 via_chip_map 128 }, 129 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 130 0, 131 "NVIDIA nForce3 250 IDE Controller", 132 via_chip_map 133 }, 134 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 135 0, 136 "NVIDIA nForce3 250 Serial ATA Controller", 137 via_sata_chip_map_6 138 }, 139 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 140 0, 141 "NVIDIA nForce3 250 Serial ATA Controller", 142 via_sata_chip_map_6 143 }, 144 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 145 0, 146 "NVIDIA nForce4 IDE Controller", 147 via_chip_map 148 }, 149 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 150 0, 151 "NVIDIA nForce4 Serial ATA Controller", 152 via_sata_chip_map_6 153 }, 154 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 155 0, 156 "NVIDIA nForce4 Serial ATA Controller", 157 via_sata_chip_map_6 158 }, 159 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 160 0, 161 "NVIDIA nForce430 IDE Controller", 162 via_chip_map 163 }, 164 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 165 0, 166 "NVIDIA nForce430 Serial ATA Controller", 167 via_sata_chip_map_6 168 }, 169 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 170 0, 171 "NVIDIA nForce430 Serial ATA Controller", 172 via_sata_chip_map_6 173 }, 174 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 175 0, 176 "NVIDIA MCP04 IDE Controller", 177 via_chip_map 178 }, 179 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 180 0, 181 "NVIDIA MCP04 Serial ATA Controller", 182 via_sata_chip_map_6 183 }, 184 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 185 0, 186 "NVIDIA MCP04 Serial ATA Controller", 187 via_sata_chip_map_6 188 }, 189 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 190 0, 191 "NVIDIA MCP55 IDE Controller", 192 via_chip_map 193 }, 194 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 195 0, 196 "NVIDIA MCP55 Serial ATA Controller", 197 via_sata_chip_map_6 198 }, 199 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 200 0, 201 "NVIDIA MCP55 Serial ATA Controller", 202 via_sata_chip_map_6 203 }, 204 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 205 0, 206 "NVIDIA MCP61 IDE Controller", 207 via_chip_map 208 }, 209 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 210 0, 211 "NVIDIA MCP65 IDE Controller", 212 via_chip_map 213 }, 214 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 215 0, 216 "NVIDIA MCP73 IDE Controller", 217 via_chip_map 218 }, 219 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 220 0, 221 "NVIDIA MCP77 IDE Controller", 222 via_chip_map 223 }, 224 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 225 0, 226 "NVIDIA MCP61 Serial ATA Controller", 227 via_sata_chip_map_6 228 }, 229 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 230 0, 231 "NVIDIA MCP61 Serial ATA Controller", 232 via_sata_chip_map_6 233 }, 234 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 235 0, 236 "NVIDIA MCP61 Serial ATA Controller", 237 via_sata_chip_map_6 238 }, 239 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 240 0, 241 "NVIDIA MCP65 Serial ATA Controller", 242 via_sata_chip_map_6 243 }, 244 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 245 0, 246 "NVIDIA MCP65 Serial ATA Controller", 247 via_sata_chip_map_6 248 }, 249 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 250 0, 251 "NVIDIA MCP65 Serial ATA Controller", 252 via_sata_chip_map_6 253 }, 254 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 255 0, 256 "NVIDIA MCP65 Serial ATA Controller", 257 via_sata_chip_map_6 258 }, 259 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 260 0, 261 "NVIDIA MCP67 IDE Controller", 262 via_chip_map, 263 }, 264 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 265 0, 266 "NVIDIA MCP67 Serial ATA Controller", 267 via_sata_chip_map_6, 268 }, 269 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 270 0, 271 "NVIDIA MCP67 Serial ATA Controller", 272 via_sata_chip_map_6, 273 }, 274 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 275 0, 276 "NVIDIA MCP67 Serial ATA Controller", 277 via_sata_chip_map_6, 278 }, 279 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 280 0, 281 "NVIDIA MCP67 Serial ATA Controller", 282 via_sata_chip_map_6, 283 }, 284 { 0, 285 0, 286 NULL, 287 NULL 288 } 289 }; 290 291 static const struct pciide_product_desc pciide_via_products[] = { 292 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 293 0, 294 NULL, 295 via_chip_map, 296 }, 297 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 298 0, 299 NULL, 300 via_chip_map, 301 }, 302 { PCI_PRODUCT_VIATECH_CX700_IDE, 303 0, 304 "VIA Technologies CX700(M2)/VX700/VX800 SATA/IDE RAID Controller", 305 via_chip_map, 306 }, 307 { PCI_PRODUCT_VIATECH_CX700M2_IDE, 308 0, 309 NULL, 310 via_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_VX900_IDE, 313 0, 314 "VIA Technologies VX900/VX11 SATA controller", 315 via_chip_map, 316 }, 317 { PCI_PRODUCT_VIATECH_VX900_RAID, 318 0, 319 "VIA Technologies VX900/VX11 SATA controller (RAID mode)", 320 via_chip_map, 321 }, 322 { PCI_PRODUCT_VIATECH_VT6410_RAID, 323 0, 324 "VIA Technologies VT6410 IDE controller", 325 via_chip_map, 326 }, 327 { PCI_PRODUCT_VIATECH_VT6415_IDE, 328 0, 329 "VIA Technologies VT6415/VT6330 IDE controller", 330 via_chip_map, 331 }, 332 { PCI_PRODUCT_VIATECH_VT6421_RAID, 333 0, 334 "VIA Technologies VT6421 Serial ATA RAID Controller", 335 via_sata_chip_map_new, 336 }, 337 { PCI_PRODUCT_VIATECH_VT8237_SATA, 338 0, 339 "VIA Technologies VT8237 SATA Controller", 340 via_sata_chip_map_7, 341 }, 342 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 343 0, 344 "VIA Technologies VT8237A SATA Controller", 345 via_sata_chip_map_7, 346 }, 347 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, 348 0, 349 "VIA Technologies VT8237A (5337) SATA Controller", 350 via_sata_chip_map_7, 351 }, 352 /* 353 * The 0x3349 PCI ID may be reused in all modes (IDE, RAID, AHCI). 354 * ahcisata(4) will attach if AHCI mode is selected in the BIOS. 355 * Newer CE revision southbridges use it only in RAID mode. 356 */ 357 { PCI_PRODUCT_VIATECH_VT8251_SATA, 358 0, 359 "VIA Technologies VT8251 SATA Controller", 360 via_chip_map, 361 }, 362 /* 363 * The 0x5287 PCI ID is used only in IDE mode for newer 364 * VT8251 southbridge (CE) revisions. 365 */ 366 { PCI_PRODUCT_VIATECH_VT8251_SATA_2, 367 0, 368 "VIA Technologies VT8251 (5287) SATA Controller", 369 via_chip_map, 370 }, 371 { PCI_PRODUCT_VIATECH_VT8237S_SATA, 372 0, 373 "VIA Technologies VT8237S SATA Controller", 374 via_sata_chip_map_7, 375 }, 376 { PCI_PRODUCT_VIATECH_VT8237S_SATA_RAID, 377 0, 378 "VIA Technologies VT8237S SATA Controller (RAID mode)", 379 via_sata_chip_map_7, 380 }, 381 { PCI_PRODUCT_VIATECH_VT8261_SATA, 382 0, 383 "VIA Technologies VT8261 SATA Controller", 384 via_chip_map, 385 }, 386 { PCI_PRODUCT_VIATECH_VT8261_RAID, 387 0, 388 "VIA Technologies VT8261 SATA Controller (RAID mode)", 389 via_sata_chip_map_7, 390 }, 391 { 0, 392 0, 393 NULL, 394 NULL 395 } 396 }; 397 398 static const struct pciide_product_desc * 399 viaide_lookup(pcireg_t id) 400 { 401 402 switch (PCI_VENDOR(id)) { 403 case PCI_VENDOR_VIATECH: 404 return (pciide_lookup_product(id, pciide_via_products)); 405 406 case PCI_VENDOR_AMD: 407 return (pciide_lookup_product(id, pciide_amd_products)); 408 409 case PCI_VENDOR_NVIDIA: 410 return (pciide_lookup_product(id, pciide_nvidia_products)); 411 } 412 return (NULL); 413 } 414 415 static int 416 viaide_match(device_t parent, cfdata_t match, void *aux) 417 { 418 const struct pci_attach_args *pa = aux; 419 420 if (viaide_lookup(pa->pa_id) != NULL) 421 return (2); 422 return (0); 423 } 424 425 static void 426 viaide_attach(device_t parent, device_t self, void *aux) 427 { 428 const struct pci_attach_args *pa = aux; 429 struct pciide_softc *sc = device_private(self); 430 const struct pciide_product_desc *pp; 431 432 sc->sc_wdcdev.sc_atac.atac_dev = self; 433 434 pp = viaide_lookup(pa->pa_id); 435 if (pp == NULL) 436 panic("viaide_attach"); 437 pciide_common_attach(sc, pa, pp); 438 439 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 440 aprint_error_dev(self, "couldn't establish power handler\n"); 441 } 442 443 static int 444 via_pcib_match(const struct pci_attach_args *pa) 445 { 446 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 447 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 448 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 449 return (1); 450 return 0; 451 } 452 453 static bool 454 viaide_suspend(device_t dv, const pmf_qual_t *qual) 455 { 456 struct pciide_softc *sc = device_private(dv); 457 458 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 459 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 460 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 461 /* This two are VIA-only, but should be ignored by other devices. */ 462 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 463 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 464 465 return true; 466 } 467 468 static bool 469 viaide_resume(device_t dv, const pmf_qual_t *qual) 470 { 471 struct pciide_softc *sc = device_private(dv); 472 473 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 474 sc->sc_pm_reg[0]); 475 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 476 sc->sc_pm_reg[1]); 477 /* This two are VIA-only, but should be ignored by other devices. */ 478 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 479 sc->sc_pm_reg[2]); 480 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 481 sc->sc_pm_reg[3]); 482 483 return true; 484 } 485 486 static void 487 via_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 488 { 489 struct pciide_channel *cp; 490 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 491 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 492 int channel; 493 u_int32_t ideconf; 494 int no_ideconf = 0; 495 int single_channel = 0; 496 pcireg_t pcib_id, pcib_class; 497 struct pci_attach_args pcib_pa; 498 499 if (pciide_chipen(sc, pa) == 0) 500 return; 501 502 switch (vendor) { 503 case PCI_VENDOR_VIATECH: 504 switch (PCI_PRODUCT(pa->pa_id)) { 505 case PCI_PRODUCT_VIATECH_VT6415_IDE: 506 /* VT6415 is a single channel IDE controller. */ 507 single_channel = 1; 508 /* FALLTHROUGH */ 509 case PCI_PRODUCT_VIATECH_VT6410_RAID: 510 /* 511 * The chip enable register of the VT6410/VT6415 512 * controllers may not be set by the hardware. 513 * Treat their channels as always enabled. 514 */ 515 no_ideconf = 1; 516 /* FALLTHROUGH */ 517 case PCI_PRODUCT_VIATECH_CX700_IDE: 518 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 519 break; 520 case PCI_PRODUCT_VIATECH_VT8251_SATA: 521 /* FALLTHROUGH */ 522 case PCI_PRODUCT_VIATECH_VT8251_SATA_2: 523 /* FALLTHROUGH */ 524 case PCI_PRODUCT_VIATECH_VT8261_SATA: 525 /* FALLTHROUGH */ 526 case PCI_PRODUCT_VIATECH_VX900_IDE: 527 /* FALLTHROUGH */ 528 case PCI_PRODUCT_VIATECH_VX900_RAID: 529 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 530 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 531 break; 532 default: 533 /* 534 * get a PCI tag for the ISA bridge. 535 */ 536 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 537 goto unknown; 538 pcib_id = pcib_pa.pa_id; 539 pcib_class = pcib_pa.pa_class; 540 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 541 "VIA Technologies "); 542 switch (PCI_PRODUCT(pcib_id)) { 543 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 544 aprint_normal("VT82C586 (Apollo VP) "); 545 if(PCI_REVISION(pcib_class) >= 0x02) { 546 aprint_normal("ATA33 controller\n"); 547 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 548 } else { 549 aprint_normal("controller\n"); 550 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 551 } 552 break; 553 case PCI_PRODUCT_VIATECH_VT82C596A: 554 aprint_normal("VT82C596A (Apollo Pro) "); 555 if (PCI_REVISION(pcib_class) >= 0x12) { 556 aprint_normal("ATA66 controller\n"); 557 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 558 } else { 559 aprint_normal("ATA33 controller\n"); 560 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 561 } 562 break; 563 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 564 aprint_normal("VT82C686A (Apollo KX133) "); 565 if (PCI_REVISION(pcib_class) >= 0x40) { 566 aprint_normal("ATA100 controller\n"); 567 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 568 } else { 569 aprint_normal("ATA66 controller\n"); 570 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 571 } 572 break; 573 case PCI_PRODUCT_VIATECH_VT8231: 574 aprint_normal("VT8231 ATA100 controller\n"); 575 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 576 break; 577 case PCI_PRODUCT_VIATECH_VT8233: 578 aprint_normal("VT8233 ATA100 controller\n"); 579 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 580 break; 581 case PCI_PRODUCT_VIATECH_VT8233A: 582 aprint_normal("VT8233A ATA133 controller\n"); 583 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 584 break; 585 case PCI_PRODUCT_VIATECH_VT8235: 586 aprint_normal("VT8235 ATA133 controller\n"); 587 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 588 break; 589 case PCI_PRODUCT_VIATECH_VT8237: 590 aprint_normal("VT8237 ATA133 controller\n"); 591 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 592 break; 593 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 594 aprint_normal("VT8237A ATA133 controller\n"); 595 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 596 break; 597 case PCI_PRODUCT_VIATECH_VT8237S_ISA: 598 aprint_normal("VT8237S ATA133 controller\n"); 599 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 600 break; 601 case PCI_PRODUCT_VIATECH_CX700: 602 aprint_normal("CX700 ATA133 controller\n"); 603 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 604 break; 605 case PCI_PRODUCT_VIATECH_VT8251: 606 aprint_normal("VT8251 ATA133 controller\n"); 607 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 608 break; 609 case PCI_PRODUCT_VIATECH_VT8261: 610 aprint_normal("VT8261 ATA133 controller\n"); 611 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 612 break; 613 case PCI_PRODUCT_VIATECH_VX800: 614 aprint_normal("VX800 ATA133 controller\n"); 615 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 616 break; 617 case PCI_PRODUCT_VIATECH_VX855: 618 aprint_normal("VX855 ATA133 controller\n"); 619 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 620 break; 621 default: 622 unknown: 623 aprint_normal("unknown VIA ATA controller\n"); 624 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 625 } 626 break; 627 } 628 sc->sc_apo_regbase = APO_VIA_REGBASE; 629 break; 630 case PCI_VENDOR_AMD: 631 switch (sc->sc_pp->ide_product) { 632 case PCI_PRODUCT_AMD_PBC8111_IDE: 633 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 634 break; 635 case PCI_PRODUCT_AMD_CS5536_IDE: 636 case PCI_PRODUCT_AMD_PBC766_IDE: 637 case PCI_PRODUCT_AMD_PBC768_IDE: 638 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 639 break; 640 default: 641 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 642 } 643 sc->sc_apo_regbase = APO_AMD_REGBASE; 644 break; 645 case PCI_VENDOR_NVIDIA: 646 switch (sc->sc_pp->ide_product) { 647 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 648 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 649 break; 650 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 651 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 652 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 653 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 654 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 655 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 656 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 657 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 658 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 659 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 660 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 661 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 662 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 663 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 664 break; 665 } 666 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 667 break; 668 default: 669 panic("via_chip_map: unknown vendor"); 670 } 671 672 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 673 "bus-master DMA support present"); 674 pciide_mapreg_dma(sc, pa); 675 aprint_verbose("\n"); 676 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 677 if (sc->sc_dma_ok) { 678 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 679 sc->sc_wdcdev.irqack = pciide_irqack; 680 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 681 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 682 } 683 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 684 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 685 if (sc->sc_wdcdev.sc_atac.atac_set_modes == NULL) 686 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 687 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 688 if (single_channel) 689 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 690 else 691 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 692 sc->sc_wdcdev.wdc_maxdrives = 2; 693 694 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 695 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 696 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 697 if (interface == 0) { 698 ATADEBUG_PRINT(("via_chip_map interface == 0\n"), 699 DEBUG_PROBE); 700 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 701 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 702 } 703 } 704 705 wdc_allocate_regs(&sc->sc_wdcdev); 706 707 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 708 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 709 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 710 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 711 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 712 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 713 DEBUG_PROBE); 714 715 if (no_ideconf) 716 ideconf = APO_IDECONF_ALWAYS_EN; 717 else 718 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 719 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 720 channel++) { 721 cp = &sc->pciide_channels[channel]; 722 if (pciide_chansetup(sc, channel, interface) == 0) 723 continue; 724 725 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 726 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 727 "%s channel ignored (disabled)\n", cp->name); 728 cp->ata_channel.ch_flags |= ATACH_DISABLED; 729 continue; 730 } 731 via_mapchan(pa, cp, interface, pciide_pci_intr); 732 } 733 } 734 735 static void 736 via_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp, 737 pcireg_t interface, int (*pci_intr)(void *)) 738 { 739 struct ata_channel *wdc_cp; 740 struct pciide_softc *sc; 741 prop_bool_t compat_nat_enable; 742 743 wdc_cp = &cp->ata_channel; 744 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 745 compat_nat_enable = prop_dictionary_get( 746 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 747 "use-compat-native-irq"); 748 749 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 750 /* native mode with irq 14/15 requested? */ 751 if (compat_nat_enable != NULL && 752 prop_bool_true(compat_nat_enable)) 753 via_mapregs_compat_native(pa, cp); 754 else 755 pciide_mapregs_native(pa, cp, pci_intr); 756 } else { 757 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 758 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 759 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 760 } 761 wdcattach(wdc_cp); 762 } 763 764 /* 765 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 766 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 767 * programmed to use a single native PCI irq alone. So we install an interrupt 768 * handler for each channel, as in compatibility mode. 769 */ 770 static void 771 via_mapregs_compat_native(const struct pci_attach_args *pa, 772 struct pciide_channel *cp) 773 { 774 struct ata_channel *wdc_cp; 775 struct pciide_softc *sc; 776 777 wdc_cp = &cp->ata_channel; 778 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 779 780 /* XXX prevent pciide_mapregs_native from installing a handler */ 781 if (sc->sc_pci_ih == NULL) 782 sc->sc_pci_ih = (void *)~0; 783 pciide_mapregs_native(pa, cp, NULL); 784 785 /* interrupts are fixed to 14/15, as in compatibility mode */ 786 cp->compat = 1; 787 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 788 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 789 cp->ih = pciide_machdep_compat_intr_establish( 790 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 791 pciide_compat_intr, cp); 792 if (cp->ih == NULL) { 793 #endif 794 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 795 "no compatibility interrupt for " 796 "use by %s channel\n", cp->name); 797 wdc_cp->ch_flags |= ATACH_DISABLED; 798 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 799 } 800 sc->sc_pci_ih = cp->ih; /* XXX */ 801 #endif 802 } 803 } 804 805 static void 806 via_setup_channel(struct ata_channel *chp) 807 { 808 u_int32_t udmatim_reg, datatim_reg; 809 u_int8_t idedma_ctl; 810 int mode, drive, s; 811 struct ata_drive_datas *drvp; 812 struct atac_softc *atac = chp->ch_atac; 813 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 814 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 815 #ifndef PCIIDE_AMD756_ENABLEDMA 816 int rev = PCI_REVISION( 817 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 818 #endif 819 820 idedma_ctl = 0; 821 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 822 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 823 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 824 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 825 826 /* setup DMA if needed */ 827 pciide_channel_dma_setup(cp); 828 829 for (drive = 0; drive < 2; drive++) { 830 drvp = &chp->ch_drive[drive]; 831 /* If no drive, skip */ 832 if (drvp->drive_type == ATA_DRIVET_NONE) 833 continue; 834 /* add timing values, setup DMA if needed */ 835 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 836 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0)) { 837 mode = drvp->PIO_mode; 838 goto pio; 839 } 840 if ((atac->atac_cap & ATAC_CAP_UDMA) && 841 (drvp->drive_flags & ATA_DRIVE_UDMA)) { 842 /* use Ultra/DMA */ 843 s = splbio(); 844 drvp->drive_flags &= ~ATA_DRIVE_DMA; 845 splx(s); 846 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 847 APO_UDMA_EN_MTH(chp->ch_channel, drive); 848 switch (PCI_VENDOR(sc->sc_pci_id)) { 849 case PCI_VENDOR_VIATECH: 850 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 851 /* 8233a */ 852 udmatim_reg |= APO_UDMA_TIME( 853 chp->ch_channel, 854 drive, 855 via_udma133_tim[drvp->UDMA_mode]); 856 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 857 /* 686b */ 858 udmatim_reg |= APO_UDMA_TIME( 859 chp->ch_channel, 860 drive, 861 via_udma100_tim[drvp->UDMA_mode]); 862 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 863 /* 596b or 686a */ 864 udmatim_reg |= APO_UDMA_CLK66( 865 chp->ch_channel); 866 udmatim_reg |= APO_UDMA_TIME( 867 chp->ch_channel, 868 drive, 869 via_udma66_tim[drvp->UDMA_mode]); 870 } else { 871 /* 596a or 586b */ 872 udmatim_reg |= APO_UDMA_TIME( 873 chp->ch_channel, 874 drive, 875 via_udma33_tim[drvp->UDMA_mode]); 876 } 877 break; 878 case PCI_VENDOR_AMD: 879 case PCI_VENDOR_NVIDIA: 880 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 881 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 882 break; 883 } 884 /* can use PIO timings, MW DMA unused */ 885 mode = drvp->PIO_mode; 886 } else { 887 /* use Multiword DMA, but only if revision is OK */ 888 s = splbio(); 889 drvp->drive_flags &= ~ATA_DRIVE_UDMA; 890 splx(s); 891 #ifndef PCIIDE_AMD756_ENABLEDMA 892 /* 893 * The workaround doesn't seem to be necessary 894 * with all drives, so it can be disabled by 895 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 896 * triggered. 897 */ 898 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 899 sc->sc_pp->ide_product == 900 PCI_PRODUCT_AMD_PBC756_IDE && 901 AMD756_CHIPREV_DISABLEDMA(rev)) { 902 aprint_normal( 903 "%s:%d:%d: multi-word DMA disabled due " 904 "to chip revision\n", 905 device_xname( 906 sc->sc_wdcdev.sc_atac.atac_dev), 907 chp->ch_channel, drive); 908 mode = drvp->PIO_mode; 909 s = splbio(); 910 drvp->drive_flags &= ~ATA_DRIVE_DMA; 911 splx(s); 912 goto pio; 913 } 914 #endif 915 /* mode = min(pio, dma+2) */ 916 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 917 mode = drvp->PIO_mode; 918 else 919 mode = drvp->DMA_mode + 2; 920 } 921 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 922 923 pio: /* setup PIO mode */ 924 if (mode <= 2) { 925 drvp->DMA_mode = 0; 926 drvp->PIO_mode = 0; 927 mode = 0; 928 } else { 929 drvp->PIO_mode = mode; 930 drvp->DMA_mode = mode - 2; 931 } 932 datatim_reg |= 933 APO_DATATIM_PULSE(chp->ch_channel, drive, 934 apollo_pio_set[mode]) | 935 APO_DATATIM_RECOV(chp->ch_channel, drive, 936 apollo_pio_rec[mode]); 937 } 938 if (idedma_ctl != 0) { 939 /* Add software bits in status register */ 940 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 941 idedma_ctl); 942 } 943 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 944 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 945 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 946 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 947 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 948 } 949 950 static int 951 via_sata_chip_map_common(struct pciide_softc *sc, 952 const struct pci_attach_args *cpa) 953 { 954 pcireg_t csr; 955 int maptype, ret; 956 struct pci_attach_args pac, *pa = &pac; 957 958 pac = *cpa; 959 960 if (pciide_chipen(sc, pa) == 0) 961 return 0; 962 963 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 964 "bus-master DMA support present"); 965 pciide_mapreg_dma(sc, pa); 966 aprint_verbose("\n"); 967 968 if (sc->sc_dma_ok) { 969 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 970 sc->sc_wdcdev.irqack = pciide_irqack; 971 } 972 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 973 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 974 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 975 976 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 977 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 978 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 979 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 980 sc->sc_wdcdev.wdc_maxdrives = 2; 981 982 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 983 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 984 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 985 986 wdc_allocate_regs(&sc->sc_wdcdev); 987 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 988 PCI_MAPREG_START + 0x14); 989 switch(maptype) { 990 case PCI_MAPREG_TYPE_IO: 991 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 992 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 993 NULL, &sc->sc_ba5_ss); 994 break; 995 case PCI_MAPREG_MEM_TYPE_32BIT: 996 /* 997 * Enable memory-space access if it isn't already there. 998 */ 999 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, 1000 PCI_COMMAND_STATUS_REG); 1001 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 && 1002 (pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) { 1003 1004 pci_conf_write(pa->pa_pc, pa->pa_tag, 1005 PCI_COMMAND_STATUS_REG, 1006 csr | PCI_COMMAND_MEM_ENABLE); 1007 } 1008 1009 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 1010 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1011 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 1012 NULL, &sc->sc_ba5_ss); 1013 break; 1014 default: 1015 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1016 "couldn't map sata regs, unsupported maptype (0x%x)\n", 1017 maptype); 1018 return 0; 1019 } 1020 if (ret != 0) { 1021 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1022 "couldn't map sata regs\n"); 1023 return 0; 1024 } 1025 return 1; 1026 } 1027 1028 static void 1029 via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa, 1030 int satareg_shift) 1031 { 1032 struct pciide_channel *cp; 1033 struct ata_channel *wdc_cp; 1034 struct wdc_regs *wdr; 1035 pcireg_t interface; 1036 int channel; 1037 1038 interface = PCI_INTERFACE(pa->pa_class); 1039 1040 if (via_sata_chip_map_common(sc, pa) == 0) 1041 return; 1042 1043 if (interface == 0) { 1044 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 1045 DEBUG_PROBE); 1046 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 1047 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 1048 } 1049 1050 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 1051 sc->sc_wdcdev.wdc_maxdrives = 1; 1052 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1053 channel++) { 1054 cp = &sc->pciide_channels[channel]; 1055 if (pciide_chansetup(sc, channel, interface) == 0) 1056 continue; 1057 wdc_cp = &cp->ata_channel; 1058 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1059 wdr->sata_iot = sc->sc_ba5_st; 1060 wdr->sata_baseioh = sc->sc_ba5_sh; 1061 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1062 (wdc_cp->ch_channel << satareg_shift) + 0x0, 4, 1063 &wdr->sata_status) != 0) { 1064 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1065 "couldn't map channel %d sata_status regs\n", 1066 wdc_cp->ch_channel); 1067 continue; 1068 } 1069 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1070 (wdc_cp->ch_channel << satareg_shift) + 0x4, 4, 1071 &wdr->sata_error) != 0) { 1072 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1073 "couldn't map channel %d sata_error regs\n", 1074 wdc_cp->ch_channel); 1075 continue; 1076 } 1077 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1078 (wdc_cp->ch_channel << satareg_shift) + 0x8, 4, 1079 &wdr->sata_control) != 0) { 1080 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1081 "couldn't map channel %d sata_control regs\n", 1082 wdc_cp->ch_channel); 1083 continue; 1084 } 1085 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 1086 } 1087 } 1088 1089 static void 1090 via_sata_chip_map_6(struct pciide_softc *sc, const struct pci_attach_args *pa) 1091 { 1092 via_sata_chip_map(sc, pa, 6); 1093 } 1094 1095 static void 1096 via_sata_chip_map_7(struct pciide_softc *sc, const struct pci_attach_args *pa) 1097 { 1098 via_sata_chip_map(sc, pa, 7); 1099 } 1100 1101 static void 1102 via_vt6421_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 1103 { 1104 struct pciide_channel *pc; 1105 int chan, reg; 1106 bus_size_t size; 1107 1108 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 1109 PCI_MAPREG_TYPE_IO, 0, &sc->sc_dma_iot, &sc->sc_dma_ioh, 1110 NULL, &sc->sc_dma_ios) == 0); 1111 sc->sc_dmat = pa->pa_dmat; 1112 if (sc->sc_dma_ok == 0) { 1113 aprint_verbose(", but unused (couldn't map registers)"); 1114 } else { 1115 sc->sc_wdcdev.dma_arg = sc; 1116 sc->sc_wdcdev.dma_init = pciide_dma_init; 1117 sc->sc_wdcdev.dma_start = pciide_dma_start; 1118 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 1119 } 1120 1121 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 1122 PCIIDE_OPTIONS_NODMA) { 1123 aprint_verbose( 1124 ", but unused (forced off by config file)"); 1125 sc->sc_dma_ok = 0; 1126 } 1127 1128 if (sc->sc_dma_ok == 0) 1129 return; 1130 1131 for (chan = 0; chan < 4; chan++) { 1132 pc = &sc->pciide_channels[chan]; 1133 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 1134 size = 4; 1135 if (size > (IDEDMA_SCH_OFFSET - reg)) 1136 size = IDEDMA_SCH_OFFSET - reg; 1137 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 1138 IDEDMA_SCH_OFFSET * chan + reg, size, 1139 &pc->dma_iohs[reg]) != 0) { 1140 sc->sc_dma_ok = 0; 1141 aprint_verbose(", but can't subregion offset " 1142 "%d size %lu", 1143 reg, (u_long)size); 1144 return; 1145 } 1146 } 1147 } 1148 } 1149 1150 static int 1151 via_vt6421_chansetup(struct pciide_softc *sc, int channel) 1152 { 1153 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1154 1155 sc->wdc_chanarray[channel] = &cp->ata_channel; 1156 1157 cp->ata_channel.ch_channel = channel; 1158 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 1159 1160 return 1; 1161 } 1162 1163 static void 1164 via_sata_chip_map_new(struct pciide_softc *sc, 1165 const struct pci_attach_args *pa) 1166 { 1167 struct pciide_channel *cp; 1168 struct ata_channel *wdc_cp; 1169 struct wdc_regs *wdr; 1170 int channel; 1171 pci_intr_handle_t intrhandle; 1172 const char *intrstr; 1173 int i; 1174 char intrbuf[PCI_INTRSTR_LEN]; 1175 1176 if (pciide_chipen(sc, pa) == 0) 1177 return; 1178 1179 sc->sc_apo_regbase = APO_VIA_VT6421_REGBASE; 1180 1181 if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0, 1182 &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 1183 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1184 "couldn't map SATA regs\n"); 1185 } 1186 1187 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1188 "bus-master DMA support present"); 1189 via_vt6421_mapreg_dma(sc, pa); 1190 aprint_verbose("\n"); 1191 1192 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 1193 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 1194 if (sc->sc_dma_ok) { 1195 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 1196 sc->sc_wdcdev.irqack = pciide_irqack; 1197 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 1198 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 1199 } 1200 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 1201 1202 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 1203 sc->sc_wdcdev.sc_atac.atac_nchannels = 3; 1204 sc->sc_wdcdev.wdc_maxdrives = 2; 1205 1206 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 1207 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 1208 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 1209 1210 wdc_allocate_regs(&sc->sc_wdcdev); 1211 1212 if (pci_intr_map(pa, &intrhandle) != 0) { 1213 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1214 "couldn't map native-PCI interrupt\n"); 1215 return; 1216 } 1217 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 1218 sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc, 1219 intrhandle, IPL_BIO, pciide_pci_intr, sc, 1220 device_xname(sc->sc_wdcdev.sc_atac.atac_dev)); 1221 if (sc->sc_pci_ih == NULL) { 1222 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1223 "couldn't establish native-PCI interrupt"); 1224 if (intrstr != NULL) 1225 aprint_error(" at %s", intrstr); 1226 aprint_error("\n"); 1227 return; 1228 } 1229 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1230 "using %s for native-PCI interrupt\n", 1231 intrstr ? intrstr : "unknown interrupt"); 1232 1233 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1234 channel++) { 1235 cp = &sc->pciide_channels[channel]; 1236 if (via_vt6421_chansetup(sc, channel) == 0) 1237 continue; 1238 wdc_cp = &cp->ata_channel; 1239 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1240 1241 wdr->sata_iot = sc->sc_ba5_st; 1242 wdr->sata_baseioh = sc->sc_ba5_sh; 1243 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1244 (wdc_cp->ch_channel << 6) + 0x0, 4, 1245 &wdr->sata_status) != 0) { 1246 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1247 "couldn't map channel %d sata_status regs\n", 1248 wdc_cp->ch_channel); 1249 continue; 1250 } 1251 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1252 (wdc_cp->ch_channel << 6) + 0x4, 4, 1253 &wdr->sata_error) != 0) { 1254 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1255 "couldn't map channel %d sata_error regs\n", 1256 wdc_cp->ch_channel); 1257 continue; 1258 } 1259 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1260 (wdc_cp->ch_channel << 6) + 0x8, 4, 1261 &wdr->sata_control) != 0) { 1262 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1263 "couldn't map channel %d sata_control regs\n", 1264 wdc_cp->ch_channel); 1265 continue; 1266 } 1267 1268 if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel), 1269 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1270 NULL, &wdr->cmd_ios) != 0) { 1271 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1272 "couldn't map %s channel regs\n", cp->name); 1273 } 1274 wdr->ctl_iot = wdr->cmd_iot; 1275 for (i = 0; i < WDC_NREG; i++) { 1276 if (bus_space_subregion(wdr->cmd_iot, 1277 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1278 &wdr->cmd_iohs[i]) != 0) { 1279 aprint_error_dev( 1280 sc->sc_wdcdev.sc_atac.atac_dev, 1281 "couldn't subregion %s " 1282 "channel cmd regs\n", cp->name); 1283 return; 1284 } 1285 } 1286 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1287 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1288 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1289 "couldn't map channel %d ctl regs\n", channel); 1290 return; 1291 } 1292 wdc_init_shadow_regs(wdr); 1293 wdr->data32iot = wdr->cmd_iot; 1294 wdr->data32ioh = wdr->cmd_iohs[wd_data]; 1295 wdcattach(wdc_cp); 1296 } 1297 } 1298
Indexes created Sun Oct 19 02:09:48 GMT 2025