viaide.c revision 1.98 1 /* $NetBSD: viaide.c,v 1.98 2025/04/20 15:55:16 andvar Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.98 2025/04/20 15:55:16 andvar Exp $");
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33
34 #include <dev/pci/pcivar.h>
35 #include <dev/pci/pcidevs.h>
36 #include <dev/pci/pciidereg.h>
37 #include <dev/pci/pciidevar.h>
38 #include <dev/pci/pciide_apollo_reg.h>
39
40 static int via_pcib_match(const struct pci_attach_args *);
41 static void via_chip_map(struct pciide_softc *,
42 const struct pci_attach_args *);
43 static void via_mapchan(const struct pci_attach_args *,
44 struct pciide_channel *,
45 pcireg_t, int (*)(void *));
46 static void via_mapregs_compat_native(const struct pci_attach_args *,
47 struct pciide_channel *);
48 static int via_sata_chip_map_common(struct pciide_softc *,
49 const struct pci_attach_args *);
50 static void via_sata_chip_map(struct pciide_softc *,
51 const struct pci_attach_args *, int);
52 static void via_sata_chip_map_6(struct pciide_softc *,
53 const struct pci_attach_args *);
54 static void via_sata_chip_map_7(struct pciide_softc *,
55 const struct pci_attach_args *);
56 static void via_sata_chip_map_new(struct pciide_softc *,
57 const struct pci_attach_args *);
58 static void via_setup_channel(struct ata_channel *);
59
60 static int viaide_match(device_t, cfdata_t, void *);
61 static void viaide_attach(device_t, device_t, void *);
62 static const struct pciide_product_desc *
63 viaide_lookup(pcireg_t);
64 static bool viaide_suspend(device_t, const pmf_qual_t *);
65 static bool viaide_resume(device_t, const pmf_qual_t *);
66
67 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc),
68 viaide_match, viaide_attach, pciide_detach, NULL);
69
70 static const struct pciide_product_desc pciide_amd_products[] = {
71 { PCI_PRODUCT_AMD_PBC756_IDE,
72 0,
73 "AMD AMD756 IDE Controller",
74 via_chip_map
75 },
76 { PCI_PRODUCT_AMD_PBC766_IDE,
77 0,
78 "AMD AMD766 IDE Controller",
79 via_chip_map
80 },
81 { PCI_PRODUCT_AMD_PBC768_IDE,
82 0,
83 "AMD AMD768 IDE Controller",
84 via_chip_map
85 },
86 { PCI_PRODUCT_AMD_PBC8111_IDE,
87 0,
88 "AMD AMD8111 IDE Controller",
89 via_chip_map
90 },
91 { PCI_PRODUCT_AMD_CS5536_IDE,
92 0,
93 "AMD CS5536 IDE Controller",
94 via_chip_map
95 },
96 { 0,
97 0,
98 NULL,
99 NULL
100 }
101 };
102
103 static const struct pciide_product_desc pciide_nvidia_products[] = {
104 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100,
105 0,
106 "NVIDIA nForce IDE Controller",
107 via_chip_map
108 },
109 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133,
110 0,
111 "NVIDIA nForce2 IDE Controller",
112 via_chip_map
113 },
114 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133,
115 0,
116 "NVIDIA nForce2 Ultra 400 IDE Controller",
117 via_chip_map
118 },
119 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA,
120 0,
121 "NVIDIA nForce2 Ultra 400 Serial ATA Controller",
122 via_sata_chip_map_6
123 },
124 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133,
125 0,
126 "NVIDIA nForce3 IDE Controller",
127 via_chip_map
128 },
129 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133,
130 0,
131 "NVIDIA nForce3 250 IDE Controller",
132 via_chip_map
133 },
134 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA,
135 0,
136 "NVIDIA nForce3 250 Serial ATA Controller",
137 via_sata_chip_map_6
138 },
139 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2,
140 0,
141 "NVIDIA nForce3 250 Serial ATA Controller",
142 via_sata_chip_map_6
143 },
144 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133,
145 0,
146 "NVIDIA nForce4 IDE Controller",
147 via_chip_map
148 },
149 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1,
150 0,
151 "NVIDIA nForce4 Serial ATA Controller",
152 via_sata_chip_map_6
153 },
154 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2,
155 0,
156 "NVIDIA nForce4 Serial ATA Controller",
157 via_sata_chip_map_6
158 },
159 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133,
160 0,
161 "NVIDIA nForce430 IDE Controller",
162 via_chip_map
163 },
164 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1,
165 0,
166 "NVIDIA nForce430 Serial ATA Controller",
167 via_sata_chip_map_6
168 },
169 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2,
170 0,
171 "NVIDIA nForce430 Serial ATA Controller",
172 via_sata_chip_map_6
173 },
174 { PCI_PRODUCT_NVIDIA_MCP04_IDE,
175 0,
176 "NVIDIA MCP04 IDE Controller",
177 via_chip_map
178 },
179 { PCI_PRODUCT_NVIDIA_MCP04_SATA,
180 0,
181 "NVIDIA MCP04 Serial ATA Controller",
182 via_sata_chip_map_6
183 },
184 { PCI_PRODUCT_NVIDIA_MCP04_SATA2,
185 0,
186 "NVIDIA MCP04 Serial ATA Controller",
187 via_sata_chip_map_6
188 },
189 { PCI_PRODUCT_NVIDIA_MCP55_IDE,
190 0,
191 "NVIDIA MCP55 IDE Controller",
192 via_chip_map
193 },
194 { PCI_PRODUCT_NVIDIA_MCP55_SATA,
195 0,
196 "NVIDIA MCP55 Serial ATA Controller",
197 via_sata_chip_map_6
198 },
199 { PCI_PRODUCT_NVIDIA_MCP55_SATA2,
200 0,
201 "NVIDIA MCP55 Serial ATA Controller",
202 via_sata_chip_map_6
203 },
204 { PCI_PRODUCT_NVIDIA_MCP61_IDE,
205 0,
206 "NVIDIA MCP61 IDE Controller",
207 via_chip_map
208 },
209 { PCI_PRODUCT_NVIDIA_MCP65_IDE,
210 0,
211 "NVIDIA MCP65 IDE Controller",
212 via_chip_map
213 },
214 { PCI_PRODUCT_NVIDIA_MCP73_IDE,
215 0,
216 "NVIDIA MCP73 IDE Controller",
217 via_chip_map
218 },
219 { PCI_PRODUCT_NVIDIA_MCP77_IDE,
220 0,
221 "NVIDIA MCP77 IDE Controller",
222 via_chip_map
223 },
224 { PCI_PRODUCT_NVIDIA_MCP61_SATA,
225 0,
226 "NVIDIA MCP61 Serial ATA Controller",
227 via_sata_chip_map_6
228 },
229 { PCI_PRODUCT_NVIDIA_MCP61_SATA2,
230 0,
231 "NVIDIA MCP61 Serial ATA Controller",
232 via_sata_chip_map_6
233 },
234 { PCI_PRODUCT_NVIDIA_MCP61_SATA3,
235 0,
236 "NVIDIA MCP61 Serial ATA Controller",
237 via_sata_chip_map_6
238 },
239 { PCI_PRODUCT_NVIDIA_MCP65_SATA,
240 0,
241 "NVIDIA MCP65 Serial ATA Controller",
242 via_sata_chip_map_6
243 },
244 { PCI_PRODUCT_NVIDIA_MCP65_SATA2,
245 0,
246 "NVIDIA MCP65 Serial ATA Controller",
247 via_sata_chip_map_6
248 },
249 { PCI_PRODUCT_NVIDIA_MCP65_SATA3,
250 0,
251 "NVIDIA MCP65 Serial ATA Controller",
252 via_sata_chip_map_6
253 },
254 { PCI_PRODUCT_NVIDIA_MCP65_SATA4,
255 0,
256 "NVIDIA MCP65 Serial ATA Controller",
257 via_sata_chip_map_6
258 },
259 { PCI_PRODUCT_NVIDIA_MCP67_IDE,
260 0,
261 "NVIDIA MCP67 IDE Controller",
262 via_chip_map,
263 },
264 { PCI_PRODUCT_NVIDIA_MCP67_SATA,
265 0,
266 "NVIDIA MCP67 Serial ATA Controller",
267 via_sata_chip_map_6,
268 },
269 { PCI_PRODUCT_NVIDIA_MCP67_SATA2,
270 0,
271 "NVIDIA MCP67 Serial ATA Controller",
272 via_sata_chip_map_6,
273 },
274 { PCI_PRODUCT_NVIDIA_MCP67_SATA3,
275 0,
276 "NVIDIA MCP67 Serial ATA Controller",
277 via_sata_chip_map_6,
278 },
279 { PCI_PRODUCT_NVIDIA_MCP67_SATA4,
280 0,
281 "NVIDIA MCP67 Serial ATA Controller",
282 via_sata_chip_map_6,
283 },
284 { 0,
285 0,
286 NULL,
287 NULL
288 }
289 };
290
291 static const struct pciide_product_desc pciide_via_products[] = {
292 { PCI_PRODUCT_VIATECH_VT82C586_IDE,
293 0,
294 NULL,
295 via_chip_map,
296 },
297 { PCI_PRODUCT_VIATECH_VT82C586A_IDE,
298 0,
299 NULL,
300 via_chip_map,
301 },
302 { PCI_PRODUCT_VIATECH_CX700_IDE,
303 0,
304 "VIA Technologies CX700(M2)/VX700/VX800 SATA/IDE RAID Controller",
305 via_chip_map,
306 },
307 { PCI_PRODUCT_VIATECH_CX700M2_IDE,
308 0,
309 NULL,
310 via_chip_map,
311 },
312 { PCI_PRODUCT_VIATECH_VX900_IDE,
313 0,
314 "VIA Technologies VX900/VX11 SATA controller",
315 via_chip_map,
316 },
317 { PCI_PRODUCT_VIATECH_VX900_RAID,
318 0,
319 "VIA Technologies VX900/VX11 SATA controller (RAID mode)",
320 via_chip_map,
321 },
322 { PCI_PRODUCT_VIATECH_VT6410_RAID,
323 0,
324 "VIA Technologies VT6410 IDE controller",
325 via_chip_map,
326 },
327 { PCI_PRODUCT_VIATECH_VT6415_IDE,
328 0,
329 "VIA Technologies VT6415/VT6330 IDE controller",
330 via_chip_map,
331 },
332 { PCI_PRODUCT_VIATECH_VT6421_RAID,
333 0,
334 "VIA Technologies VT6421 Serial ATA RAID Controller",
335 via_sata_chip_map_new,
336 },
337 { PCI_PRODUCT_VIATECH_VT8237_SATA,
338 0,
339 "VIA Technologies VT8237 SATA Controller",
340 via_sata_chip_map_7,
341 },
342 { PCI_PRODUCT_VIATECH_VT8237A_SATA,
343 0,
344 "VIA Technologies VT8237A SATA Controller",
345 via_sata_chip_map_7,
346 },
347 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2,
348 0,
349 "VIA Technologies VT8237A (5337) SATA Controller",
350 via_sata_chip_map_7,
351 },
352 /*
353 * The 0x3349 PCI ID may be reused in all modes (IDE, RAID, AHCI).
354 * ahcisata(4) will attach if AHCI mode is selected in the BIOS.
355 * Newer CE revision southbridges use it only in RAID mode.
356 */
357 { PCI_PRODUCT_VIATECH_VT8251_SATA,
358 0,
359 "VIA Technologies VT8251 SATA Controller",
360 via_chip_map,
361 },
362 /*
363 * The 0x5287 PCI ID is used only in IDE mode for newer
364 * VT8251 southbridge (CE) revisions.
365 */
366 { PCI_PRODUCT_VIATECH_VT8251_SATA_2,
367 0,
368 "VIA Technologies VT8251 (5287) SATA Controller",
369 via_chip_map,
370 },
371 { PCI_PRODUCT_VIATECH_VT8237S_SATA,
372 0,
373 "VIA Technologies VT8237S SATA Controller",
374 via_sata_chip_map_7,
375 },
376 { PCI_PRODUCT_VIATECH_VT8237S_SATA_RAID,
377 0,
378 "VIA Technologies VT8237S SATA Controller (RAID mode)",
379 via_sata_chip_map_7,
380 },
381 { PCI_PRODUCT_VIATECH_VT8261_SATA,
382 0,
383 "VIA Technologies VT8261 SATA Controller",
384 via_chip_map,
385 },
386 { PCI_PRODUCT_VIATECH_VT8261_RAID,
387 0,
388 "VIA Technologies VT8261 SATA Controller (RAID mode)",
389 via_sata_chip_map_7,
390 },
391 { 0,
392 0,
393 NULL,
394 NULL
395 }
396 };
397
398 static const struct pciide_product_desc *
399 viaide_lookup(pcireg_t id)
400 {
401
402 switch (PCI_VENDOR(id)) {
403 case PCI_VENDOR_VIATECH:
404 return (pciide_lookup_product(id, pciide_via_products));
405
406 case PCI_VENDOR_AMD:
407 return (pciide_lookup_product(id, pciide_amd_products));
408
409 case PCI_VENDOR_NVIDIA:
410 return (pciide_lookup_product(id, pciide_nvidia_products));
411 }
412 return (NULL);
413 }
414
415 static int
416 viaide_match(device_t parent, cfdata_t match, void *aux)
417 {
418 const struct pci_attach_args *pa = aux;
419
420 if (viaide_lookup(pa->pa_id) != NULL)
421 return (2);
422 return (0);
423 }
424
425 static void
426 viaide_attach(device_t parent, device_t self, void *aux)
427 {
428 const struct pci_attach_args *pa = aux;
429 struct pciide_softc *sc = device_private(self);
430 const struct pciide_product_desc *pp;
431
432 sc->sc_wdcdev.sc_atac.atac_dev = self;
433
434 pp = viaide_lookup(pa->pa_id);
435 if (pp == NULL)
436 panic("viaide_attach");
437 pciide_common_attach(sc, pa, pp);
438
439 if (!pmf_device_register(self, viaide_suspend, viaide_resume))
440 aprint_error_dev(self, "couldn't establish power handler\n");
441 }
442
443 static int
444 via_pcib_match(const struct pci_attach_args *pa)
445 {
446 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
447 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
448 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH)
449 return (1);
450 return 0;
451 }
452
453 static bool
454 viaide_suspend(device_t dv, const pmf_qual_t *qual)
455 {
456 struct pciide_softc *sc = device_private(dv);
457
458 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
459 /* APO_DATATIM(sc) includes APO_UDMA(sc) */
460 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
461 /* This two are VIA-only, but should be ignored by other devices. */
462 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc));
463 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc));
464
465 return true;
466 }
467
468 static bool
469 viaide_resume(device_t dv, const pmf_qual_t *qual)
470 {
471 struct pciide_softc *sc = device_private(dv);
472
473 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc),
474 sc->sc_pm_reg[0]);
475 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc),
476 sc->sc_pm_reg[1]);
477 /* This two are VIA-only, but should be ignored by other devices. */
478 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc),
479 sc->sc_pm_reg[2]);
480 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc),
481 sc->sc_pm_reg[3]);
482
483 return true;
484 }
485
486 static void
487 via_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
488 {
489 struct pciide_channel *cp;
490 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
491 pcireg_t vendor = PCI_VENDOR(pa->pa_id);
492 int channel;
493 u_int32_t ideconf;
494 int no_ideconf = 0;
495 int single_channel = 0;
496 pcireg_t pcib_id, pcib_class;
497 struct pci_attach_args pcib_pa;
498
499 if (pciide_chipen(sc, pa) == 0)
500 return;
501
502 switch (vendor) {
503 case PCI_VENDOR_VIATECH:
504 switch (PCI_PRODUCT(pa->pa_id)) {
505 case PCI_PRODUCT_VIATECH_VT6415_IDE:
506 /* VT6415 is a single channel IDE controller. */
507 single_channel = 1;
508 /* FALLTHROUGH */
509 case PCI_PRODUCT_VIATECH_VT6410_RAID:
510 /*
511 * The chip enable register of the VT6410/VT6415
512 * controllers may not be set by the hardware.
513 * Treat their channels as always enabled.
514 */
515 no_ideconf = 1;
516 /* FALLTHROUGH */
517 case PCI_PRODUCT_VIATECH_CX700_IDE:
518 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
519 break;
520 case PCI_PRODUCT_VIATECH_VT8251_SATA:
521 /* FALLTHROUGH */
522 case PCI_PRODUCT_VIATECH_VT8251_SATA_2:
523 /* FALLTHROUGH */
524 case PCI_PRODUCT_VIATECH_VT8261_SATA:
525 /* FALLTHROUGH */
526 case PCI_PRODUCT_VIATECH_VX900_IDE:
527 /* FALLTHROUGH */
528 case PCI_PRODUCT_VIATECH_VX900_RAID:
529 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
530 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
531 break;
532 default:
533 /*
534 * get a PCI tag for the ISA bridge.
535 */
536 if (pci_find_device(&pcib_pa, via_pcib_match) == 0)
537 goto unknown;
538 pcib_id = pcib_pa.pa_id;
539 pcib_class = pcib_pa.pa_class;
540 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
541 "VIA Technologies ");
542 switch (PCI_PRODUCT(pcib_id)) {
543 case PCI_PRODUCT_VIATECH_VT82C586_ISA:
544 aprint_normal("VT82C586 (Apollo VP) ");
545 if(PCI_REVISION(pcib_class) >= 0x02) {
546 aprint_normal("ATA33 controller\n");
547 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
548 } else {
549 aprint_normal("controller\n");
550 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
551 }
552 break;
553 case PCI_PRODUCT_VIATECH_VT82C596A:
554 aprint_normal("VT82C596A (Apollo Pro) ");
555 if (PCI_REVISION(pcib_class) >= 0x12) {
556 aprint_normal("ATA66 controller\n");
557 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
558 } else {
559 aprint_normal("ATA33 controller\n");
560 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
561 }
562 break;
563 case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
564 aprint_normal("VT82C686A (Apollo KX133) ");
565 if (PCI_REVISION(pcib_class) >= 0x40) {
566 aprint_normal("ATA100 controller\n");
567 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
568 } else {
569 aprint_normal("ATA66 controller\n");
570 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
571 }
572 break;
573 case PCI_PRODUCT_VIATECH_VT8231:
574 aprint_normal("VT8231 ATA100 controller\n");
575 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
576 break;
577 case PCI_PRODUCT_VIATECH_VT8233:
578 aprint_normal("VT8233 ATA100 controller\n");
579 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
580 break;
581 case PCI_PRODUCT_VIATECH_VT8233A:
582 aprint_normal("VT8233A ATA133 controller\n");
583 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
584 break;
585 case PCI_PRODUCT_VIATECH_VT8235:
586 aprint_normal("VT8235 ATA133 controller\n");
587 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
588 break;
589 case PCI_PRODUCT_VIATECH_VT8237:
590 aprint_normal("VT8237 ATA133 controller\n");
591 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
592 break;
593 case PCI_PRODUCT_VIATECH_VT8237A_ISA:
594 aprint_normal("VT8237A ATA133 controller\n");
595 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
596 break;
597 case PCI_PRODUCT_VIATECH_VT8237S_ISA:
598 aprint_normal("VT8237S ATA133 controller\n");
599 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
600 break;
601 case PCI_PRODUCT_VIATECH_CX700:
602 aprint_normal("CX700 ATA133 controller\n");
603 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
604 break;
605 case PCI_PRODUCT_VIATECH_VT8251:
606 aprint_normal("VT8251 ATA133 controller\n");
607 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
608 break;
609 case PCI_PRODUCT_VIATECH_VT8261:
610 aprint_normal("VT8261 ATA133 controller\n");
611 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
612 break;
613 case PCI_PRODUCT_VIATECH_VX800:
614 aprint_normal("VX800 ATA133 controller\n");
615 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
616 break;
617 case PCI_PRODUCT_VIATECH_VX855:
618 aprint_normal("VX855 ATA133 controller\n");
619 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
620 break;
621 default:
622 unknown:
623 aprint_normal("unknown VIA ATA controller\n");
624 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
625 }
626 break;
627 }
628 sc->sc_apo_regbase = APO_VIA_REGBASE;
629 break;
630 case PCI_VENDOR_AMD:
631 switch (sc->sc_pp->ide_product) {
632 case PCI_PRODUCT_AMD_PBC8111_IDE:
633 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
634 break;
635 case PCI_PRODUCT_AMD_CS5536_IDE:
636 case PCI_PRODUCT_AMD_PBC766_IDE:
637 case PCI_PRODUCT_AMD_PBC768_IDE:
638 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
639 break;
640 default:
641 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
642 }
643 sc->sc_apo_regbase = APO_AMD_REGBASE;
644 break;
645 case PCI_VENDOR_NVIDIA:
646 switch (sc->sc_pp->ide_product) {
647 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
648 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
649 break;
650 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
651 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133:
652 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
653 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133:
654 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133:
655 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133:
656 case PCI_PRODUCT_NVIDIA_MCP04_IDE:
657 case PCI_PRODUCT_NVIDIA_MCP55_IDE:
658 case PCI_PRODUCT_NVIDIA_MCP61_IDE:
659 case PCI_PRODUCT_NVIDIA_MCP65_IDE:
660 case PCI_PRODUCT_NVIDIA_MCP67_IDE:
661 case PCI_PRODUCT_NVIDIA_MCP73_IDE:
662 case PCI_PRODUCT_NVIDIA_MCP77_IDE:
663 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
664 break;
665 }
666 sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
667 break;
668 default:
669 panic("via_chip_map: unknown vendor");
670 }
671
672 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
673 "bus-master DMA support present");
674 pciide_mapreg_dma(sc, pa);
675 aprint_verbose("\n");
676 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
677 if (sc->sc_dma_ok) {
678 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
679 sc->sc_wdcdev.irqack = pciide_irqack;
680 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0)
681 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
682 }
683 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
684 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
685 if (sc->sc_wdcdev.sc_atac.atac_set_modes == NULL)
686 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel;
687 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
688 if (single_channel)
689 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
690 else
691 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
692 sc->sc_wdcdev.wdc_maxdrives = 2;
693
694 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
695 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) {
696 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
697 if (interface == 0) {
698 ATADEBUG_PRINT(("via_chip_map interface == 0\n"),
699 DEBUG_PROBE);
700 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
701 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
702 }
703 }
704
705 wdc_allocate_regs(&sc->sc_wdcdev);
706
707 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
708 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
709 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
710 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
711 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
712 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
713 DEBUG_PROBE);
714
715 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
716 if (ideconf == 0 && no_ideconf)
717 ideconf = APO_IDECONF_ALWAYS_EN;
718 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
719 channel++) {
720 cp = &sc->pciide_channels[channel];
721 if (pciide_chansetup(sc, channel, interface) == 0)
722 continue;
723
724 if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
725 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
726 "%s channel ignored (disabled)\n", cp->name);
727 cp->ata_channel.ch_flags |= ATACH_DISABLED;
728 continue;
729 }
730 via_mapchan(pa, cp, interface, pciide_pci_intr);
731 }
732 }
733
734 static void
735 via_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp,
736 pcireg_t interface, int (*pci_intr)(void *))
737 {
738 struct ata_channel *wdc_cp;
739 struct pciide_softc *sc;
740 prop_bool_t compat_nat_enable;
741
742 wdc_cp = &cp->ata_channel;
743 sc = CHAN_TO_PCIIDE(&cp->ata_channel);
744 compat_nat_enable = prop_dictionary_get(
745 device_properties(sc->sc_wdcdev.sc_atac.atac_dev),
746 "use-compat-native-irq");
747
748 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) {
749 /* native mode with irq 14/15 requested? */
750 if (compat_nat_enable != NULL &&
751 prop_bool_true(compat_nat_enable))
752 via_mapregs_compat_native(pa, cp);
753 else
754 pciide_mapregs_native(pa, cp, pci_intr);
755 } else {
756 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel);
757 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0)
758 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel);
759 }
760 wdcattach(wdc_cp);
761 }
762
763 /*
764 * At least under certain (mis)configurations (e.g. on the "Pegasos" board)
765 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be
766 * programmed to use a single native PCI irq alone. So we install an interrupt
767 * handler for each channel, as in compatibility mode.
768 */
769 static void
770 via_mapregs_compat_native(const struct pci_attach_args *pa,
771 struct pciide_channel *cp)
772 {
773 struct ata_channel *wdc_cp;
774 struct pciide_softc *sc;
775
776 wdc_cp = &cp->ata_channel;
777 sc = CHAN_TO_PCIIDE(&cp->ata_channel);
778
779 /* XXX prevent pciide_mapregs_native from installing a handler */
780 if (sc->sc_pci_ih == NULL)
781 sc->sc_pci_ih = (void *)~0;
782 pciide_mapregs_native(pa, cp, NULL);
783
784 /* interrupts are fixed to 14/15, as in compatibility mode */
785 cp->compat = 1;
786 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) {
787 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
788 cp->ih = pciide_machdep_compat_intr_establish(
789 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel,
790 pciide_compat_intr, cp);
791 if (cp->ih == NULL) {
792 #endif
793 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
794 "no compatibility interrupt for "
795 "use by %s channel\n", cp->name);
796 wdc_cp->ch_flags |= ATACH_DISABLED;
797 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
798 }
799 sc->sc_pci_ih = cp->ih; /* XXX */
800 #endif
801 }
802 }
803
804 static void
805 via_setup_channel(struct ata_channel *chp)
806 {
807 u_int32_t udmatim_reg, datatim_reg;
808 u_int8_t idedma_ctl;
809 int mode, drive, s;
810 struct ata_drive_datas *drvp;
811 struct atac_softc *atac = chp->ch_atac;
812 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
813 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
814 #ifndef PCIIDE_AMD756_ENABLEDMA
815 int rev = PCI_REVISION(
816 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
817 #endif
818
819 idedma_ctl = 0;
820 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
821 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc));
822 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
823 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
824
825 /* setup DMA if needed */
826 pciide_channel_dma_setup(cp);
827
828 for (drive = 0; drive < 2; drive++) {
829 drvp = &chp->ch_drive[drive];
830 /* If no drive, skip */
831 if (drvp->drive_type == ATA_DRIVET_NONE)
832 continue;
833 /* add timing values, setup DMA if needed */
834 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 &&
835 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0)) {
836 mode = drvp->PIO_mode;
837 goto pio;
838 }
839 if ((atac->atac_cap & ATAC_CAP_UDMA) &&
840 (drvp->drive_flags & ATA_DRIVE_UDMA)) {
841 /* use Ultra/DMA */
842 s = splbio();
843 drvp->drive_flags &= ~ATA_DRIVE_DMA;
844 splx(s);
845 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
846 APO_UDMA_EN_MTH(chp->ch_channel, drive);
847 switch (PCI_VENDOR(sc->sc_pci_id)) {
848 case PCI_VENDOR_VIATECH:
849 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) {
850 /* 8233a */
851 udmatim_reg |= APO_UDMA_TIME(
852 chp->ch_channel,
853 drive,
854 via_udma133_tim[drvp->UDMA_mode]);
855 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) {
856 /* 686b */
857 udmatim_reg |= APO_UDMA_TIME(
858 chp->ch_channel,
859 drive,
860 via_udma100_tim[drvp->UDMA_mode]);
861 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) {
862 /* 596b or 686a */
863 udmatim_reg |= APO_UDMA_CLK66(
864 chp->ch_channel);
865 udmatim_reg |= APO_UDMA_TIME(
866 chp->ch_channel,
867 drive,
868 via_udma66_tim[drvp->UDMA_mode]);
869 } else {
870 /* 596a or 586b */
871 udmatim_reg |= APO_UDMA_TIME(
872 chp->ch_channel,
873 drive,
874 via_udma33_tim[drvp->UDMA_mode]);
875 }
876 break;
877 case PCI_VENDOR_AMD:
878 case PCI_VENDOR_NVIDIA:
879 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel,
880 drive, amd7x6_udma_tim[drvp->UDMA_mode]);
881 break;
882 }
883 /* can use PIO timings, MW DMA unused */
884 mode = drvp->PIO_mode;
885 } else {
886 /* use Multiword DMA, but only if revision is OK */
887 s = splbio();
888 drvp->drive_flags &= ~ATA_DRIVE_UDMA;
889 splx(s);
890 #ifndef PCIIDE_AMD756_ENABLEDMA
891 /*
892 * The workaround doesn't seem to be necessary
893 * with all drives, so it can be disabled by
894 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
895 * triggered.
896 */
897 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD &&
898 sc->sc_pp->ide_product ==
899 PCI_PRODUCT_AMD_PBC756_IDE &&
900 AMD756_CHIPREV_DISABLEDMA(rev)) {
901 aprint_normal(
902 "%s:%d:%d: multi-word DMA disabled due "
903 "to chip revision\n",
904 device_xname(
905 sc->sc_wdcdev.sc_atac.atac_dev),
906 chp->ch_channel, drive);
907 mode = drvp->PIO_mode;
908 s = splbio();
909 drvp->drive_flags &= ~ATA_DRIVE_DMA;
910 splx(s);
911 goto pio;
912 }
913 #endif
914 /* mode = min(pio, dma+2) */
915 if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
916 mode = drvp->PIO_mode;
917 else
918 mode = drvp->DMA_mode + 2;
919 }
920 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
921
922 pio: /* setup PIO mode */
923 if (mode <= 2) {
924 drvp->DMA_mode = 0;
925 drvp->PIO_mode = 0;
926 mode = 0;
927 } else {
928 drvp->PIO_mode = mode;
929 drvp->DMA_mode = mode - 2;
930 }
931 datatim_reg |=
932 APO_DATATIM_PULSE(chp->ch_channel, drive,
933 apollo_pio_set[mode]) |
934 APO_DATATIM_RECOV(chp->ch_channel, drive,
935 apollo_pio_rec[mode]);
936 }
937 if (idedma_ctl != 0) {
938 /* Add software bits in status register */
939 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
940 idedma_ctl);
941 }
942 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg);
943 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg);
944 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
945 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
946 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE);
947 }
948
949 static int
950 via_sata_chip_map_common(struct pciide_softc *sc,
951 const struct pci_attach_args *cpa)
952 {
953 pcireg_t csr;
954 int maptype, ret;
955 struct pci_attach_args pac, *pa = &pac;
956
957 pac = *cpa;
958
959 if (pciide_chipen(sc, pa) == 0)
960 return 0;
961
962 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
963 "bus-master DMA support present");
964 pciide_mapreg_dma(sc, pa);
965 aprint_verbose("\n");
966
967 if (sc->sc_dma_ok) {
968 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
969 sc->sc_wdcdev.irqack = pciide_irqack;
970 }
971 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
972 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
973 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
974
975 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
976 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
977 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
978 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
979 sc->sc_wdcdev.wdc_maxdrives = 2;
980
981 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
982 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
983 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
984
985 wdc_allocate_regs(&sc->sc_wdcdev);
986 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
987 PCI_MAPREG_START + 0x14);
988 switch(maptype) {
989 case PCI_MAPREG_TYPE_IO:
990 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
991 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
992 NULL, &sc->sc_ba5_ss);
993 break;
994 case PCI_MAPREG_MEM_TYPE_32BIT:
995 /*
996 * Enable memory-space access if it isn't already there.
997 */
998 csr = pci_conf_read(pa->pa_pc, pa->pa_tag,
999 PCI_COMMAND_STATUS_REG);
1000 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 &&
1001 (pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) {
1002
1003 pci_conf_write(pa->pa_pc, pa->pa_tag,
1004 PCI_COMMAND_STATUS_REG,
1005 csr | PCI_COMMAND_MEM_ENABLE);
1006 }
1007
1008 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
1009 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
1010 0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
1011 NULL, &sc->sc_ba5_ss);
1012 break;
1013 default:
1014 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1015 "couldn't map sata regs, unsupported maptype (0x%x)\n",
1016 maptype);
1017 return 0;
1018 }
1019 if (ret != 0) {
1020 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1021 "couldn't map sata regs\n");
1022 return 0;
1023 }
1024 return 1;
1025 }
1026
1027 static void
1028 via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa,
1029 int satareg_shift)
1030 {
1031 struct pciide_channel *cp;
1032 struct ata_channel *wdc_cp;
1033 struct wdc_regs *wdr;
1034 pcireg_t interface;
1035 int channel;
1036
1037 interface = PCI_INTERFACE(pa->pa_class);
1038
1039 if (via_sata_chip_map_common(sc, pa) == 0)
1040 return;
1041
1042 if (interface == 0) {
1043 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
1044 DEBUG_PROBE);
1045 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
1046 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
1047 }
1048
1049 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
1050 sc->sc_wdcdev.wdc_maxdrives = 1;
1051 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
1052 channel++) {
1053 cp = &sc->pciide_channels[channel];
1054 if (pciide_chansetup(sc, channel, interface) == 0)
1055 continue;
1056 wdc_cp = &cp->ata_channel;
1057 wdr = CHAN_TO_WDC_REGS(wdc_cp);
1058 wdr->sata_iot = sc->sc_ba5_st;
1059 wdr->sata_baseioh = sc->sc_ba5_sh;
1060 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
1061 (wdc_cp->ch_channel << satareg_shift) + 0x0, 4,
1062 &wdr->sata_status) != 0) {
1063 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1064 "couldn't map channel %d sata_status regs\n",
1065 wdc_cp->ch_channel);
1066 continue;
1067 }
1068 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
1069 (wdc_cp->ch_channel << satareg_shift) + 0x4, 4,
1070 &wdr->sata_error) != 0) {
1071 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1072 "couldn't map channel %d sata_error regs\n",
1073 wdc_cp->ch_channel);
1074 continue;
1075 }
1076 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
1077 (wdc_cp->ch_channel << satareg_shift) + 0x8, 4,
1078 &wdr->sata_control) != 0) {
1079 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1080 "couldn't map channel %d sata_control regs\n",
1081 wdc_cp->ch_channel);
1082 continue;
1083 }
1084 pciide_mapchan(pa, cp, interface, pciide_pci_intr);
1085 }
1086 }
1087
1088 static void
1089 via_sata_chip_map_6(struct pciide_softc *sc, const struct pci_attach_args *pa)
1090 {
1091 via_sata_chip_map(sc, pa, 6);
1092 }
1093
1094 static void
1095 via_sata_chip_map_7(struct pciide_softc *sc, const struct pci_attach_args *pa)
1096 {
1097 via_sata_chip_map(sc, pa, 7);
1098 }
1099
1100 static void
1101 via_vt6421_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa)
1102 {
1103 struct pciide_channel *pc;
1104 int chan, reg;
1105 bus_size_t size;
1106
1107 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA,
1108 PCI_MAPREG_TYPE_IO, 0, &sc->sc_dma_iot, &sc->sc_dma_ioh,
1109 NULL, &sc->sc_dma_ios) == 0);
1110 sc->sc_dmat = pa->pa_dmat;
1111 if (sc->sc_dma_ok == 0) {
1112 aprint_verbose(", but unused (couldn't map registers)");
1113 } else {
1114 sc->sc_wdcdev.dma_arg = sc;
1115 sc->sc_wdcdev.dma_init = pciide_dma_init;
1116 sc->sc_wdcdev.dma_start = pciide_dma_start;
1117 sc->sc_wdcdev.dma_finish = pciide_dma_finish;
1118 }
1119
1120 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
1121 PCIIDE_OPTIONS_NODMA) {
1122 aprint_verbose(
1123 ", but unused (forced off by config file)");
1124 sc->sc_dma_ok = 0;
1125 }
1126
1127 if (sc->sc_dma_ok == 0)
1128 return;
1129
1130 for (chan = 0; chan < 4; chan++) {
1131 pc = &sc->pciide_channels[chan];
1132 for (reg = 0; reg < IDEDMA_NREGS; reg++) {
1133 size = 4;
1134 if (size > (IDEDMA_SCH_OFFSET - reg))
1135 size = IDEDMA_SCH_OFFSET - reg;
1136 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh,
1137 IDEDMA_SCH_OFFSET * chan + reg, size,
1138 &pc->dma_iohs[reg]) != 0) {
1139 sc->sc_dma_ok = 0;
1140 aprint_verbose(", but can't subregion offset "
1141 "%d size %lu",
1142 reg, (u_long)size);
1143 return;
1144 }
1145 }
1146 }
1147 }
1148
1149 static int
1150 via_vt6421_chansetup(struct pciide_softc *sc, int channel)
1151 {
1152 struct pciide_channel *cp = &sc->pciide_channels[channel];
1153
1154 sc->wdc_chanarray[channel] = &cp->ata_channel;
1155
1156 cp->ata_channel.ch_channel = channel;
1157 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
1158
1159 return 1;
1160 }
1161
1162 static void
1163 via_sata_chip_map_new(struct pciide_softc *sc,
1164 const struct pci_attach_args *pa)
1165 {
1166 struct pciide_channel *cp;
1167 struct ata_channel *wdc_cp;
1168 struct wdc_regs *wdr;
1169 int channel;
1170 pci_intr_handle_t intrhandle;
1171 const char *intrstr;
1172 int i;
1173 char intrbuf[PCI_INTRSTR_LEN];
1174
1175 if (pciide_chipen(sc, pa) == 0)
1176 return;
1177
1178 sc->sc_apo_regbase = APO_VIA_VT6421_REGBASE;
1179
1180 if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0,
1181 &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) {
1182 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1183 "couldn't map SATA regs\n");
1184 }
1185
1186 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1187 "bus-master DMA support present");
1188 via_vt6421_mapreg_dma(sc, pa);
1189 aprint_verbose("\n");
1190
1191 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
1192 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
1193 if (sc->sc_dma_ok) {
1194 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
1195 sc->sc_wdcdev.irqack = pciide_irqack;
1196 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
1197 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
1198 }
1199 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
1200
1201 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
1202 sc->sc_wdcdev.sc_atac.atac_nchannels = 3;
1203 sc->sc_wdcdev.wdc_maxdrives = 2;
1204
1205 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
1206 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
1207 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
1208
1209 wdc_allocate_regs(&sc->sc_wdcdev);
1210
1211 if (pci_intr_map(pa, &intrhandle) != 0) {
1212 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1213 "couldn't map native-PCI interrupt\n");
1214 return;
1215 }
1216 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf));
1217 sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc,
1218 intrhandle, IPL_BIO, pciide_pci_intr, sc,
1219 device_xname(sc->sc_wdcdev.sc_atac.atac_dev));
1220 if (sc->sc_pci_ih == NULL) {
1221 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1222 "couldn't establish native-PCI interrupt");
1223 if (intrstr != NULL)
1224 aprint_error(" at %s", intrstr);
1225 aprint_error("\n");
1226 return;
1227 }
1228 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1229 "using %s for native-PCI interrupt\n",
1230 intrstr ? intrstr : "unknown interrupt");
1231
1232 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
1233 channel++) {
1234 cp = &sc->pciide_channels[channel];
1235 if (via_vt6421_chansetup(sc, channel) == 0)
1236 continue;
1237 wdc_cp = &cp->ata_channel;
1238 wdr = CHAN_TO_WDC_REGS(wdc_cp);
1239
1240 wdr->sata_iot = sc->sc_ba5_st;
1241 wdr->sata_baseioh = sc->sc_ba5_sh;
1242 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
1243 (wdc_cp->ch_channel << 6) + 0x0, 4,
1244 &wdr->sata_status) != 0) {
1245 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1246 "couldn't map channel %d sata_status regs\n",
1247 wdc_cp->ch_channel);
1248 continue;
1249 }
1250 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
1251 (wdc_cp->ch_channel << 6) + 0x4, 4,
1252 &wdr->sata_error) != 0) {
1253 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1254 "couldn't map channel %d sata_error regs\n",
1255 wdc_cp->ch_channel);
1256 continue;
1257 }
1258 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
1259 (wdc_cp->ch_channel << 6) + 0x8, 4,
1260 &wdr->sata_control) != 0) {
1261 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1262 "couldn't map channel %d sata_control regs\n",
1263 wdc_cp->ch_channel);
1264 continue;
1265 }
1266
1267 if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel),
1268 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh,
1269 NULL, &wdr->cmd_ios) != 0) {
1270 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1271 "couldn't map %s channel regs\n", cp->name);
1272 }
1273 wdr->ctl_iot = wdr->cmd_iot;
1274 for (i = 0; i < WDC_NREG; i++) {
1275 if (bus_space_subregion(wdr->cmd_iot,
1276 wdr->cmd_baseioh, i, i == 0 ? 4 : 1,
1277 &wdr->cmd_iohs[i]) != 0) {
1278 aprint_error_dev(
1279 sc->sc_wdcdev.sc_atac.atac_dev,
1280 "couldn't subregion %s "
1281 "channel cmd regs\n", cp->name);
1282 return;
1283 }
1284 }
1285 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
1286 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) {
1287 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1288 "couldn't map channel %d ctl regs\n", channel);
1289 return;
1290 }
1291 wdc_init_shadow_regs(wdr);
1292 wdr->data32iot = wdr->cmd_iot;
1293 wdr->data32ioh = wdr->cmd_iohs[wd_data];
1294 wdcattach(wdc_cp);
1295 }
1296 }
1297