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      1 /* $NetBSD: if_eireg.h,v 1.4 2005/12/11 12:23:28 christos Exp $ */
      2 
      3 /*
      4  * 2000 Ben Harris
      5  *
      6  * This file is in the public domain.
      7  */
      8 
      9 /*
     10  * if_eireg.h - register definitions etc for the Acorn Ether1 card
     11  */
     12 
     13 #ifndef _IF_EIREG_H_
     14 #define _IF_EIREG_H_
     15 
     16 /*
     17  * The card has three address spaces.  The ROM is mapped into the
     18  * bottom 32 bytes of SYNC address space, and contains the
     19  * expansion card ID information and the Ethernet address.  There is a
     20  * pair of write-only registers at the start of the FAST address
     21  * space.  One of these performs miscellaneous control functions, and
     22  * the other acts as a page selector for the board memory.  The board
     23  * has 64k of RAM, and 4k pages of this can be mapped at offset 0x2000
     24  * in the FAST space by writing the page number to the page register.
     25  * The 82586 has access to the whole of this memory and (I believe)
     26  * sees it as the top 64k of its address space.
     27  */
     28 
     29 /* Registers in the board's control space */
     30 #define EI_PAGE		0
     31 #define EI_CONTROL	1
     32 #define EI_CTL_RST	0x01 /* Reset */
     33 #define EI_CTL_LB	0x02 /* Loop-back */
     34 #define EI_CTL_CA	0x04 /* Channel Attention */
     35 #define EI_CTL_CLI	0x08 /* Clear Interrupt */
     36 
     37 /* Offset of base of memory in bus_addr_t units */
     38 #define EI_MEMOFF	0x2000
     39 
     40 /*
     41  * All addresses within board RAM are in bytes of actual RAM.  RAM is
     42  * 16 bits wide, and can only be accessed by word transfers
     43  * (bus_space_xxx_2).
     44  */
     45 #define EI_MEMSIZE	0x10000
     46 #define EI_MEMBASE	(0x1000000 - EI_MEMSIZE)
     47 #define EI_PAGESIZE	0x1000
     48 #define EI_NPAGES	(EI_MEMSIZE / EI_PAGESIZE)
     49 #define ei_atop(a)	(((a) % EI_MEMSIZE) / EI_PAGESIZE)
     50 #define ei_atopo(a)	((a) % EI_PAGESIZE)
     51 
     52 #define EI_SCP_ADDR	IE_SCP_ADDR % EI_MEMSIZE
     53 
     54 /*
     55  * The ROM on the Ether1 is a bit oddly wired, in that the interrupt line
     56  * is wired up as the high-order address line, so as to allow the interrupt
     57  * status bit the first byte to reflect the actual interrupt status.
     58  */
     59 
     60 #define EI_ROMSIZE	0x20
     61 /* First eight bytes are standard extended podule ID. */
     62 #define EI_ROM_HWREV	0x08
     63 #define EI_ROM_EADDR	0x09
     64 #define EI_ROM_CRC	0x1c
     65 
     66 #endif
     67