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if_eireg.h revision 1.2.16.1
      1  1.2.16.1  skrll /* $NetBSD: if_eireg.h,v 1.2.16.1 2004/08/03 10:50:27 skrll Exp $ */
      2       1.1  bjh21 
      3       1.1  bjh21 /*
      4       1.1  bjh21  * 2000 Ben Harris
      5       1.1  bjh21  *
      6       1.1  bjh21  * This file is in the public domain.
      7       1.1  bjh21  */
      8       1.1  bjh21 
      9       1.1  bjh21 /*
     10       1.1  bjh21  * if_eireg.h - register definitions etc for the Acorn Ether1 card
     11       1.1  bjh21  */
     12       1.1  bjh21 
     13       1.1  bjh21 #ifndef _IF_EIREG_H_
     14       1.1  bjh21 #define _IF_EIREG_H_
     15       1.1  bjh21 
     16       1.1  bjh21 /*
     17       1.1  bjh21  * The card has three address spaces.  The ROM is mapped into the
     18       1.2  bjh21  * bottom 32 bytes of SYNC address space, and contains the
     19       1.1  bjh21  * expansion card ID information and the Ethernet address.  There is a
     20       1.2  bjh21  * pair of write-only registers at the start of the FAST address
     21       1.1  bjh21  * space.  One of these performs miscellaneous control functions, and
     22       1.1  bjh21  * the other acts as a page selector for the board memory.  The board
     23       1.1  bjh21  * has 64k of RAM, and 4k pages of this can be mapped at offset 0x2000
     24       1.1  bjh21  * in the FAST space by writing the page number to the page register.
     25       1.1  bjh21  * The 82586 has access to the whole of this memory and (I believe)
     26       1.1  bjh21  * sees it as the top 64k of its address space.
     27       1.1  bjh21  */
     28       1.1  bjh21 
     29       1.1  bjh21 /* Registers in the board's control space */
     30       1.1  bjh21 #define EI_PAGE		0
     31       1.1  bjh21 #define EI_CONTROL	1
     32       1.2  bjh21 #define EI_CTL_RST	0x01 /* Reset */
     33       1.2  bjh21 #define EI_CTL_LB	0x02 /* Loop-back */
     34       1.2  bjh21 #define EI_CTL_CA	0x04 /* Channel Attention */
     35       1.2  bjh21 #define EI_CTL_CLI	0x08 /* Clear Interrupt */
     36       1.1  bjh21 
     37       1.1  bjh21 /* Offset of base of memory in bus_addr_t units */
     38       1.1  bjh21 #define EI_MEMOFF	0x2000
     39       1.1  bjh21 
     40       1.1  bjh21 /*
     41       1.1  bjh21  * All addresses within board RAM are in bytes of actual RAM.  RAM is
     42       1.2  bjh21  * 16 bits wide, and can only be accessed by word transfers
     43       1.1  bjh21  * (bus_space_xxx_2).
     44       1.1  bjh21  */
     45       1.1  bjh21 #define EI_MEMSIZE	0x10000
     46       1.1  bjh21 #define EI_MEMBASE	(0x1000000 - EI_MEMSIZE)
     47       1.1  bjh21 #define EI_PAGESIZE	0x1000
     48       1.1  bjh21 #define EI_NPAGES	(EI_MEMSIZE / EI_PAGESIZE)
     49       1.1  bjh21 #define ei_atop(a)	(((a) % EI_MEMSIZE) / EI_PAGESIZE)
     50       1.1  bjh21 #define ei_atopo(a)	((a) % EI_PAGESIZE)
     51       1.1  bjh21 
     52       1.1  bjh21 #define EI_SCP_ADDR	IE_SCP_ADDR % EI_MEMSIZE
     53       1.1  bjh21 
     54       1.2  bjh21 /*
     55  1.2.16.1  skrll  * The ROM on the Ether1 is a bit oddly wired, in that the interrupt line
     56  1.2.16.1  skrll  * is wired up as the high-order address line, so as to allow the interrupt
     57  1.2.16.1  skrll  * status bit the first byte to reflect the actual interrupt status.
     58       1.2  bjh21  */
     59       1.2  bjh21 
     60       1.2  bjh21 #define EI_ROMSIZE	0x20
     61       1.2  bjh21 /* First eight bytes are standard extended podule ID. */
     62       1.2  bjh21 #define EI_ROM_HWREV	0x08
     63       1.2  bjh21 #define EI_ROM_EADDR	0x09
     64       1.2  bjh21 #define EI_ROM_CRC	0x1c
     65       1.1  bjh21 
     66       1.1  bjh21 #endif
     67