1 /* $NetBSD: sec.c,v 1.17 2017/01/20 12:25:07 maya Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2006 Ben Harris 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /* 30 * sec.c -- driver for Acorn SCSI expansion cards (AKA30, AKA31, AKA32) 31 * 32 * These cards are documented in: 33 * Acorn Archimedes 500 series / Acorn R200 series Technical Reference Manual 34 * Published by Acorn Computers Limited 35 * ISBN 1 85250 086 7 36 * Part number 0486,052 37 * Issue 1, November 1990 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: sec.c,v 1.17 2017/01/20 12:25:07 maya Exp $"); 42 43 #include <sys/param.h> 44 45 #include <sys/buf.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 #include <sys/reboot.h> /* For bootverbose */ 49 #include <sys/syslog.h> 50 #include <sys/systm.h> 51 52 #include <dev/scsipi/scsi_all.h> 53 #include <dev/scsipi/scsipi_all.h> 54 #include <dev/scsipi/scsiconf.h> 55 56 #include <sys/bus.h> 57 58 #include <dev/ic/wd33c93reg.h> 59 #include <dev/ic/wd33c93var.h> 60 #include <dev/ic/nec71071reg.h> 61 62 #include <dev/podulebus/podulebus.h> 63 #include <dev/podulebus/podules.h> 64 #include <dev/podulebus/powerromreg.h> 65 #include <dev/podulebus/secreg.h> 66 67 #include "opt_ddb.h" 68 69 struct sec_softc { 70 struct wd33c93_softc sc_sbic; 71 bus_space_tag_t sc_pod_t; 72 bus_space_handle_t sc_pod_h; 73 bus_space_tag_t sc_mod_t; 74 bus_space_handle_t sc_mod_h; 75 void *sc_ih; 76 struct evcnt sc_intrcnt; 77 uint8_t sc_mpr; 78 79 /* Details of the current DMA transfer */ 80 bool sc_dmaactive; 81 void * sc_dmaaddr; 82 int sc_dmaoff; 83 size_t sc_dmalen; 84 bool sc_dmain; 85 /* Details of the current block within the above transfer */ 86 size_t sc_dmablk; 87 }; 88 89 #define SEC_DMABLK 16384 90 #define SEC_NBLKS 3 91 #define SEC_DMAMODE MODE_TMODE_DMD 92 93 /* autoconfiguration glue */ 94 static int sec_match(device_t, cfdata_t, void *); 95 static void sec_attach(device_t, device_t, void *); 96 97 /* shutdown hook */ 98 static bool sec_shutdown(device_t, int); 99 100 /* callbacks from MI WD33C93 driver */ 101 static int sec_dmasetup(struct wd33c93_softc *, void **, size_t *, int, 102 size_t *); 103 static int sec_dmago(struct wd33c93_softc *); 104 static void sec_dmastop(struct wd33c93_softc *); 105 static void sec_reset(struct wd33c93_softc *); 106 107 static int sec_intr(void *); 108 static int sec_dmatc(struct sec_softc *sc); 109 110 void sec_dumpdma(void *arg); 111 112 CFATTACH_DECL_NEW(sec, sizeof(struct sec_softc), 113 sec_match, sec_attach, NULL, NULL); 114 115 static inline void 116 sec_setpage(struct sec_softc *sc, int page) 117 { 118 119 sc->sc_mpr = (sc->sc_mpr & ~SEC_MPR_PAGE) | page; 120 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr); 121 } 122 123 static inline void 124 sec_cli(struct sec_softc *sc) 125 { 126 127 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_CLRINT, 0); 128 } 129 130 static inline void 131 dmac_write(struct sec_softc *sc, int reg, uint8_t val) 132 { 133 134 bus_space_write_1(sc->sc_mod_t, sc->sc_mod_h, 135 SEC_DMAC + DMAC(reg), val); 136 } 137 138 static inline uint8_t 139 dmac_read(struct sec_softc *sc, int reg) 140 { 141 142 return bus_space_read_1(sc->sc_mod_t, sc->sc_mod_h, 143 SEC_DMAC + DMAC(reg)); 144 } 145 146 static int 147 sec_match(device_t parent, cfdata_t cf, void *aux) 148 { 149 struct podulebus_attach_args *pa = aux; 150 151 /* Standard ROM, skipping the MCS card that used the same ID. */ 152 if (pa->pa_product == PODULE_ACORN_SCSI && 153 strncmp(pa->pa_descr, "MCS", 3) != 0) 154 return 1; 155 156 /* PowerROM */ 157 if (pa->pa_product == PODULE_ALSYSTEMS_SCSI && 158 podulebus_initloader(pa) == 0 && 159 podloader_callloader(pa, 0, 0) == PRID_ACORN_SCSI1) 160 return 1; 161 162 return 0; 163 } 164 165 static void 166 sec_attach(device_t parent, device_t self, void *aux) 167 { 168 struct podulebus_attach_args *pa = aux; 169 struct sec_softc *sc = device_private(self); 170 int i; 171 172 sc->sc_sbic.sc_dev = self; 173 /* Set up bus spaces */ 174 sc->sc_pod_t = pa->pa_fast_t; 175 bus_space_map(pa->pa_fast_t, pa->pa_fast_base, 0x1000, 0, 176 &sc->sc_pod_h); 177 sc->sc_mod_t = pa->pa_mod_t; 178 bus_space_map(pa->pa_mod_t, pa->pa_mod_base, 0x1000, 0, 179 &sc->sc_mod_h); 180 181 sc->sc_sbic.sc_regt = sc->sc_mod_t; 182 bus_space_subregion(sc->sc_mod_t, sc->sc_mod_h, SEC_SBIC + 0, 1, 183 &sc->sc_sbic.sc_asr_regh); 184 bus_space_subregion(sc->sc_mod_t, sc->sc_mod_h, SEC_SBIC + 1, 1, 185 &sc->sc_sbic.sc_data_regh); 186 187 sc->sc_sbic.sc_id = 7; 188 sc->sc_sbic.sc_clkfreq = SEC_CLKFREQ; 189 sc->sc_sbic.sc_dmamode = SBIC_CTL_BURST_DMA; 190 191 sc->sc_sbic.sc_adapter.adapt_request = wd33c93_scsi_request; 192 sc->sc_sbic.sc_adapter.adapt_minphys = minphys; 193 194 sc->sc_sbic.sc_dmasetup = sec_dmasetup; 195 sc->sc_sbic.sc_dmago = sec_dmago; 196 sc->sc_sbic.sc_dmastop = sec_dmastop; 197 sc->sc_sbic.sc_reset = sec_reset; 198 199 sc->sc_mpr = 0; 200 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr); 201 202 for (i = 0; i < SEC_NPAGES; i++) { 203 sec_setpage(sc, i); 204 bus_space_set_region_2(sc->sc_mod_t, sc->sc_mod_h, 205 SEC_SRAM, 0, SEC_PAGESIZE / 2); 206 } 207 208 wd33c93_attach(&sc->sc_sbic); 209 210 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 211 device_xname(self), "intr"); 212 sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, sec_intr, 213 sc, &sc->sc_intrcnt); 214 sec_cli(sc); 215 sc->sc_mpr |= SEC_MPR_IE; 216 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr); 217 if (!pmf_device_register1(sc->sc_sbic.sc_dev, NULL, NULL, sec_shutdown)) 218 aprint_error_dev(sc->sc_sbic.sc_dev, 219 "couldn't establish power handler\n"); 220 } 221 222 /* 223 * Before reboot, reset the page register to 0 so that RISC OS can see 224 * the podule ROM. 225 */ 226 static bool 227 sec_shutdown(device_t dev, int howto) 228 { 229 struct sec_softc *sc = device_private(dev); 230 231 sec_setpage(sc, 0); 232 return true; 233 } 234 235 static void 236 sec_copyin(struct sec_softc *sc, void *dest, int src, size_t size) 237 { 238 uint16_t tmp, *wptr; 239 int cnt, extra_byte; 240 241 KASSERT(src >= 0); 242 KASSERT(src + size <= SEC_MEMSIZE); 243 if (src % 2 != 0) { 244 /* 245 * There's a stray byte at the start. Read the word 246 * containing it. 247 */ 248 sec_setpage(sc, src / SEC_PAGESIZE); 249 tmp = bus_space_read_2(sc->sc_mod_t, sc->sc_mod_h, 250 SEC_SRAM + (src % SEC_PAGESIZE / 2)); 251 *(uint8_t *)dest = tmp >> 8; 252 dest = ((uint8_t *)dest) + 1; 253 src++; size--; 254 } 255 KASSERT(src % 2 == 0); 256 KASSERT(ALIGNED_POINTER(dest, uint16_t)); 257 wptr = dest; 258 extra_byte = size % 2; 259 size -= extra_byte; 260 while (size > 0) { 261 cnt = SEC_PAGESIZE - src % SEC_PAGESIZE; 262 if (cnt > size) 263 cnt = size; 264 sec_setpage(sc, src / SEC_PAGESIZE); 265 /* bus ops are in words */ 266 bus_space_read_region_2(sc->sc_mod_t, sc->sc_mod_h, 267 SEC_SRAM + src % SEC_PAGESIZE / 2, wptr, cnt / 2); 268 src += cnt; 269 wptr += cnt / 2; 270 size -= cnt; 271 } 272 if (extra_byte) { 273 sec_setpage(sc, src / SEC_PAGESIZE); 274 *(u_int8_t *)wptr = 275 bus_space_read_2(sc->sc_mod_t, sc->sc_mod_h, 276 SEC_SRAM + src % SEC_PAGESIZE / 2) & 0xff; 277 } 278 } 279 280 static void 281 sec_copyout(struct sec_softc *sc, const void *src, int dest, size_t size) 282 { 283 int cnt, extra_byte; 284 const uint16_t *wptr; 285 uint16_t tmp; 286 287 KASSERT(dest >= 0); 288 KASSERT(dest + size <= SEC_MEMSIZE); 289 if (dest % 2 != 0) { 290 /* 291 * There's a stray byte at the start. Read the word 292 * containing it. 293 */ 294 sec_setpage(sc, dest / SEC_PAGESIZE); 295 tmp = bus_space_read_2(sc->sc_mod_t, sc->sc_mod_h, 296 SEC_SRAM + (dest % SEC_PAGESIZE / 2)); 297 tmp &= 0xff; 298 tmp |= *(uint8_t const *)src << 8; 299 bus_space_write_2(sc->sc_mod_t, sc->sc_mod_h, 300 SEC_SRAM + (dest % SEC_PAGESIZE / 2), tmp); 301 src = ((uint8_t const *)src) + 1; 302 dest++; size--; 303 } 304 KASSERT(dest % 2 == 0); 305 KASSERT(ALIGNED_POINTER(src, uint16_t)); 306 wptr = src; 307 extra_byte = size % 2; 308 size -= extra_byte; 309 while (size > 0) { 310 cnt = SEC_PAGESIZE - dest % SEC_PAGESIZE; 311 if (cnt > size) 312 cnt = size; 313 sec_setpage(sc, dest / SEC_PAGESIZE); 314 /* bus ops are in words */ 315 bus_space_write_region_2(sc->sc_mod_t, sc->sc_mod_h, 316 dest % SEC_PAGESIZE / 2, wptr, cnt / 2); 317 wptr += cnt / 2; 318 dest += cnt; 319 size -= cnt; 320 } 321 if (extra_byte) { 322 /* 323 * There's a stray byte at the end. Read the word 324 * containing it. 325 */ 326 sec_setpage(sc, dest / SEC_PAGESIZE); 327 tmp = bus_space_read_2(sc->sc_mod_t, sc->sc_mod_h, 328 SEC_SRAM + (dest % SEC_PAGESIZE / 2)); 329 tmp &= 0xff00; 330 tmp |= *(uint8_t const *)wptr; 331 bus_space_write_2(sc->sc_mod_t, sc->sc_mod_h, 332 SEC_SRAM + (dest % SEC_PAGESIZE / 2), tmp); 333 } 334 } 335 336 static void 337 sec_dmablk(struct sec_softc *sc, int blk) 338 { 339 int off; 340 size_t len; 341 342 KASSERT(blk >= 0); 343 KASSERT(blk * SEC_DMABLK < sc->sc_dmalen); 344 off = (blk % SEC_NBLKS) * SEC_DMABLK + sc->sc_dmaoff; 345 len = MIN(SEC_DMABLK, sc->sc_dmalen - (blk * SEC_DMABLK)); 346 dmac_write(sc, NEC71071_ADDRLO, off & 0xff); 347 dmac_write(sc, NEC71071_ADDRMID, off >> 8); 348 dmac_write(sc, NEC71071_ADDRHI, 0); 349 /* 350 * "Note: The number of DMA transfer cycles is actually the 351 * value of the current count register + 1. Therefore, when 352 * programming the count register, specify the number of DMA 353 * transfers minus one." -- uPD71071 datasheet 354 */ 355 dmac_write(sc, NEC71071_COUNTLO, (len - 1) & 0xff); 356 dmac_write(sc, NEC71071_COUNTHI, (len - 1) >> 8); 357 } 358 359 static void 360 sec_copyoutblk(struct sec_softc *sc, int blk) 361 { 362 int off; 363 size_t len; 364 365 KASSERT(blk >= 0); 366 KASSERT(blk * SEC_DMABLK < sc->sc_dmalen); 367 KASSERT(!sc->sc_dmain); 368 off = (blk % SEC_NBLKS) * SEC_DMABLK + sc->sc_dmaoff; 369 len = MIN(SEC_DMABLK, sc->sc_dmalen - (blk * SEC_DMABLK)); 370 sec_copyout(sc, (char*)sc->sc_dmaaddr + (blk * SEC_DMABLK), off, len); 371 } 372 373 static void 374 sec_copyinblk(struct sec_softc *sc, int blk) 375 { 376 int off; 377 size_t len; 378 379 KASSERT(blk >= 0); 380 KASSERT(blk * SEC_DMABLK < sc->sc_dmalen); 381 KASSERT(sc->sc_dmain); 382 off = (blk % SEC_NBLKS) * SEC_DMABLK + sc->sc_dmaoff; 383 len = MIN(SEC_DMABLK, sc->sc_dmalen - (blk * SEC_DMABLK)); 384 sec_copyin(sc, (char*)sc->sc_dmaaddr + (blk * SEC_DMABLK), off, len); 385 } 386 387 static int 388 sec_dmasetup(struct wd33c93_softc *sc_sbic, void **addr, size_t *len, 389 int datain, size_t *dmasize) 390 { 391 struct sec_softc *sc = (struct sec_softc *)sc_sbic; 392 uint8_t mode; 393 394 sc->sc_dmaaddr = *addr; 395 sc->sc_dmaoff = ALIGNED_POINTER(*addr, uint16_t) ? 0 : 1; 396 sc->sc_dmalen = *len; 397 sc->sc_dmain = datain; 398 sc->sc_dmablk = 0; 399 mode = SEC_DMAMODE | (datain ? MODE_TDIR_IOTM : MODE_TDIR_MTIO); 400 /* Program first block into DMAC and queue up second. */ 401 dmac_write(sc, NEC71071_CHANNEL, 0); 402 if (!sc->sc_dmain) 403 sec_copyoutblk(sc, 0); 404 sec_dmablk(sc, 0); 405 /* Mode control register */ 406 dmac_write(sc, NEC71071_MODE, mode); 407 return sc->sc_dmalen; 408 } 409 410 static int 411 sec_dmago(struct wd33c93_softc *sc_sbic) 412 { 413 struct sec_softc *sc = (struct sec_softc *)sc_sbic; 414 415 dmac_write(sc, NEC71071_MASK, 0xe); 416 sc->sc_dmaactive = true; 417 if (!sc->sc_dmain && sc->sc_dmalen > SEC_DMABLK) 418 sec_copyoutblk(sc, 1); 419 return sc->sc_dmalen; 420 } 421 422 static void 423 sec_dmastop(struct wd33c93_softc *sc_sbic) 424 { 425 struct sec_softc *sc = (struct sec_softc *)sc_sbic; 426 427 dmac_write(sc, NEC71071_MASK, 0xf); 428 if (sc->sc_dmaactive && sc->sc_dmain) 429 sec_copyinblk(sc, sc->sc_dmablk); 430 sc->sc_dmaactive = false; 431 } 432 433 /* 434 * Reset the SCSI bus, and incidentally the SBIC and DMAC. 435 */ 436 static void 437 sec_reset(struct wd33c93_softc *sc_sbic) 438 { 439 struct sec_softc *sc = (struct sec_softc *)sc_sbic; 440 uint8_t asr, csr; 441 442 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, 443 sc->sc_mpr | SEC_MPR_UR); 444 DELAY(7); 445 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr); 446 /* Wait for and clear the reset-complete interrupt */ 447 do 448 GET_SBIC_asr(sc_sbic, asr); 449 while (!(asr & SBIC_ASR_INT)); 450 GET_SBIC_csr(sc_sbic, csr); 451 __USE(csr); 452 dmac_write(sc, NEC71071_DCTRL1, DCTRL1_CMP | DCTRL1_RQL); 453 dmac_write(sc, NEC71071_DCTRL2, 0); 454 sec_cli(sc); 455 } 456 457 static int 458 sec_intr(void *arg) 459 { 460 struct sec_softc *sc = arg; 461 u_int8_t isr; 462 463 isr = bus_space_read_1(sc->sc_pod_t, sc->sc_pod_h, SEC_ISR); 464 if (!(isr & SEC_ISR_IRQ)) 465 return 0; 466 if (isr & SEC_ISR_DMAC) 467 sec_dmatc(sc); 468 if (isr & SEC_ISR_SBIC) 469 wd33c93_intr(&sc->sc_sbic); 470 return 1; 471 } 472 473 static int 474 sec_dmatc(struct sec_softc *sc) 475 { 476 477 sec_cli(sc); 478 /* DMAC finished block n-1 and is now working on block n */ 479 sc->sc_dmablk++; 480 if (sc->sc_dmalen > sc->sc_dmablk * SEC_DMABLK) { 481 dmac_write(sc, NEC71071_CHANNEL, 0); 482 sec_dmablk(sc, sc->sc_dmablk); 483 dmac_write(sc, NEC71071_MASK, 0xe); 484 if (!sc->sc_dmain && 485 sc->sc_dmalen > (sc->sc_dmablk + 1) * SEC_DMABLK) 486 sec_copyoutblk(sc, sc->sc_dmablk + 1); 487 } else { 488 /* All blocks fully processed. */ 489 sc->sc_dmaactive = false; 490 } 491 if (sc->sc_dmain) 492 sec_copyinblk(sc, sc->sc_dmablk - 1); 493 return 1; 494 } 495 496 #ifdef DDB 497 void 498 sec_dumpdma(void *arg) 499 { 500 struct sec_softc *sc = arg; 501 502 dmac_write(sc, NEC71071_CHANNEL, 0); 503 printf("%s: DMA state: cur count %02x%02x cur addr %02x%02x%02x ", 504 device_xname(sc->sc_sbic.sc_dev), 505 dmac_read(sc, NEC71071_COUNTHI), dmac_read(sc, NEC71071_COUNTLO), 506 dmac_read(sc, NEC71071_ADDRHI), dmac_read(sc, NEC71071_ADDRMID), 507 dmac_read(sc, NEC71071_ADDRLO)); 508 dmac_write(sc, NEC71071_CHANNEL, 0 | CHANNEL_WBASE); 509 printf("base count %02x%02x base addr %02x%02x%02x\n", 510 dmac_read(sc, NEC71071_COUNTHI), dmac_read(sc, NEC71071_COUNTLO), 511 dmac_read(sc, NEC71071_ADDRHI), dmac_read(sc, NEC71071_ADDRMID), 512 dmac_read(sc, NEC71071_ADDRLO)); 513 printf("%s: DMA state: dctrl %1x%02x mode %02x status %02x req %02x " 514 "mask %02x\n", 515 device_xname(sc->sc_sbic.sc_dev), dmac_read(sc, NEC71071_DCTRL2), 516 dmac_read(sc, NEC71071_DCTRL1), dmac_read(sc, NEC71071_MODE), 517 dmac_read(sc, NEC71071_STATUS), dmac_read(sc, NEC71071_REQUEST), 518 dmac_read(sc, NEC71071_MASK)); 519 printf("%s: soft DMA state: %zd@%p%s%d\n", 520 device_xname(sc->sc_sbic.sc_dev), 521 sc->sc_dmalen, sc->sc_dmaaddr, sc->sc_dmain ? "<-" : "->", 522 sc->sc_dmaoff); 523 } 524 525 void sec_dumpall(void); /* Call from DDB */ 526 527 extern struct cfdriver sec_cd; 528 529 void sec_dumpall(void) 530 { 531 int i; 532 struct sec_softc *sc; 533 534 for (i = 0; i < sec_cd.cd_ndevs; ++i) { 535 sc = device_lookup_private(&sec_cd, i); 536 if (sc != NULL) 537 sec_dumpdma(sc); 538 } 539 } 540 #endif 541
Indexes created Sun Sep 21 19:09:51 GMT 2025