sec.c revision 1.1
1 /* $NetBSD: sec.c,v 1.1 2006/10/01 12:39:35 bjh21 Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2006 Ben Harris 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /* 30 * sec.c -- driver for Acorn SCSI expansion cards (AKA30, AKA31, AKA32) 31 * 32 * These cards are documented in: 33 * Acorn Archimedes 500 series / Acorn R200 series Technical Reference Manual 34 * Published by Acorn Computers Limited 35 * ISBN 1 85250 086 7 36 * Part number 0486,052 37 * Issue 1, November 1990 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: sec.c,v 1.1 2006/10/01 12:39:35 bjh21 Exp $"); 42 43 #include <sys/param.h> 44 45 #include <sys/buf.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 #include <sys/reboot.h> /* For bootverbose */ 49 #include <sys/syslog.h> 50 #include <sys/systm.h> 51 52 #include <dev/scsipi/scsi_all.h> 53 #include <dev/scsipi/scsipi_all.h> 54 #include <dev/scsipi/scsiconf.h> 55 56 #include <machine/bus.h> 57 58 #include <dev/ic/wd33c93reg.h> 59 #include <dev/ic/wd33c93var.h> 60 #include <dev/ic/nec71071reg.h> 61 62 #include <dev/podulebus/podulebus.h> 63 #include <dev/podulebus/podules.h> 64 #include <dev/podulebus/powerromreg.h> 65 #include <dev/podulebus/secreg.h> 66 67 #include "opt_ddb.h" 68 69 struct sec_softc { 70 struct wd33c93_softc sc_sbic; 71 bus_space_tag_t sc_pod_t; 72 bus_space_handle_t sc_pod_h; 73 bus_space_tag_t sc_mod_t; 74 bus_space_handle_t sc_mod_h; 75 void *sc_ih; 76 struct evcnt sc_intrcnt; 77 uint8_t sc_mpr; 78 79 /* Details of the current DMA transfer */ 80 boolean_t sc_dmaactive; 81 caddr_t sc_dmaaddr; 82 int sc_dmaoff; 83 size_t sc_dmalen; 84 boolean_t sc_dmain; 85 /* Details of the current block within the above transfer */ 86 size_t sc_dmablk; 87 }; 88 89 #define SEC_DMABLK 16384 90 #define SEC_NBLKS 3 91 #define SEC_DMAMODE MODE_TMODE_SGL 92 93 /* autoconfiguration glue */ 94 static int sec_match(struct device *, struct cfdata *, void *); 95 static void sec_attach(struct device *, struct device *, void *); 96 97 /* callbacks from MI WD33C93 driver */ 98 static int sec_dmasetup(struct wd33c93_softc *, caddr_t *, size_t *, int, 99 size_t *); 100 static int sec_dmago(struct wd33c93_softc *); 101 static void sec_dmastop(struct wd33c93_softc *); 102 static void sec_reset(struct wd33c93_softc *); 103 104 static int sec_intr(void *); 105 static int sec_dmatc(struct sec_softc *sc); 106 107 void sec_dumpdma(void *arg); 108 109 CFATTACH_DECL(sec, sizeof(struct sec_softc), 110 sec_match, sec_attach, NULL, NULL); 111 112 static inline void 113 sec_setpage(struct sec_softc *sc, int page) 114 { 115 116 sc->sc_mpr = (sc->sc_mpr & ~SEC_MPR_PAGE) | page; 117 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr); 118 } 119 120 static inline void 121 sec_cli(struct sec_softc *sc) 122 { 123 124 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_CLRINT, 0); 125 } 126 127 static inline void 128 dmac_write(struct sec_softc *sc, int reg, uint8_t val) 129 { 130 131 bus_space_write_1(sc->sc_mod_t, sc->sc_mod_h, 132 SEC_DMAC + DMAC(reg), val); 133 } 134 135 static inline uint8_t 136 dmac_read(struct sec_softc *sc, int reg) 137 { 138 139 return bus_space_read_1(sc->sc_mod_t, sc->sc_mod_h, 140 SEC_DMAC + DMAC(reg)); 141 } 142 143 static int 144 sec_match(struct device *parent, struct cfdata *cf, void *aux) 145 { 146 struct podulebus_attach_args *pa = aux; 147 148 /* Standard ROM, skipping the MCS card that used the same ID. */ 149 if (pa->pa_product == PODULE_ACORN_SCSI && 150 strncmp(pa->pa_descr, "MCS", 3) != 0) 151 return 1; 152 153 /* PowerROM */ 154 if (pa->pa_product == PODULE_ALSYSTEMS_SCSI && 155 podulebus_initloader(pa) == 0 && 156 podloader_callloader(pa, 0, 0) == PRID_ACORN_SCSI1) 157 return 1; 158 159 return 0; 160 } 161 162 static void 163 sec_attach(struct device *parent, struct device *self, void *aux) 164 { 165 struct podulebus_attach_args *pa = aux; 166 struct sec_softc *sc = device_private(self); 167 int i; 168 169 /* Set up bus spaces */ 170 sc->sc_pod_t = pa->pa_fast_t; 171 bus_space_map(pa->pa_fast_t, pa->pa_fast_base, 0x1000, 0, 172 &sc->sc_pod_h); 173 sc->sc_mod_t = pa->pa_mod_t; 174 bus_space_map(pa->pa_mod_t, pa->pa_mod_base, 0x1000, 0, 175 &sc->sc_mod_h); 176 177 sc->sc_sbic.sc_regt = sc->sc_mod_t; 178 bus_space_subregion(sc->sc_mod_t, sc->sc_mod_h, SEC_SBIC, 179 0x1000 - SEC_SBIC, &sc->sc_sbic.sc_regh); 180 181 sc->sc_sbic.sc_id = 7; 182 sc->sc_sbic.sc_clkfreq = SEC_CLKFREQ; 183 184 sc->sc_sbic.sc_adapter.adapt_request = wd33c93_scsi_request; 185 sc->sc_sbic.sc_adapter.adapt_minphys = minphys; 186 187 sc->sc_sbic.sc_dmasetup = sec_dmasetup; 188 sc->sc_sbic.sc_dmago = sec_dmago; 189 sc->sc_sbic.sc_dmastop = sec_dmastop; 190 sc->sc_sbic.sc_reset = sec_reset; 191 192 sc->sc_mpr = 0; 193 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr); 194 195 for (i = 0; i < SEC_NPAGES; i++) { 196 sec_setpage(sc, i); 197 bus_space_set_region_2(sc->sc_mod_t, sc->sc_mod_h, 198 SEC_SRAM, 0, SEC_PAGESIZE / 2); 199 } 200 201 wd33c93_attach(&sc->sc_sbic); 202 203 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 204 self->dv_xname, "intr"); 205 sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, sec_intr, 206 sc, &sc->sc_intrcnt); 207 sec_cli(sc); 208 sc->sc_mpr |= SEC_MPR_IE; 209 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr); 210 } 211 212 static void 213 sec_copyin(struct sec_softc *sc, void *dest, int src, size_t size) 214 { 215 uint16_t tmp, *wptr; 216 int cnt, extra_byte; 217 218 KASSERT(src >= 0); 219 KASSERT(src + size <= SEC_MEMSIZE); 220 if (src % 2 != 0) { 221 /* 222 * There's a stray byte at the start. Read the word 223 * containing it. 224 */ 225 sec_setpage(sc, src / SEC_PAGESIZE); 226 tmp = bus_space_read_2(sc->sc_mod_t, sc->sc_mod_h, 227 SEC_SRAM + (src % SEC_PAGESIZE / 2)); 228 *(uint8_t *)dest = tmp >> 8; 229 dest = ((uint8_t *)dest) + 1; 230 src++; size--; 231 } 232 KASSERT(src % 2 == 0); 233 KASSERT(ALIGNED_POINTER(dest, uint16_t)); 234 wptr = dest; 235 extra_byte = size % 2; 236 size -= extra_byte; 237 while (size > 0) { 238 cnt = SEC_PAGESIZE - src % SEC_PAGESIZE; 239 if (cnt > size) 240 cnt = size; 241 sec_setpage(sc, src / SEC_PAGESIZE); 242 /* bus ops are in words */ 243 bus_space_read_region_2(sc->sc_mod_t, sc->sc_mod_h, 244 SEC_SRAM + src % SEC_PAGESIZE / 2, wptr, cnt / 2); 245 src += cnt; 246 wptr += cnt / 2; 247 size -= cnt; 248 } 249 if (extra_byte) { 250 sec_setpage(sc, src / SEC_PAGESIZE); 251 *(u_int8_t *)wptr = 252 bus_space_read_2(sc->sc_mod_t, sc->sc_mod_h, 253 SEC_SRAM + src % SEC_PAGESIZE / 2) & 0xff; 254 } 255 } 256 257 static void 258 sec_copyout(struct sec_softc *sc, const void *src, int dest, size_t size) 259 { 260 int cnt, extra_byte; 261 const uint16_t *wptr; 262 uint16_t tmp; 263 264 KASSERT(dest >= 0); 265 KASSERT(dest + size <= SEC_MEMSIZE); 266 if (dest % 2 != 0) { 267 /* 268 * There's a stray byte at the start. Read the word 269 * containing it. 270 */ 271 sec_setpage(sc, dest / SEC_PAGESIZE); 272 tmp = bus_space_read_2(sc->sc_mod_t, sc->sc_mod_h, 273 SEC_SRAM + (dest % SEC_PAGESIZE / 2)); 274 tmp &= 0xff; 275 tmp |= *(uint8_t const *)src << 8; 276 bus_space_write_2(sc->sc_mod_t, sc->sc_mod_h, 277 SEC_SRAM + (dest % SEC_PAGESIZE / 2), tmp); 278 src = ((uint8_t const *)src) + 1; 279 dest++; size--; 280 } 281 KASSERT(dest % 2 == 0); 282 KASSERT(ALIGNED_POINTER(src, uint16_t)); 283 wptr = src; 284 extra_byte = size % 2; 285 size -= extra_byte; 286 while (size > 0) { 287 cnt = SEC_PAGESIZE - dest % SEC_PAGESIZE; 288 if (cnt > size) 289 cnt = size; 290 sec_setpage(sc, dest / SEC_PAGESIZE); 291 /* bus ops are in words */ 292 bus_space_write_region_2(sc->sc_mod_t, sc->sc_mod_h, 293 dest % SEC_PAGESIZE / 2, wptr, cnt / 2); 294 wptr += cnt / 2; 295 dest += cnt; 296 size -= cnt; 297 } 298 if (extra_byte) { 299 /* 300 * There's a stray byte at the end. Read the word 301 * containing it. 302 */ 303 sec_setpage(sc, dest / SEC_PAGESIZE); 304 tmp = bus_space_read_2(sc->sc_mod_t, sc->sc_mod_h, 305 SEC_SRAM + (dest % SEC_PAGESIZE / 2)); 306 tmp &= 0xff00; 307 tmp |= *(uint8_t const *)wptr; 308 bus_space_write_2(sc->sc_mod_t, sc->sc_mod_h, 309 SEC_SRAM + (dest % SEC_PAGESIZE / 2), tmp); 310 } 311 } 312 313 static void 314 sec_dmablk(struct sec_softc *sc, int blk) 315 { 316 int off; 317 size_t len; 318 319 KASSERT(blk >= 0); 320 KASSERT(blk * SEC_DMABLK < sc->sc_dmalen); 321 off = (blk % SEC_NBLKS) * SEC_DMABLK + sc->sc_dmaoff; 322 len = MIN(SEC_DMABLK, sc->sc_dmalen - (blk * SEC_DMABLK)); 323 if (!sc->sc_dmain) 324 sec_copyout(sc, sc->sc_dmaaddr + (blk * SEC_DMABLK), off, len); 325 dmac_write(sc, NEC71071_ADDRLO, off & 0xff); 326 dmac_write(sc, NEC71071_ADDRMID, off >> 8); 327 dmac_write(sc, NEC71071_ADDRHI, 0); 328 /* 329 * "Note: The number of DMA transfer cycles is actually the 330 * value of the current count register + 1. Therefore, when 331 * programming the count register, specify the number of DMA 332 * transfers minus one." -- uPD71071 datasheet 333 */ 334 dmac_write(sc, NEC71071_COUNTLO, (len - 1) & 0xff); 335 dmac_write(sc, NEC71071_COUNTHI, (len - 1) >> 8); 336 } 337 338 static void 339 sec_dmablkdone(struct sec_softc *sc, int blk) 340 { 341 int off; 342 size_t len; 343 344 KASSERT(blk >= 0); 345 KASSERT(blk * SEC_DMABLK < sc->sc_dmalen); 346 off = (blk % SEC_NBLKS) * SEC_DMABLK + sc->sc_dmaoff; 347 len = MIN(SEC_DMABLK, sc->sc_dmalen - (blk * SEC_DMABLK)); 348 if (sc->sc_dmain) 349 sec_copyin(sc, sc->sc_dmaaddr + (blk * SEC_DMABLK), off, len); 350 } 351 352 static int 353 sec_dmasetup(struct wd33c93_softc *sc_sbic, caddr_t *addr, size_t *len, 354 int datain, size_t *dmasize) 355 { 356 struct sec_softc *sc = (struct sec_softc *)sc_sbic; 357 uint8_t mode; 358 359 sc->sc_dmaaddr = *addr; 360 sc->sc_dmaoff = ALIGNED_POINTER(*addr, uint16_t) ? 0 : 1; 361 sc->sc_dmalen = *len; 362 sc->sc_dmain = datain; 363 sc->sc_dmablk = 0; 364 mode = SEC_DMAMODE | (datain ? MODE_TDIR_IOTM : MODE_TDIR_MTIO); 365 /* Program first block into DMAC and queue up second. */ 366 dmac_write(sc, NEC71071_CHANNEL, 0); 367 sec_dmablk(sc, 0); 368 if (sc->sc_dmalen > SEC_DMABLK) { 369 dmac_write(sc, NEC71071_CHANNEL, 0 | CHANNEL_WBASE); 370 sec_dmablk(sc, 1); 371 mode |= MODE_AUTI; 372 } 373 /* Mode control register */ 374 dmac_write(sc, NEC71071_MODE, mode); 375 return sc->sc_dmalen; 376 } 377 378 static int 379 sec_dmago(struct wd33c93_softc *sc_sbic) 380 { 381 struct sec_softc *sc = (struct sec_softc *)sc_sbic; 382 383 dmac_write(sc, NEC71071_MASK, 0xe); 384 sc->sc_dmaactive = TRUE; 385 return sc->sc_dmalen; 386 } 387 388 static void 389 sec_dmastop(struct wd33c93_softc *sc_sbic) 390 { 391 struct sec_softc *sc = (struct sec_softc *)sc_sbic; 392 393 dmac_write(sc, NEC71071_MASK, 0xf); 394 if (sc->sc_dmaactive) 395 sec_dmablkdone(sc, sc->sc_dmablk); 396 sc->sc_dmaactive = FALSE; 397 } 398 399 /* 400 * Reset the SCSI bus, and incidentally the SBIC and DMAC. 401 */ 402 static void 403 sec_reset(struct wd33c93_softc *sc_sbic) 404 { 405 struct sec_softc *sc = (struct sec_softc *)sc_sbic; 406 uint8_t asr, csr; 407 408 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, 409 sc->sc_mpr | SEC_MPR_UR); 410 DELAY(7); 411 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr); 412 /* Wait for and clear the reset-complete interrupt */ 413 do 414 GET_SBIC_asr(sc_sbic, asr); 415 while (!(asr & SBIC_ASR_INT)); 416 GET_SBIC_csr(sc_sbic, csr); 417 dmac_write(sc, NEC71071_DCTRL1, DCTRL1_CMP | DCTRL1_RQL); 418 dmac_write(sc, NEC71071_DCTRL2, 0); 419 sec_cli(sc); 420 } 421 422 static int 423 sec_intr(void *arg) 424 { 425 struct sec_softc *sc = arg; 426 u_int8_t isr; 427 428 isr = bus_space_read_1(sc->sc_pod_t, sc->sc_pod_h, SEC_ISR); 429 if (!(isr & SEC_ISR_IRQ)) 430 return 0; 431 if (isr & SEC_ISR_DMAC) 432 sec_dmatc(sc); 433 if (isr & SEC_ISR_SBIC) 434 wd33c93_intr(&sc->sc_sbic); 435 return 1; 436 } 437 438 static int 439 sec_dmatc(struct sec_softc *sc) 440 { 441 442 sec_cli(sc); 443 /* DMAC finished block n-1 and is now working on block n */ 444 sc->sc_dmablk++; 445 if (sc->sc_dmalen > (sc->sc_dmablk + 1) * SEC_DMABLK) { 446 /* Queue up another block */ 447 dmac_write(sc, NEC71071_CHANNEL, 0 | CHANNEL_WBASE); 448 sec_dmablk(sc, sc->sc_dmablk + 1); 449 } else if (sc->sc_dmalen > sc->sc_dmablk * SEC_DMABLK) { 450 /* No more blocks to queue -- cancel autoinitialize mode */ 451 dmac_write(sc, NEC71071_MODE, SEC_DMAMODE | 452 (sc->sc_dmain ? MODE_TDIR_IOTM : MODE_TDIR_MTIO)); 453 } else { 454 /* All blocks fully processed. */ 455 sc->sc_dmaactive = FALSE; 456 } 457 sec_dmablkdone(sc, sc->sc_dmablk - 1); 458 return 1; 459 } 460 461 #ifdef DDB 462 void 463 sec_dumpdma(void *arg) 464 { 465 struct sec_softc *sc = arg; 466 467 dmac_write(sc, NEC71071_CHANNEL, 0); 468 printf("%s: DMA state: cur count %02x%02x cur addr %02x%02x%02x ", 469 sc->sc_sbic.sc_dev.dv_xname, 470 dmac_read(sc, NEC71071_COUNTHI), dmac_read(sc, NEC71071_COUNTLO), 471 dmac_read(sc, NEC71071_ADDRHI), dmac_read(sc, NEC71071_ADDRMID), 472 dmac_read(sc, NEC71071_ADDRLO)); 473 dmac_write(sc, NEC71071_CHANNEL, 0 | CHANNEL_WBASE); 474 printf("base count %02x%02x base addr %02x%02x%02x\n", 475 dmac_read(sc, NEC71071_COUNTHI), dmac_read(sc, NEC71071_COUNTLO), 476 dmac_read(sc, NEC71071_ADDRHI), dmac_read(sc, NEC71071_ADDRMID), 477 dmac_read(sc, NEC71071_ADDRLO)); 478 printf("%s: DMA state: dctrl %1x%02x mode %02x status %02x req %02x " 479 "mask %02x\n", 480 sc->sc_sbic.sc_dev.dv_xname, dmac_read(sc, NEC71071_DCTRL2), 481 dmac_read(sc, NEC71071_DCTRL1), dmac_read(sc, NEC71071_MODE), 482 dmac_read(sc, NEC71071_STATUS), dmac_read(sc, NEC71071_REQUEST), 483 dmac_read(sc, NEC71071_MASK)); 484 printf("%s: soft DMA state: %zd@%p%s%d\n", sc->sc_sbic.sc_dev.dv_xname, 485 sc->sc_dmalen, sc->sc_dmaaddr, sc->sc_dmain ? "<-" : "->", 486 sc->sc_dmaoff); 487 } 488 489 void sec_dumpall(void); /* Call from DDB */ 490 491 extern struct cfdriver sec_cd; 492 493 void sec_dumpall(void) 494 { 495 int i; 496 497 for (i = 0; i < sec_cd.cd_ndevs; ++i) 498 if (sec_cd.cd_devs[i]) 499 sec_dumpdma(sec_cd.cd_devs[i]); 500 } 501 #endif 502
Indexes created Wed Sep 24 02:09:48 GMT 2025