sec.c revision 1.13
1 /* $NetBSD: sec.c,v 1.13 2009/01/25 15:23:42 bjh21 Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2006 Ben Harris 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /* 30 * sec.c -- driver for Acorn SCSI expansion cards (AKA30, AKA31, AKA32) 31 * 32 * These cards are documented in: 33 * Acorn Archimedes 500 series / Acorn R200 series Technical Reference Manual 34 * Published by Acorn Computers Limited 35 * ISBN 1 85250 086 7 36 * Part number 0486,052 37 * Issue 1, November 1990 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: sec.c,v 1.13 2009/01/25 15:23:42 bjh21 Exp $"); 42 43 #include <sys/param.h> 44 45 #include <sys/buf.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 #include <sys/reboot.h> /* For bootverbose */ 49 #include <sys/syslog.h> 50 #include <sys/systm.h> 51 52 #include <dev/scsipi/scsi_all.h> 53 #include <dev/scsipi/scsipi_all.h> 54 #include <dev/scsipi/scsiconf.h> 55 56 #include <sys/bus.h> 57 58 #include <dev/ic/wd33c93reg.h> 59 #include <dev/ic/wd33c93var.h> 60 #include <dev/ic/nec71071reg.h> 61 62 #include <dev/podulebus/podulebus.h> 63 #include <dev/podulebus/podules.h> 64 #include <dev/podulebus/powerromreg.h> 65 #include <dev/podulebus/secreg.h> 66 67 #include "opt_ddb.h" 68 69 struct sec_softc { 70 struct wd33c93_softc sc_sbic; 71 bus_space_tag_t sc_pod_t; 72 bus_space_handle_t sc_pod_h; 73 bus_space_tag_t sc_mod_t; 74 bus_space_handle_t sc_mod_h; 75 void *sc_ih; 76 struct evcnt sc_intrcnt; 77 uint8_t sc_mpr; 78 79 /* Details of the current DMA transfer */ 80 bool sc_dmaactive; 81 void * sc_dmaaddr; 82 int sc_dmaoff; 83 size_t sc_dmalen; 84 bool sc_dmain; 85 /* Details of the current block within the above transfer */ 86 size_t sc_dmablk; 87 }; 88 89 #define SEC_DMABLK 16384 90 #define SEC_NBLKS 3 91 #define SEC_DMAMODE MODE_TMODE_DMD 92 93 /* autoconfiguration glue */ 94 static int sec_match(device_t, cfdata_t, void *); 95 static void sec_attach(device_t, device_t, void *); 96 97 /* shutdown hook */ 98 static void sec_shutdown(void *); 99 100 /* callbacks from MI WD33C93 driver */ 101 static int sec_dmasetup(struct wd33c93_softc *, void **, size_t *, int, 102 size_t *); 103 static int sec_dmago(struct wd33c93_softc *); 104 static void sec_dmastop(struct wd33c93_softc *); 105 static void sec_reset(struct wd33c93_softc *); 106 107 static int sec_intr(void *); 108 static int sec_dmatc(struct sec_softc *sc); 109 110 void sec_dumpdma(void *arg); 111 112 CFATTACH_DECL_NEW(sec, sizeof(struct sec_softc), 113 sec_match, sec_attach, NULL, NULL); 114 115 static inline void 116 sec_setpage(struct sec_softc *sc, int page) 117 { 118 119 sc->sc_mpr = (sc->sc_mpr & ~SEC_MPR_PAGE) | page; 120 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr); 121 } 122 123 static inline void 124 sec_cli(struct sec_softc *sc) 125 { 126 127 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_CLRINT, 0); 128 } 129 130 static inline void 131 dmac_write(struct sec_softc *sc, int reg, uint8_t val) 132 { 133 134 bus_space_write_1(sc->sc_mod_t, sc->sc_mod_h, 135 SEC_DMAC + DMAC(reg), val); 136 } 137 138 static inline uint8_t 139 dmac_read(struct sec_softc *sc, int reg) 140 { 141 142 return bus_space_read_1(sc->sc_mod_t, sc->sc_mod_h, 143 SEC_DMAC + DMAC(reg)); 144 } 145 146 static int 147 sec_match(device_t parent, cfdata_t cf, void *aux) 148 { 149 struct podulebus_attach_args *pa = aux; 150 151 /* Standard ROM, skipping the MCS card that used the same ID. */ 152 if (pa->pa_product == PODULE_ACORN_SCSI && 153 strncmp(pa->pa_descr, "MCS", 3) != 0) 154 return 1; 155 156 /* PowerROM */ 157 if (pa->pa_product == PODULE_ALSYSTEMS_SCSI && 158 podulebus_initloader(pa) == 0 && 159 podloader_callloader(pa, 0, 0) == PRID_ACORN_SCSI1) 160 return 1; 161 162 return 0; 163 } 164 165 static void 166 sec_attach(device_t parent, device_t self, void *aux) 167 { 168 struct podulebus_attach_args *pa = aux; 169 struct sec_softc *sc = device_private(self); 170 int i; 171 172 sc->sc_sbic.sc_dev = self; 173 /* Set up bus spaces */ 174 sc->sc_pod_t = pa->pa_fast_t; 175 bus_space_map(pa->pa_fast_t, pa->pa_fast_base, 0x1000, 0, 176 &sc->sc_pod_h); 177 sc->sc_mod_t = pa->pa_mod_t; 178 bus_space_map(pa->pa_mod_t, pa->pa_mod_base, 0x1000, 0, 179 &sc->sc_mod_h); 180 181 sc->sc_sbic.sc_regt = sc->sc_mod_t; 182 bus_space_subregion(sc->sc_mod_t, sc->sc_mod_h, SEC_SBIC, 183 0x1000 - SEC_SBIC, &sc->sc_sbic.sc_regh); 184 185 sc->sc_sbic.sc_id = 7; 186 sc->sc_sbic.sc_clkfreq = SEC_CLKFREQ; 187 sc->sc_sbic.sc_dmamode = SBIC_CTL_BURST_DMA; 188 189 sc->sc_sbic.sc_adapter.adapt_request = wd33c93_scsi_request; 190 sc->sc_sbic.sc_adapter.adapt_minphys = minphys; 191 192 sc->sc_sbic.sc_dmasetup = sec_dmasetup; 193 sc->sc_sbic.sc_dmago = sec_dmago; 194 sc->sc_sbic.sc_dmastop = sec_dmastop; 195 sc->sc_sbic.sc_reset = sec_reset; 196 197 sc->sc_mpr = 0; 198 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr); 199 200 for (i = 0; i < SEC_NPAGES; i++) { 201 sec_setpage(sc, i); 202 bus_space_set_region_2(sc->sc_mod_t, sc->sc_mod_h, 203 SEC_SRAM, 0, SEC_PAGESIZE / 2); 204 } 205 206 wd33c93_attach(&sc->sc_sbic); 207 208 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 209 device_xname(self), "intr"); 210 sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, sec_intr, 211 sc, &sc->sc_intrcnt); 212 sec_cli(sc); 213 sc->sc_mpr |= SEC_MPR_IE; 214 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr); 215 shutdownhook_establish(sec_shutdown, sc); 216 } 217 218 /* 219 * Before reboot, reset the page register to 0 so that RISC OS can see 220 * the podule ROM. 221 */ 222 static void 223 sec_shutdown(void *cookie) 224 { 225 struct sec_softc *sc = cookie; 226 227 sec_setpage(sc, 0); 228 } 229 230 static void 231 sec_copyin(struct sec_softc *sc, void *dest, int src, size_t size) 232 { 233 uint16_t tmp, *wptr; 234 int cnt, extra_byte; 235 236 KASSERT(src >= 0); 237 KASSERT(src + size <= SEC_MEMSIZE); 238 if (src % 2 != 0) { 239 /* 240 * There's a stray byte at the start. Read the word 241 * containing it. 242 */ 243 sec_setpage(sc, src / SEC_PAGESIZE); 244 tmp = bus_space_read_2(sc->sc_mod_t, sc->sc_mod_h, 245 SEC_SRAM + (src % SEC_PAGESIZE / 2)); 246 *(uint8_t *)dest = tmp >> 8; 247 dest = ((uint8_t *)dest) + 1; 248 src++; size--; 249 } 250 KASSERT(src % 2 == 0); 251 KASSERT(ALIGNED_POINTER(dest, uint16_t)); 252 wptr = dest; 253 extra_byte = size % 2; 254 size -= extra_byte; 255 while (size > 0) { 256 cnt = SEC_PAGESIZE - src % SEC_PAGESIZE; 257 if (cnt > size) 258 cnt = size; 259 sec_setpage(sc, src / SEC_PAGESIZE); 260 /* bus ops are in words */ 261 bus_space_read_region_2(sc->sc_mod_t, sc->sc_mod_h, 262 SEC_SRAM + src % SEC_PAGESIZE / 2, wptr, cnt / 2); 263 src += cnt; 264 wptr += cnt / 2; 265 size -= cnt; 266 } 267 if (extra_byte) { 268 sec_setpage(sc, src / SEC_PAGESIZE); 269 *(u_int8_t *)wptr = 270 bus_space_read_2(sc->sc_mod_t, sc->sc_mod_h, 271 SEC_SRAM + src % SEC_PAGESIZE / 2) & 0xff; 272 } 273 } 274 275 static void 276 sec_copyout(struct sec_softc *sc, const void *src, int dest, size_t size) 277 { 278 int cnt, extra_byte; 279 const uint16_t *wptr; 280 uint16_t tmp; 281 282 KASSERT(dest >= 0); 283 KASSERT(dest + size <= SEC_MEMSIZE); 284 if (dest % 2 != 0) { 285 /* 286 * There's a stray byte at the start. Read the word 287 * containing it. 288 */ 289 sec_setpage(sc, dest / SEC_PAGESIZE); 290 tmp = bus_space_read_2(sc->sc_mod_t, sc->sc_mod_h, 291 SEC_SRAM + (dest % SEC_PAGESIZE / 2)); 292 tmp &= 0xff; 293 tmp |= *(uint8_t const *)src << 8; 294 bus_space_write_2(sc->sc_mod_t, sc->sc_mod_h, 295 SEC_SRAM + (dest % SEC_PAGESIZE / 2), tmp); 296 src = ((uint8_t const *)src) + 1; 297 dest++; size--; 298 } 299 KASSERT(dest % 2 == 0); 300 KASSERT(ALIGNED_POINTER(src, uint16_t)); 301 wptr = src; 302 extra_byte = size % 2; 303 size -= extra_byte; 304 while (size > 0) { 305 cnt = SEC_PAGESIZE - dest % SEC_PAGESIZE; 306 if (cnt > size) 307 cnt = size; 308 sec_setpage(sc, dest / SEC_PAGESIZE); 309 /* bus ops are in words */ 310 bus_space_write_region_2(sc->sc_mod_t, sc->sc_mod_h, 311 dest % SEC_PAGESIZE / 2, wptr, cnt / 2); 312 wptr += cnt / 2; 313 dest += cnt; 314 size -= cnt; 315 } 316 if (extra_byte) { 317 /* 318 * There's a stray byte at the end. Read the word 319 * containing it. 320 */ 321 sec_setpage(sc, dest / SEC_PAGESIZE); 322 tmp = bus_space_read_2(sc->sc_mod_t, sc->sc_mod_h, 323 SEC_SRAM + (dest % SEC_PAGESIZE / 2)); 324 tmp &= 0xff00; 325 tmp |= *(uint8_t const *)wptr; 326 bus_space_write_2(sc->sc_mod_t, sc->sc_mod_h, 327 SEC_SRAM + (dest % SEC_PAGESIZE / 2), tmp); 328 } 329 } 330 331 static void 332 sec_dmablk(struct sec_softc *sc, int blk) 333 { 334 int off; 335 size_t len; 336 337 KASSERT(blk >= 0); 338 KASSERT(blk * SEC_DMABLK < sc->sc_dmalen); 339 off = (blk % SEC_NBLKS) * SEC_DMABLK + sc->sc_dmaoff; 340 len = MIN(SEC_DMABLK, sc->sc_dmalen - (blk * SEC_DMABLK)); 341 dmac_write(sc, NEC71071_ADDRLO, off & 0xff); 342 dmac_write(sc, NEC71071_ADDRMID, off >> 8); 343 dmac_write(sc, NEC71071_ADDRHI, 0); 344 /* 345 * "Note: The number of DMA transfer cycles is actually the 346 * value of the current count register + 1. Therefore, when 347 * programming the count register, specify the number of DMA 348 * transfers minus one." -- uPD71071 datasheet 349 */ 350 dmac_write(sc, NEC71071_COUNTLO, (len - 1) & 0xff); 351 dmac_write(sc, NEC71071_COUNTHI, (len - 1) >> 8); 352 } 353 354 static void 355 sec_copyoutblk(struct sec_softc *sc, int blk) 356 { 357 int off; 358 size_t len; 359 360 KASSERT(blk >= 0); 361 KASSERT(blk * SEC_DMABLK < sc->sc_dmalen); 362 KASSERT(!sc->sc_dmain); 363 off = (blk % SEC_NBLKS) * SEC_DMABLK + sc->sc_dmaoff; 364 len = MIN(SEC_DMABLK, sc->sc_dmalen - (blk * SEC_DMABLK)); 365 sec_copyout(sc, (char*)sc->sc_dmaaddr + (blk * SEC_DMABLK), off, len); 366 } 367 368 static void 369 sec_copyinblk(struct sec_softc *sc, int blk) 370 { 371 int off; 372 size_t len; 373 374 KASSERT(blk >= 0); 375 KASSERT(blk * SEC_DMABLK < sc->sc_dmalen); 376 KASSERT(sc->sc_dmain); 377 off = (blk % SEC_NBLKS) * SEC_DMABLK + sc->sc_dmaoff; 378 len = MIN(SEC_DMABLK, sc->sc_dmalen - (blk * SEC_DMABLK)); 379 sec_copyin(sc, (char*)sc->sc_dmaaddr + (blk * SEC_DMABLK), off, len); 380 } 381 382 static int 383 sec_dmasetup(struct wd33c93_softc *sc_sbic, void **addr, size_t *len, 384 int datain, size_t *dmasize) 385 { 386 struct sec_softc *sc = (struct sec_softc *)sc_sbic; 387 uint8_t mode; 388 389 sc->sc_dmaaddr = *addr; 390 sc->sc_dmaoff = ALIGNED_POINTER(*addr, uint16_t) ? 0 : 1; 391 sc->sc_dmalen = *len; 392 sc->sc_dmain = datain; 393 sc->sc_dmablk = 0; 394 mode = SEC_DMAMODE | (datain ? MODE_TDIR_IOTM : MODE_TDIR_MTIO); 395 /* Program first block into DMAC and queue up second. */ 396 dmac_write(sc, NEC71071_CHANNEL, 0); 397 if (!sc->sc_dmain) 398 sec_copyoutblk(sc, 0); 399 sec_dmablk(sc, 0); 400 /* Mode control register */ 401 dmac_write(sc, NEC71071_MODE, mode); 402 return sc->sc_dmalen; 403 } 404 405 static int 406 sec_dmago(struct wd33c93_softc *sc_sbic) 407 { 408 struct sec_softc *sc = (struct sec_softc *)sc_sbic; 409 410 dmac_write(sc, NEC71071_MASK, 0xe); 411 sc->sc_dmaactive = true; 412 if (!sc->sc_dmain && sc->sc_dmalen > SEC_DMABLK) 413 sec_copyoutblk(sc, 1); 414 return sc->sc_dmalen; 415 } 416 417 static void 418 sec_dmastop(struct wd33c93_softc *sc_sbic) 419 { 420 struct sec_softc *sc = (struct sec_softc *)sc_sbic; 421 422 dmac_write(sc, NEC71071_MASK, 0xf); 423 if (sc->sc_dmaactive && sc->sc_dmain) 424 sec_copyinblk(sc, sc->sc_dmablk); 425 sc->sc_dmaactive = false; 426 } 427 428 /* 429 * Reset the SCSI bus, and incidentally the SBIC and DMAC. 430 */ 431 static void 432 sec_reset(struct wd33c93_softc *sc_sbic) 433 { 434 struct sec_softc *sc = (struct sec_softc *)sc_sbic; 435 uint8_t asr, csr; 436 437 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, 438 sc->sc_mpr | SEC_MPR_UR); 439 DELAY(7); 440 bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr); 441 /* Wait for and clear the reset-complete interrupt */ 442 do 443 GET_SBIC_asr(sc_sbic, asr); 444 while (!(asr & SBIC_ASR_INT)); 445 GET_SBIC_csr(sc_sbic, csr); 446 dmac_write(sc, NEC71071_DCTRL1, DCTRL1_CMP | DCTRL1_RQL); 447 dmac_write(sc, NEC71071_DCTRL2, 0); 448 sec_cli(sc); 449 } 450 451 static int 452 sec_intr(void *arg) 453 { 454 struct sec_softc *sc = arg; 455 u_int8_t isr; 456 457 isr = bus_space_read_1(sc->sc_pod_t, sc->sc_pod_h, SEC_ISR); 458 if (!(isr & SEC_ISR_IRQ)) 459 return 0; 460 if (isr & SEC_ISR_DMAC) 461 sec_dmatc(sc); 462 if (isr & SEC_ISR_SBIC) 463 wd33c93_intr(&sc->sc_sbic); 464 return 1; 465 } 466 467 static int 468 sec_dmatc(struct sec_softc *sc) 469 { 470 471 sec_cli(sc); 472 /* DMAC finished block n-1 and is now working on block n */ 473 sc->sc_dmablk++; 474 if (sc->sc_dmalen > sc->sc_dmablk * SEC_DMABLK) { 475 dmac_write(sc, NEC71071_CHANNEL, 0); 476 sec_dmablk(sc, sc->sc_dmablk); 477 dmac_write(sc, NEC71071_MASK, 0xe); 478 if (!sc->sc_dmain && 479 sc->sc_dmalen > (sc->sc_dmablk + 1) * SEC_DMABLK) 480 sec_copyoutblk(sc, sc->sc_dmablk + 1); 481 } else { 482 /* All blocks fully processed. */ 483 sc->sc_dmaactive = false; 484 } 485 if (sc->sc_dmain) 486 sec_copyinblk(sc, sc->sc_dmablk - 1); 487 return 1; 488 } 489 490 #ifdef DDB 491 void 492 sec_dumpdma(void *arg) 493 { 494 struct sec_softc *sc = arg; 495 496 dmac_write(sc, NEC71071_CHANNEL, 0); 497 printf("%s: DMA state: cur count %02x%02x cur addr %02x%02x%02x ", 498 device_xname(sc->sc_sbic.sc_dev), 499 dmac_read(sc, NEC71071_COUNTHI), dmac_read(sc, NEC71071_COUNTLO), 500 dmac_read(sc, NEC71071_ADDRHI), dmac_read(sc, NEC71071_ADDRMID), 501 dmac_read(sc, NEC71071_ADDRLO)); 502 dmac_write(sc, NEC71071_CHANNEL, 0 | CHANNEL_WBASE); 503 printf("base count %02x%02x base addr %02x%02x%02x\n", 504 dmac_read(sc, NEC71071_COUNTHI), dmac_read(sc, NEC71071_COUNTLO), 505 dmac_read(sc, NEC71071_ADDRHI), dmac_read(sc, NEC71071_ADDRMID), 506 dmac_read(sc, NEC71071_ADDRLO)); 507 printf("%s: DMA state: dctrl %1x%02x mode %02x status %02x req %02x " 508 "mask %02x\n", 509 device_xname(sc->sc_sbic.sc_dev), dmac_read(sc, NEC71071_DCTRL2), 510 dmac_read(sc, NEC71071_DCTRL1), dmac_read(sc, NEC71071_MODE), 511 dmac_read(sc, NEC71071_STATUS), dmac_read(sc, NEC71071_REQUEST), 512 dmac_read(sc, NEC71071_MASK)); 513 printf("%s: soft DMA state: %zd@%p%s%d\n", 514 device_xname(sc->sc_sbic.sc_dev), 515 sc->sc_dmalen, sc->sc_dmaaddr, sc->sc_dmain ? "<-" : "->", 516 sc->sc_dmaoff); 517 } 518 519 void sec_dumpall(void); /* Call from DDB */ 520 521 extern struct cfdriver sec_cd; 522 523 void sec_dumpall(void) 524 { 525 int i; 526 struct sec_softc *sc; 527 528 for (i = 0; i < sec_cd.cd_ndevs; ++i) { 529 sc = device_lookup_private(&sec_cd, i); 530 if (sc != NULL) 531 sec_dumpdma(sc); 532 } 533 } 534 #endif 535
Indexes created Tue Sep 23 07:09:52 GMT 2025