if_qtreg.h revision 1.1
1 /* $NetBSD: if_qtreg.h,v 1.1 2003/08/28 10:03:32 ragge Exp $ */ 2 /* 3 * Copyright (c) 1992 Steven M. Schultz 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * @(#)if_qtreg.h 1.0 (GTE) 10/12/92 29 */ 30 /* 31 * Modification History 32 * 26 Feb 93 -- sms 33 * Add defines for number of receive and transmit ring descriptors. 34 * 35 * 12 Oct 92 -- Steven M. Schultz (sms) 36 * Created from the DELQA-PLUS Addendum to the DELQA User's Guide. 37 */ 38 39 #define QT_MAX_RCV 32 40 #define QT_MAX_XMT 12 41 42 /* Receive ring descriptor and bit/field definitions */ 43 44 struct qt_rring 45 { 46 short rmd0; 47 short rmd1; 48 short rmd2; 49 short rmd3; 50 short rmd4; 51 short rmd5; 52 struct qt_uba *rhost0; 53 short rhost1; 54 }; 55 56 #define RMD0_ERR3 0x4000 /* Error summary. FRA|CRC|OFL|BUF */ 57 #define RMD0_FRA 0x2000 /* Framing error */ 58 #define RMD0_OFL 0x1000 /* Overflow error. Oversized packet */ 59 #define RMD0_CRC 0x0800 /* CRC error */ 60 #define RMD0_BUF 0x0400 /* Internal device buffer error */ 61 #define RMD0_STP 0x0200 /* Start of packet */ 62 #define RMD0_ENP 0x0100 /* End of packet */ 63 64 #define RMD1_MCNT 0x0fff /* Message byte count */ 65 66 #define RMD2_ERR4 0x8000 /* Error summary. BBL|CER|MIS */ 67 #define RMD2_BBL 0x4000 /* Babble error on transmit */ 68 #define RMD2_CER 0x2000 /* Collision error on transmit */ 69 #define RMD2_MIS 0x1000 /* Packet lost on receive */ 70 #define RMD2_EOR 0x0800 /* End of receive ring */ 71 #define RMD2_RON 0x0020 /* Receiver on */ 72 #define RMD2_TON 0x0010 /* Transmitter on */ 73 74 #define RMD3_OWN 0x8000 /* Ownership field. */ 75 76 #define RMD4_LADR 0xfff8 /* Octabyte aligned low address bits */ 77 78 #define RMD5_HADR 0x003f /* High 6 bits of buffer address */ 79 80 #define RMD0_BITS "\010\016FRA\015OFL\014CRC\013BUF\012STP\011ENP" 81 #define RMD2_BITS "\010\017BBL\014CER\013MIS\012EOR\06RON\05TON" 82 83 /* Transmit ring descriptor and bit/field definitions */ 84 85 struct qt_tring 86 { 87 short tmd0; 88 short tmd1; 89 short tmd2; 90 short tmd3; 91 short tmd4; 92 short tmd5; 93 struct qt_uba *thost0; 94 short thost1; 95 }; 96 97 #define TMD0_ERR1 0x4000 /* Error summary. LCO|LCA|RTR */ 98 #define TMD0_MOR 0x1000 /* More than one retry on transmit */ 99 #define TMD0_ONE 0x0800 /* One retry on transmit */ 100 #define TMD0_DEF 0x0400 /* Deferral during transmit */ 101 102 #define TMD1_LCO 0x1000 /* Late collision on transmit */ 103 #define TMD1_LCA 0x0800 /* Loss of carrier on transmit */ 104 #define TMD1_RTR 0x0400 /* Retry error on transmit */ 105 #define TMD1_TDR 0x03ff /* Time Domain Reflectometry value */ 106 107 #define TMD2_ERR2 0x8000 /* Error summary. BBL|CER|MIS */ 108 #define TMD2_BBL 0x4000 /* Babble error on transmit */ 109 #define TMD2_CER 0x2000 /* Collision error on transmit */ 110 #define TMD2_MIS 0x1000 /* Packet lost on receive */ 111 #define TMD2_EOR 0x0800 /* Endof Receive ring reached */ 112 #define TMD2_RON 0x0020 /* Receiver on */ 113 #define TMD2_TON 0x0010 /* Transmitter on */ 114 115 #define TMD3_OWN 0x8000 /* Ownership field */ 116 #define TMD3_FOT 0x4000 /* First of two flag */ 117 #define TMD3_BCT 0x0fff /* Byte count */ 118 119 #define TMD4_LADR 0xfff8 /* Octabyte aligned low address bits */ 120 121 #define TMD5_HADR 0x003f /* High 6 bits of buffer address */ 122 123 #define TMD1_BITS "\010\015LCO\014LCA\013RTR" 124 #define TMD2_BITS "\010\017BBL\016CER\015MIS\014EOR\06RON\05TON" 125 126 /* DELQA-YM CSR layout */ 127 128 struct qtcsr0 129 { 130 short Ibal; 131 short Ibah; 132 short Icr; 133 short pad0; 134 short Srqr; 135 short pad1; 136 }; 137 138 struct qtdevice 139 { 140 union { 141 u_char Sarom[12]; 142 struct qtcsr0 csr0; 143 } qt_un0; 144 short srr; 145 short arqr; 146 }; 147 148 #define ibal qt_un0.csr0.Ibal 149 #define ibah qt_un0.csr0.Ibah 150 #define srqr qt_un0.csr0.Srqr 151 #define icr qt_un0.csr0.Icr 152 #define sarom qt_un0.Sarom 153 154 /* SRR definitions */ 155 156 #define SRR_FES 0x8000 157 #define SRR_CHN 0x4000 158 #define SRR_NXM 0x1000 159 #define SRR_PER 0x0800 160 #define SRR_IME 0x0400 161 #define SRR_TBL 0x0200 162 #define SRR_RESP 0x0003 163 #define SRR_BITS "\010\017CHN\015NXM\014PER\013IME\012TBL" 164 165 /* SRQR definitions */ 166 167 #define SRQR_REQ 0x0003 168 169 /* ARQR definitions */ 170 171 #define ARQR_TRQ 0x8000 172 #define ARQR_RRQ 0x0080 173 #define ARQR_SR 0x0002 174 175 /* define ICR definitions */ 176 177 #define ICR_CMD 0x0001 178 179 /* DELQA registers used to shift into -T mode */ 180 181 #define xcr0 qt_un0.csr0.Ibal 182 #define xcr1 qt_un0.csr0.Ibah 183 184 /* INIT block structure and definitions */ 185 186 struct qt_init 187 { 188 short mode; 189 u_char paddr[6]; /* 48 bit physical address */ 190 u_char laddr[8]; /* 64 bit logical address filter */ 191 u_short rx_lo; /* low 16 bits of receive ring addr */ 192 u_short rx_hi; /* high 6 bits of receive ring addr */ 193 u_short tx_lo; /* low 16 bits of transmit ring addr */ 194 u_short tx_hi; /* high 6 bits of transmit ring addr */ 195 u_short options; 196 u_short vector; 197 u_short hit; 198 char passwd[6]; 199 }; 200 201 #define INIT_MODE_PRO 0x8000 /* Promiscuous mode */ 202 #define INIT_MODE_INT 0x0040 /* Internal Loopback */ 203 #define INIT_MODE_DRT 0x0020 /* Disable Retry */ 204 #define INIT_MODE_DTC 0x0008 /* Disable Transmit CRC */ 205 #define INIT_MODE_LOP 0x0004 /* Loopback */ 206 207 #define INIT_OPTIONS_HIT 0x0002 /* Host Inactivity Timeout Flag */ 208 #define INIT_OPTIONS_INT 0x0001 /* Interrupt Enable Flag */ 209
Indexes created Mon Sep 29 21:09:56 GMT 2025