qec.c revision 1.10
1 /* $NetBSD: qec.c,v 1.10 2000/01/11 12:59:44 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <machine/bus.h> 48 #include <machine/autoconf.h> 49 50 #include <dev/sbus/sbusvar.h> 51 #include <dev/sbus/qecreg.h> 52 #include <dev/sbus/qecvar.h> 53 54 static int qecprint __P((void *, const char *)); 55 static int qecmatch __P((struct device *, struct cfdata *, void *)); 56 static void qecattach __P((struct device *, struct device *, void *)); 57 void qec_init __P((struct qec_softc *)); 58 59 static int qec_bus_map __P(( 60 bus_space_tag_t, 61 bus_type_t, /*slot*/ 62 bus_addr_t, /*offset*/ 63 bus_size_t, /*size*/ 64 int, /*flags*/ 65 vaddr_t, /*preferred virtual address */ 66 bus_space_handle_t *)); 67 static void *qec_intr_establish __P(( 68 bus_space_tag_t, 69 int, /*level*/ 70 int, /*flags*/ 71 int (*) __P((void *)), /*handler*/ 72 void *)); /*arg*/ 73 74 struct cfattach qec_ca = { 75 sizeof(struct qec_softc), qecmatch, qecattach 76 }; 77 78 int 79 qecprint(aux, busname) 80 void *aux; 81 const char *busname; 82 { 83 struct sbus_attach_args *sa = aux; 84 bus_space_tag_t t = sa->sa_bustag; 85 struct qec_softc *sc = t->cookie; 86 87 sa->sa_bustag = sc->sc_bustag; /* XXX */ 88 sbus_print(aux, busname); /* XXX */ 89 sa->sa_bustag = t; /* XXX */ 90 return (UNCONF); 91 } 92 93 int 94 qecmatch(parent, cf, aux) 95 struct device *parent; 96 struct cfdata *cf; 97 void *aux; 98 { 99 struct sbus_attach_args *sa = aux; 100 101 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 102 } 103 104 /* 105 * Attach all the sub-devices we can find 106 */ 107 void 108 qecattach(parent, self, aux) 109 struct device *parent, *self; 110 void *aux; 111 { 112 struct sbus_attach_args *sa = aux; 113 struct qec_softc *sc = (void *)self; 114 int node; 115 int sbusburst; 116 bus_space_tag_t sbt; 117 bus_space_handle_t bh; 118 int error; 119 120 sc->sc_bustag = sa->sa_bustag; 121 sc->sc_dmatag = sa->sa_dmatag; 122 node = sa->sa_node; 123 124 if (sa->sa_nreg < 2) { 125 printf("%s: only %d register sets\n", 126 self->dv_xname, sa->sa_nreg); 127 return; 128 } 129 130 if (sbus_bus_map(sa->sa_bustag, 131 sa->sa_reg[0].sbr_slot, 132 sa->sa_reg[0].sbr_offset, 133 sa->sa_reg[0].sbr_size, 134 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_regs) != 0) { 135 printf("%s: attach: cannot map registers\n", self->dv_xname); 136 return; 137 } 138 139 /* 140 * This device's "register space 1" is just a buffer where the 141 * Lance ring-buffers can be stored. Note the buffer's location 142 * and size, so the child driver can pick them up. 143 */ 144 if (sbus_bus_map(sa->sa_bustag, 145 sa->sa_reg[1].sbr_slot, 146 sa->sa_reg[1].sbr_offset, 147 sa->sa_reg[1].sbr_size, 148 BUS_SPACE_MAP_LINEAR, 0, &bh) != 0) { 149 printf("%s: attach: cannot map registers\n", self->dv_xname); 150 return; 151 } 152 sc->sc_buffer = (caddr_t)bh; 153 sc->sc_bufsiz = (bus_size_t)sa->sa_reg[1].sbr_size; 154 155 /* Get number of on-board channels */ 156 sc->sc_nchannels = getpropint(node, "#channels", -1); 157 if (sc->sc_nchannels == -1) { 158 printf(": no channels\n"); 159 return; 160 } 161 162 /* 163 * Get transfer burst size from PROM 164 */ 165 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 166 if (sbusburst == 0) 167 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 168 169 sc->sc_burst = getpropint(node, "burst-sizes", -1); 170 if (sc->sc_burst == -1) 171 /* take SBus burst sizes */ 172 sc->sc_burst = sbusburst; 173 174 /* Clamp at parent's burst sizes */ 175 sc->sc_burst &= sbusburst; 176 177 sbus_establish(&sc->sc_sd, &sc->sc_dev); 178 179 /* 180 * Collect address translations from the OBP. 181 */ 182 error = getprop(node, "ranges", sizeof(struct sbus_range), 183 &sc->sc_nrange, (void **)&sc->sc_range); 184 switch (error) { 185 case 0: 186 break; 187 case ENOENT: 188 default: 189 panic("%s: error getting ranges property", self->dv_xname); 190 } 191 192 /* Allocate a bus tag */ 193 sbt = (bus_space_tag_t) 194 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 195 if (sbt == NULL) { 196 printf("%s: attach: out of memory\n", self->dv_xname); 197 return; 198 } 199 200 bzero(sbt, sizeof *sbt); 201 sbt->cookie = sc; 202 sbt->parent = sc->sc_bustag; 203 sbt->sparc_bus_map = qec_bus_map; 204 sbt->sparc_intr_establish = qec_intr_establish; 205 206 /* 207 * Save interrupt information for use in our qec_intr_establish() 208 * function below. Apparently, the intr level for the quad 209 * ethernet board (qe) is stored in the QEC node rather then 210 * separately in each of the QE nodes. 211 * 212 * XXX - qe.c should call bus_intr_establish() with `level = 0'.. 213 * XXX - maybe we should have our own attach args for all that. 214 */ 215 sc->sc_intr = sa->sa_intr; 216 217 printf(": %dK memory\n", sc->sc_bufsiz / 1024); 218 219 qec_init(sc); 220 221 /* search through children */ 222 for (node = firstchild(node); node; node = nextsibling(node)) { 223 struct sbus_attach_args sa; 224 sbus_setup_attach_args((struct sbus_softc *)parent, 225 sbt, sc->sc_dmatag, node, &sa); 226 (void)config_found(&sc->sc_dev, (void *)&sa, qecprint); 227 sbus_destroy_attach_args(&sa); 228 } 229 } 230 231 int 232 qec_bus_map(t, btype, offset, size, flags, vaddr, hp) 233 bus_space_tag_t t; 234 bus_type_t btype; 235 bus_addr_t offset; 236 bus_size_t size; 237 int flags; 238 vaddr_t vaddr; 239 bus_space_handle_t *hp; 240 { 241 struct qec_softc *sc = t->cookie; 242 int slot = btype; 243 int i; 244 245 for (i = 0; i < sc->sc_nrange; i++) { 246 bus_addr_t paddr; 247 bus_type_t iospace; 248 249 if (sc->sc_range[i].cspace != slot) 250 continue; 251 252 /* We've found the connection to the parent bus */ 253 paddr = sc->sc_range[i].poffset + offset; 254 iospace = sc->sc_range[i].pspace; 255 return (bus_space_map2(sc->sc_bustag, iospace, paddr, 256 size, flags, vaddr, hp)); 257 } 258 259 return (EINVAL); 260 } 261 262 void * 263 qec_intr_establish(t, level, flags, handler, arg) 264 bus_space_tag_t t; 265 int level; 266 int flags; 267 int (*handler) __P((void *)); 268 void *arg; 269 { 270 struct qec_softc *sc = t->cookie; 271 272 if (level == 0) { 273 /* 274 * qe.c calls bus_intr_establish() with `level = 0' 275 * XXX - see also comment in qec_attach(). 276 */ 277 if (sc->sc_intr == NULL) { 278 printf("%s: warning: no interrupts\n", 279 sc->sc_dev.dv_xname); 280 return (NULL); 281 } 282 level = sc->sc_intr->sbi_pri; 283 } 284 285 return (bus_intr_establish(t->parent, level, flags, handler, arg)); 286 } 287 288 void 289 qec_init(sc) 290 struct qec_softc *sc; 291 { 292 bus_space_tag_t t = sc->sc_bustag; 293 bus_space_handle_t qr = sc->sc_regs; 294 u_int32_t v, burst = 0, psize; 295 int i; 296 297 /* First, reset the controller */ 298 bus_space_write_4(t, qr, QEC_QRI_CTRL, QEC_CTRL_RESET); 299 for (i = 0; i < 1000; i++) { 300 DELAY(100); 301 v = bus_space_read_4(t, qr, QEC_QRI_CTRL); 302 if ((v & QEC_CTRL_RESET) == 0) 303 break; 304 } 305 306 /* 307 * Cut available buffer size into receive and transmit buffers. 308 * XXX - should probably be done in be & qe driver... 309 */ 310 v = sc->sc_msize = sc->sc_bufsiz / sc->sc_nchannels; 311 bus_space_write_4(t, qr, QEC_QRI_MSIZE, v); 312 313 v = sc->sc_rsize = sc->sc_bufsiz / (sc->sc_nchannels * 2); 314 bus_space_write_4(t, qr, QEC_QRI_RSIZE, v); 315 bus_space_write_4(t, qr, QEC_QRI_TSIZE, v); 316 317 psize = sc->sc_nchannels == 1 ? QEC_PSIZE_2048 : 0; 318 bus_space_write_4(t, qr, QEC_QRI_PSIZE, psize); 319 320 if (sc->sc_burst & SBUS_BURST_64) 321 burst = QEC_CTRL_B64; 322 else if (sc->sc_burst & SBUS_BURST_32) 323 burst = QEC_CTRL_B32; 324 else 325 burst = QEC_CTRL_B16; 326 327 v = bus_space_read_4(t, qr, QEC_QRI_CTRL); 328 v = (v & QEC_CTRL_MODEMASK) | burst; 329 bus_space_write_4(t, qr, QEC_QRI_CTRL, v); 330 } 331 332 /* 333 * Common routine to initialize the QEC packet ring buffer. 334 * Called from be & qe drivers. 335 */ 336 void 337 qec_meminit(qr, pktbufsz) 338 struct qec_ring *qr; 339 unsigned int pktbufsz; 340 { 341 bus_addr_t txbufdma, rxbufdma; 342 bus_addr_t dma; 343 caddr_t p; 344 unsigned int ntbuf, nrbuf, i; 345 346 p = qr->rb_membase; 347 dma = qr->rb_dmabase; 348 349 ntbuf = qr->rb_ntbuf; 350 nrbuf = qr->rb_nrbuf; 351 352 /* 353 * Allocate transmit descriptors 354 */ 355 qr->rb_txd = (struct qec_xd *)p; 356 qr->rb_txddma = dma; 357 p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 358 dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 359 360 /* 361 * Allocate receive descriptors 362 */ 363 qr->rb_rxd = (struct qec_xd *)p; 364 qr->rb_rxddma = dma; 365 p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 366 dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 367 368 369 /* 370 * Allocate transmit buffers 371 */ 372 qr->rb_txbuf = p; 373 txbufdma = dma; 374 p += ntbuf * pktbufsz; 375 dma += ntbuf * pktbufsz; 376 377 /* 378 * Allocate receive buffers 379 */ 380 qr->rb_rxbuf = p; 381 rxbufdma = dma; 382 p += nrbuf * pktbufsz; 383 dma += nrbuf * pktbufsz; 384 385 /* 386 * Initialize transmit buffer descriptors 387 */ 388 for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) { 389 qr->rb_txd[i].xd_addr = (u_int32_t) 390 (txbufdma + (i % ntbuf) * pktbufsz); 391 qr->rb_txd[i].xd_flags = 0; 392 } 393 394 /* 395 * Initialize receive buffer descriptors 396 */ 397 for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) { 398 qr->rb_rxd[i].xd_addr = (u_int32_t) 399 (rxbufdma + (i % nrbuf) * pktbufsz); 400 qr->rb_rxd[i].xd_flags = (i < nrbuf) 401 ? QEC_XD_OWN | (pktbufsz & QEC_XD_LENGTH) 402 : 0; 403 } 404 405 qr->rb_tdhead = qr->rb_tdtail = 0; 406 qr->rb_td_nbusy = 0; 407 qr->rb_rdtail = 0; 408 } 409
Indexes created Fri Sep 26 20:09:58 GMT 2025