qec.c revision 1.13
1 /* $NetBSD: qec.c,v 1.13 2001/09/26 20:53:15 eeh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 #include <machine/autoconf.h> 50 51 #include <dev/sbus/sbusvar.h> 52 #include <dev/sbus/qecreg.h> 53 #include <dev/sbus/qecvar.h> 54 55 static int qecprint __P((void *, const char *)); 56 static int qecmatch __P((struct device *, struct cfdata *, void *)); 57 static void qecattach __P((struct device *, struct device *, void *)); 58 void qec_init __P((struct qec_softc *)); 59 60 static int qec_bus_map __P(( 61 bus_space_tag_t, 62 bus_type_t, /*slot*/ 63 bus_addr_t, /*offset*/ 64 bus_size_t, /*size*/ 65 int, /*flags*/ 66 vaddr_t, /*preferred virtual address */ 67 bus_space_handle_t *)); 68 static void *qec_intr_establish __P(( 69 bus_space_tag_t, 70 int, /*bus interrupt priority*/ 71 int, /*`device class' interrupt level*/ 72 int, /*flags*/ 73 int (*) __P((void *)), /*handler*/ 74 void *)); /*arg*/ 75 76 struct cfattach qec_ca = { 77 sizeof(struct qec_softc), qecmatch, qecattach 78 }; 79 80 int 81 qecprint(aux, busname) 82 void *aux; 83 const char *busname; 84 { 85 struct sbus_attach_args *sa = aux; 86 bus_space_tag_t t = sa->sa_bustag; 87 struct qec_softc *sc = t->cookie; 88 89 sa->sa_bustag = sc->sc_bustag; /* XXX */ 90 sbus_print(aux, busname); /* XXX */ 91 sa->sa_bustag = t; /* XXX */ 92 return (UNCONF); 93 } 94 95 int 96 qecmatch(parent, cf, aux) 97 struct device *parent; 98 struct cfdata *cf; 99 void *aux; 100 { 101 struct sbus_attach_args *sa = aux; 102 103 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 104 } 105 106 /* 107 * Attach all the sub-devices we can find 108 */ 109 void 110 qecattach(parent, self, aux) 111 struct device *parent, *self; 112 void *aux; 113 { 114 struct sbus_attach_args *sa = aux; 115 struct qec_softc *sc = (void *)self; 116 int node; 117 int sbusburst; 118 bus_space_tag_t sbt; 119 bus_space_handle_t bh; 120 int error; 121 122 sc->sc_bustag = sa->sa_bustag; 123 sc->sc_dmatag = sa->sa_dmatag; 124 node = sa->sa_node; 125 126 if (sa->sa_nreg < 2) { 127 printf("%s: only %d register sets\n", 128 self->dv_xname, sa->sa_nreg); 129 return; 130 } 131 132 if (sbus_bus_map(sa->sa_bustag, 133 sa->sa_reg[0].sbr_slot, 134 sa->sa_reg[0].sbr_offset, 135 sa->sa_reg[0].sbr_size, 136 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_regs) != 0) { 137 printf("%s: attach: cannot map registers\n", self->dv_xname); 138 return; 139 } 140 141 /* 142 * This device's "register space 1" is just a buffer where the 143 * Lance ring-buffers can be stored. Note the buffer's location 144 * and size, so the child driver can pick them up. 145 */ 146 if (sbus_bus_map(sa->sa_bustag, 147 sa->sa_reg[1].sbr_slot, 148 sa->sa_reg[1].sbr_offset, 149 sa->sa_reg[1].sbr_size, 150 BUS_SPACE_MAP_LINEAR, 0, &bh) != 0) { 151 printf("%s: attach: cannot map registers\n", self->dv_xname); 152 return; 153 } 154 sc->sc_buffer = (caddr_t)(u_long)bh; 155 sc->sc_bufsiz = (bus_size_t)sa->sa_reg[1].sbr_size; 156 157 /* Get number of on-board channels */ 158 sc->sc_nchannels = PROM_getpropint(node, "#channels", -1); 159 if (sc->sc_nchannels == -1) { 160 printf(": no channels\n"); 161 return; 162 } 163 164 /* 165 * Get transfer burst size from PROM 166 */ 167 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 168 if (sbusburst == 0) 169 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 170 171 sc->sc_burst = PROM_getpropint(node, "burst-sizes", -1); 172 if (sc->sc_burst == -1) 173 /* take SBus burst sizes */ 174 sc->sc_burst = sbusburst; 175 176 /* Clamp at parent's burst sizes */ 177 sc->sc_burst &= sbusburst; 178 179 sbus_establish(&sc->sc_sd, &sc->sc_dev); 180 181 /* 182 * Collect address translations from the OBP. 183 */ 184 error = PROM_getprop(node, "ranges", sizeof(struct sbus_range), 185 &sc->sc_nrange, (void **)&sc->sc_range); 186 switch (error) { 187 case 0: 188 break; 189 case ENOENT: 190 default: 191 panic("%s: error getting ranges property", self->dv_xname); 192 } 193 194 /* Allocate a bus tag */ 195 sbt = (bus_space_tag_t) 196 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 197 if (sbt == NULL) { 198 printf("%s: attach: out of memory\n", self->dv_xname); 199 return; 200 } 201 202 bzero(sbt, sizeof *sbt); 203 sbt->cookie = sc; 204 sbt->parent = sc->sc_bustag; 205 sbt->sparc_bus_map = qec_bus_map; 206 sbt->sparc_intr_establish = qec_intr_establish; 207 208 /* 209 * Save interrupt information for use in our qec_intr_establish() 210 * function below. Apparently, the intr level for the quad 211 * ethernet board (qe) is stored in the QEC node rather then 212 * separately in each of the QE nodes. 213 * 214 * XXX - qe.c should call bus_intr_establish() with `level = 0'.. 215 * XXX - maybe we should have our own attach args for all that. 216 */ 217 sc->sc_intr = sa->sa_intr; 218 219 printf(": %dK memory\n", sc->sc_bufsiz / 1024); 220 221 qec_init(sc); 222 223 /* search through children */ 224 for (node = firstchild(node); node; node = nextsibling(node)) { 225 struct sbus_attach_args sa; 226 sbus_setup_attach_args((struct sbus_softc *)parent, 227 sbt, sc->sc_dmatag, node, &sa); 228 (void)config_found(&sc->sc_dev, (void *)&sa, qecprint); 229 sbus_destroy_attach_args(&sa); 230 } 231 } 232 233 int 234 qec_bus_map(t, btype, offset, size, flags, vaddr, hp) 235 bus_space_tag_t t; 236 bus_type_t btype; 237 bus_addr_t offset; 238 bus_size_t size; 239 int flags; 240 vaddr_t vaddr; 241 bus_space_handle_t *hp; 242 { 243 struct qec_softc *sc = t->cookie; 244 int slot = btype; 245 int i; 246 247 for (i = 0; i < sc->sc_nrange; i++) { 248 bus_addr_t paddr; 249 bus_type_t iospace; 250 251 if (sc->sc_range[i].cspace != slot) 252 continue; 253 254 /* We've found the connection to the parent bus */ 255 paddr = sc->sc_range[i].poffset + offset; 256 iospace = sc->sc_range[i].pspace; 257 return (bus_space_map2(sc->sc_bustag, iospace, paddr, 258 size, flags, vaddr, hp)); 259 } 260 261 return (EINVAL); 262 } 263 264 void * 265 qec_intr_establish(t, pri, level, flags, handler, arg) 266 bus_space_tag_t t; 267 int pri; 268 int level; 269 int flags; 270 int (*handler) __P((void *)); 271 void *arg; 272 { 273 struct qec_softc *sc = t->cookie; 274 275 if (pri == 0) { 276 /* 277 * qe.c calls bus_intr_establish() with `pri == 0' 278 * XXX - see also comment in qec_attach(). 279 */ 280 if (sc->sc_intr == NULL) { 281 printf("%s: warning: no interrupts\n", 282 sc->sc_dev.dv_xname); 283 return (NULL); 284 } 285 pri = sc->sc_intr->sbi_pri; 286 } 287 288 return (bus_intr_establish(t->parent, pri, level, flags, handler, arg)); 289 } 290 291 void 292 qec_init(sc) 293 struct qec_softc *sc; 294 { 295 bus_space_tag_t t = sc->sc_bustag; 296 bus_space_handle_t qr = sc->sc_regs; 297 u_int32_t v, burst = 0, psize; 298 int i; 299 300 /* First, reset the controller */ 301 bus_space_write_4(t, qr, QEC_QRI_CTRL, QEC_CTRL_RESET); 302 for (i = 0; i < 1000; i++) { 303 DELAY(100); 304 v = bus_space_read_4(t, qr, QEC_QRI_CTRL); 305 if ((v & QEC_CTRL_RESET) == 0) 306 break; 307 } 308 309 /* 310 * Cut available buffer size into receive and transmit buffers. 311 * XXX - should probably be done in be & qe driver... 312 */ 313 v = sc->sc_msize = sc->sc_bufsiz / sc->sc_nchannels; 314 bus_space_write_4(t, qr, QEC_QRI_MSIZE, v); 315 316 v = sc->sc_rsize = sc->sc_bufsiz / (sc->sc_nchannels * 2); 317 bus_space_write_4(t, qr, QEC_QRI_RSIZE, v); 318 bus_space_write_4(t, qr, QEC_QRI_TSIZE, v); 319 320 psize = sc->sc_nchannels == 1 ? QEC_PSIZE_2048 : 0; 321 bus_space_write_4(t, qr, QEC_QRI_PSIZE, psize); 322 323 if (sc->sc_burst & SBUS_BURST_64) 324 burst = QEC_CTRL_B64; 325 else if (sc->sc_burst & SBUS_BURST_32) 326 burst = QEC_CTRL_B32; 327 else 328 burst = QEC_CTRL_B16; 329 330 v = bus_space_read_4(t, qr, QEC_QRI_CTRL); 331 v = (v & QEC_CTRL_MODEMASK) | burst; 332 bus_space_write_4(t, qr, QEC_QRI_CTRL, v); 333 } 334 335 /* 336 * Common routine to initialize the QEC packet ring buffer. 337 * Called from be & qe drivers. 338 */ 339 void 340 qec_meminit(qr, pktbufsz) 341 struct qec_ring *qr; 342 unsigned int pktbufsz; 343 { 344 bus_addr_t txbufdma, rxbufdma; 345 bus_addr_t dma; 346 caddr_t p; 347 unsigned int ntbuf, nrbuf, i; 348 349 p = qr->rb_membase; 350 dma = qr->rb_dmabase; 351 352 ntbuf = qr->rb_ntbuf; 353 nrbuf = qr->rb_nrbuf; 354 355 /* 356 * Allocate transmit descriptors 357 */ 358 qr->rb_txd = (struct qec_xd *)p; 359 qr->rb_txddma = dma; 360 p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 361 dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 362 363 /* 364 * Allocate receive descriptors 365 */ 366 qr->rb_rxd = (struct qec_xd *)p; 367 qr->rb_rxddma = dma; 368 p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 369 dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 370 371 372 /* 373 * Allocate transmit buffers 374 */ 375 qr->rb_txbuf = p; 376 txbufdma = dma; 377 p += ntbuf * pktbufsz; 378 dma += ntbuf * pktbufsz; 379 380 /* 381 * Allocate receive buffers 382 */ 383 qr->rb_rxbuf = p; 384 rxbufdma = dma; 385 p += nrbuf * pktbufsz; 386 dma += nrbuf * pktbufsz; 387 388 /* 389 * Initialize transmit buffer descriptors 390 */ 391 for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) { 392 qr->rb_txd[i].xd_addr = (u_int32_t) 393 (txbufdma + (i % ntbuf) * pktbufsz); 394 qr->rb_txd[i].xd_flags = 0; 395 } 396 397 /* 398 * Initialize receive buffer descriptors 399 */ 400 for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) { 401 qr->rb_rxd[i].xd_addr = (u_int32_t) 402 (rxbufdma + (i % nrbuf) * pktbufsz); 403 qr->rb_rxd[i].xd_flags = (i < nrbuf) 404 ? QEC_XD_OWN | (pktbufsz & QEC_XD_LENGTH) 405 : 0; 406 } 407 408 qr->rb_tdhead = qr->rb_tdtail = 0; 409 qr->rb_td_nbusy = 0; 410 qr->rb_rdtail = 0; 411 } 412
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