qec.c revision 1.16
1 /* $NetBSD: qec.c,v 1.16 2001/12/04 17:56:36 wiz Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: qec.c,v 1.16 2001/12/04 17:56:36 wiz Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 #include <machine/autoconf.h> 52 53 #include <dev/sbus/sbusvar.h> 54 #include <dev/sbus/qecreg.h> 55 #include <dev/sbus/qecvar.h> 56 57 static int qecprint __P((void *, const char *)); 58 static int qecmatch __P((struct device *, struct cfdata *, void *)); 59 static void qecattach __P((struct device *, struct device *, void *)); 60 void qec_init __P((struct qec_softc *)); 61 62 static int qec_bus_map __P(( 63 bus_space_tag_t, 64 bus_type_t, /*slot*/ 65 bus_addr_t, /*offset*/ 66 bus_size_t, /*size*/ 67 int, /*flags*/ 68 vaddr_t, /*preferred virtual address */ 69 bus_space_handle_t *)); 70 static void *qec_intr_establish __P(( 71 bus_space_tag_t, 72 int, /*bus interrupt priority*/ 73 int, /*`device class' interrupt level*/ 74 int, /*flags*/ 75 int (*) __P((void *)), /*handler*/ 76 void *)); /*arg*/ 77 78 struct cfattach qec_ca = { 79 sizeof(struct qec_softc), qecmatch, qecattach 80 }; 81 82 int 83 qecprint(aux, busname) 84 void *aux; 85 const char *busname; 86 { 87 struct sbus_attach_args *sa = aux; 88 bus_space_tag_t t = sa->sa_bustag; 89 struct qec_softc *sc = t->cookie; 90 91 sa->sa_bustag = sc->sc_bustag; /* XXX */ 92 sbus_print(aux, busname); /* XXX */ 93 sa->sa_bustag = t; /* XXX */ 94 return (UNCONF); 95 } 96 97 int 98 qecmatch(parent, cf, aux) 99 struct device *parent; 100 struct cfdata *cf; 101 void *aux; 102 { 103 struct sbus_attach_args *sa = aux; 104 105 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 106 } 107 108 /* 109 * Attach all the sub-devices we can find 110 */ 111 void 112 qecattach(parent, self, aux) 113 struct device *parent, *self; 114 void *aux; 115 { 116 struct sbus_attach_args *sa = aux; 117 struct qec_softc *sc = (void *)self; 118 int node; 119 int sbusburst; 120 bus_space_tag_t sbt; 121 bus_space_handle_t bh; 122 int error; 123 124 sc->sc_bustag = sa->sa_bustag; 125 sc->sc_dmatag = sa->sa_dmatag; 126 node = sa->sa_node; 127 128 if (sa->sa_nreg < 2) { 129 printf("%s: only %d register sets\n", 130 self->dv_xname, sa->sa_nreg); 131 return; 132 } 133 134 if (sbus_bus_map(sa->sa_bustag, 135 sa->sa_reg[0].sbr_slot, 136 sa->sa_reg[0].sbr_offset, 137 sa->sa_reg[0].sbr_size, 138 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_regs) != 0) { 139 printf("%s: attach: cannot map registers\n", self->dv_xname); 140 return; 141 } 142 143 /* 144 * This device's "register space 1" is just a buffer where the 145 * Lance ring-buffers can be stored. Note the buffer's location 146 * and size, so the child driver can pick them up. 147 */ 148 if (sbus_bus_map(sa->sa_bustag, 149 sa->sa_reg[1].sbr_slot, 150 sa->sa_reg[1].sbr_offset, 151 sa->sa_reg[1].sbr_size, 152 BUS_SPACE_MAP_LINEAR, 0, &bh) != 0) { 153 printf("%s: attach: cannot map registers\n", self->dv_xname); 154 return; 155 } 156 sc->sc_buffer = (caddr_t)(u_long)bh; 157 sc->sc_bufsiz = (bus_size_t)sa->sa_reg[1].sbr_size; 158 159 /* Get number of on-board channels */ 160 sc->sc_nchannels = PROM_getpropint(node, "#channels", -1); 161 if (sc->sc_nchannels == -1) { 162 printf(": no channels\n"); 163 return; 164 } 165 166 /* 167 * Get transfer burst size from PROM 168 */ 169 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 170 if (sbusburst == 0) 171 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 172 173 sc->sc_burst = PROM_getpropint(node, "burst-sizes", -1); 174 if (sc->sc_burst == -1) 175 /* take SBus burst sizes */ 176 sc->sc_burst = sbusburst; 177 178 /* Clamp at parent's burst sizes */ 179 sc->sc_burst &= sbusburst; 180 181 sbus_establish(&sc->sc_sd, &sc->sc_dev); 182 183 /* 184 * Collect address translations from the OBP. 185 */ 186 error = PROM_getprop(node, "ranges", sizeof(struct sbus_range), 187 &sc->sc_nrange, (void **)&sc->sc_range); 188 switch (error) { 189 case 0: 190 break; 191 case ENOENT: 192 default: 193 panic("%s: error getting ranges property", self->dv_xname); 194 } 195 196 /* Allocate a bus tag */ 197 sbt = (bus_space_tag_t) 198 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 199 if (sbt == NULL) { 200 printf("%s: attach: out of memory\n", self->dv_xname); 201 return; 202 } 203 204 bzero(sbt, sizeof *sbt); 205 sbt->cookie = sc; 206 sbt->parent = sc->sc_bustag; 207 sbt->sparc_bus_map = qec_bus_map; 208 sbt->sparc_intr_establish = qec_intr_establish; 209 210 /* 211 * Save interrupt information for use in our qec_intr_establish() 212 * function below. Apparently, the intr level for the quad 213 * ethernet board (qe) is stored in the QEC node rather than 214 * separately in each of the QE nodes. 215 * 216 * XXX - qe.c should call bus_intr_establish() with `level = 0'.. 217 * XXX - maybe we should have our own attach args for all that. 218 */ 219 sc->sc_intr = sa->sa_intr; 220 221 printf(": %dK memory\n", sc->sc_bufsiz / 1024); 222 223 qec_init(sc); 224 225 /* search through children */ 226 for (node = firstchild(node); node; node = nextsibling(node)) { 227 struct sbus_attach_args sa; 228 sbus_setup_attach_args((struct sbus_softc *)parent, 229 sbt, sc->sc_dmatag, node, &sa); 230 (void)config_found(&sc->sc_dev, (void *)&sa, qecprint); 231 sbus_destroy_attach_args(&sa); 232 } 233 } 234 235 int 236 qec_bus_map(t, btype, offset, size, flags, vaddr, hp) 237 bus_space_tag_t t; 238 bus_type_t btype; 239 bus_addr_t offset; 240 bus_size_t size; 241 int flags; 242 vaddr_t vaddr; 243 bus_space_handle_t *hp; 244 { 245 struct qec_softc *sc = t->cookie; 246 int slot = btype; 247 int i; 248 249 for (i = 0; i < sc->sc_nrange; i++) { 250 bus_addr_t paddr; 251 bus_type_t iospace; 252 253 if (sc->sc_range[i].cspace != slot) 254 continue; 255 256 /* We've found the connection to the parent bus */ 257 paddr = sc->sc_range[i].poffset + offset; 258 iospace = sc->sc_range[i].pspace; 259 return (bus_space_map2(sc->sc_bustag, iospace, paddr, 260 size, flags, vaddr, hp)); 261 } 262 263 return (EINVAL); 264 } 265 266 void * 267 qec_intr_establish(t, pri, level, flags, handler, arg) 268 bus_space_tag_t t; 269 int pri; 270 int level; 271 int flags; 272 int (*handler) __P((void *)); 273 void *arg; 274 { 275 struct qec_softc *sc = t->cookie; 276 277 if (pri == 0) { 278 /* 279 * qe.c calls bus_intr_establish() with `pri == 0' 280 * XXX - see also comment in qec_attach(). 281 */ 282 if (sc->sc_intr == NULL) { 283 printf("%s: warning: no interrupts\n", 284 sc->sc_dev.dv_xname); 285 return (NULL); 286 } 287 pri = sc->sc_intr->sbi_pri; 288 } 289 290 return (bus_intr_establish(t->parent, pri, level, flags, handler, arg)); 291 } 292 293 void 294 qec_init(sc) 295 struct qec_softc *sc; 296 { 297 bus_space_tag_t t = sc->sc_bustag; 298 bus_space_handle_t qr = sc->sc_regs; 299 u_int32_t v, burst = 0, psize; 300 int i; 301 302 /* First, reset the controller */ 303 bus_space_write_4(t, qr, QEC_QRI_CTRL, QEC_CTRL_RESET); 304 for (i = 0; i < 1000; i++) { 305 DELAY(100); 306 v = bus_space_read_4(t, qr, QEC_QRI_CTRL); 307 if ((v & QEC_CTRL_RESET) == 0) 308 break; 309 } 310 311 /* 312 * Cut available buffer size into receive and transmit buffers. 313 * XXX - should probably be done in be & qe driver... 314 */ 315 v = sc->sc_msize = sc->sc_bufsiz / sc->sc_nchannels; 316 bus_space_write_4(t, qr, QEC_QRI_MSIZE, v); 317 318 v = sc->sc_rsize = sc->sc_bufsiz / (sc->sc_nchannels * 2); 319 bus_space_write_4(t, qr, QEC_QRI_RSIZE, v); 320 bus_space_write_4(t, qr, QEC_QRI_TSIZE, v); 321 322 psize = sc->sc_nchannels == 1 ? QEC_PSIZE_2048 : 0; 323 bus_space_write_4(t, qr, QEC_QRI_PSIZE, psize); 324 325 if (sc->sc_burst & SBUS_BURST_64) 326 burst = QEC_CTRL_B64; 327 else if (sc->sc_burst & SBUS_BURST_32) 328 burst = QEC_CTRL_B32; 329 else 330 burst = QEC_CTRL_B16; 331 332 v = bus_space_read_4(t, qr, QEC_QRI_CTRL); 333 v = (v & QEC_CTRL_MODEMASK) | burst; 334 bus_space_write_4(t, qr, QEC_QRI_CTRL, v); 335 } 336 337 /* 338 * Common routine to initialize the QEC packet ring buffer. 339 * Called from be & qe drivers. 340 */ 341 void 342 qec_meminit(qr, pktbufsz) 343 struct qec_ring *qr; 344 unsigned int pktbufsz; 345 { 346 bus_addr_t txbufdma, rxbufdma; 347 bus_addr_t dma; 348 caddr_t p; 349 unsigned int ntbuf, nrbuf, i; 350 351 p = qr->rb_membase; 352 dma = qr->rb_dmabase; 353 354 ntbuf = qr->rb_ntbuf; 355 nrbuf = qr->rb_nrbuf; 356 357 /* 358 * Allocate transmit descriptors 359 */ 360 qr->rb_txd = (struct qec_xd *)p; 361 qr->rb_txddma = dma; 362 p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 363 dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 364 365 /* 366 * Allocate receive descriptors 367 */ 368 qr->rb_rxd = (struct qec_xd *)p; 369 qr->rb_rxddma = dma; 370 p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 371 dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 372 373 374 /* 375 * Allocate transmit buffers 376 */ 377 qr->rb_txbuf = p; 378 txbufdma = dma; 379 p += ntbuf * pktbufsz; 380 dma += ntbuf * pktbufsz; 381 382 /* 383 * Allocate receive buffers 384 */ 385 qr->rb_rxbuf = p; 386 rxbufdma = dma; 387 p += nrbuf * pktbufsz; 388 dma += nrbuf * pktbufsz; 389 390 /* 391 * Initialize transmit buffer descriptors 392 */ 393 for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) { 394 qr->rb_txd[i].xd_addr = (u_int32_t) 395 (txbufdma + (i % ntbuf) * pktbufsz); 396 qr->rb_txd[i].xd_flags = 0; 397 } 398 399 /* 400 * Initialize receive buffer descriptors 401 */ 402 for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) { 403 qr->rb_rxd[i].xd_addr = (u_int32_t) 404 (rxbufdma + (i % nrbuf) * pktbufsz); 405 qr->rb_rxd[i].xd_flags = (i < nrbuf) 406 ? QEC_XD_OWN | (pktbufsz & QEC_XD_LENGTH) 407 : 0; 408 } 409 410 qr->rb_tdhead = qr->rb_tdtail = 0; 411 qr->rb_td_nbusy = 0; 412 qr->rb_rdtail = 0; 413 } 414
Indexes created Wed Sep 24 15:09:51 GMT 2025