atapi_wdc.c revision 1.59
1 /* $NetBSD: atapi_wdc.c,v 1.59 2003/10/08 10:58:13 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: atapi_wdc.c,v 1.59 2003/10/08 10:58:13 bouyer Exp $"); 35 36 #ifndef WDCDEBUG 37 #define WDCDEBUG 38 #endif /* WDCDEBUG */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/file.h> 44 #include <sys/stat.h> 45 #include <sys/buf.h> 46 #include <sys/malloc.h> 47 #include <sys/device.h> 48 #include <sys/syslog.h> 49 #include <sys/proc.h> 50 #include <sys/dvdio.h> 51 52 #include <machine/intr.h> 53 #include <machine/bus.h> 54 55 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 56 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 57 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 58 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 59 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 60 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 61 62 #include <dev/ata/atareg.h> 63 #include <dev/ata/atavar.h> 64 #include <dev/ic/wdcreg.h> 65 #include <dev/ic/wdcvar.h> 66 67 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 68 69 #define DEBUG_INTR 0x01 70 #define DEBUG_XFERS 0x02 71 #define DEBUG_STATUS 0x04 72 #define DEBUG_FUNCS 0x08 73 #define DEBUG_PROBE 0x10 74 #ifdef WDCDEBUG 75 int wdcdebug_atapi_mask = 0; 76 #define WDCDEBUG_PRINT(args, level) \ 77 if (wdcdebug_atapi_mask & (level)) \ 78 printf args 79 #else 80 #define WDCDEBUG_PRINT(args, level) 81 #endif 82 83 #define ATAPI_DELAY 10 /* 10 ms, this is used only before sending a cmd */ 84 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATYRE cmds */ 85 int wdc_atapi_get_params __P((struct scsipi_channel *, int, 86 struct ataparams *)); 87 void wdc_atapi_probe_device __P((struct atapibus_softc *, int)); 88 void wdc_atapi_minphys __P((struct buf *bp)); 89 void wdc_atapi_start __P((struct channel_softc *,struct wdc_xfer *)); 90 int wdc_atapi_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 91 void wdc_atapi_kill_xfer __P((struct channel_softc *, struct wdc_xfer *)); 92 void wdc_atapi_phase_complete __P((struct wdc_xfer *)); 93 void wdc_atapi_done __P((struct channel_softc *, struct wdc_xfer *)); 94 void wdc_atapi_reset __P((struct channel_softc *, struct wdc_xfer *)); 95 void wdc_atapi_scsipi_request __P((struct scsipi_channel *, 96 scsipi_adapter_req_t, void *)); 97 void wdc_atapi_kill_pending __P((struct scsipi_periph *)); 98 static void wdc_atapi_polldsc __P((void *arg)); 99 100 #define MAX_SIZE MAXPHYS 101 102 const struct scsipi_bustype wdc_atapi_bustype = { 103 SCSIPI_BUSTYPE_ATAPI, 104 atapi_scsipi_cmd, 105 atapi_interpret_sense, 106 atapi_print_addr, 107 wdc_atapi_kill_pending, 108 }; 109 110 void 111 wdc_atapibus_attach(ata_sc) 112 struct atabus_softc *ata_sc; 113 { 114 struct channel_softc *chp = ata_sc->sc_chan; 115 struct wdc_softc *wdc = chp->wdc; 116 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 117 struct scsipi_channel *chan = &chp->ch_atapi_channel; 118 119 /* 120 * Fill in the scsipi_adapter. 121 */ 122 adapt->adapt_dev = &wdc->sc_dev; 123 adapt->adapt_nchannels = wdc->nchannels; 124 adapt->adapt_request = wdc_atapi_scsipi_request; 125 adapt->adapt_minphys = wdc_atapi_minphys; 126 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 127 adapt->adapt_flags |= SCSIPI_ADAPT_POLL_ONLY; 128 wdc->sc_atapi_adapter.atapi_probe_device = wdc_atapi_probe_device; 129 130 /* 131 * Fill in the scsipi_channel. 132 */ 133 memset(chan, 0, sizeof(*chan)); 134 chan->chan_adapter = adapt; 135 chan->chan_bustype = &wdc_atapi_bustype; 136 chan->chan_channel = chp->channel; 137 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 138 chan->chan_openings = 1; 139 chan->chan_max_periph = 1; 140 chan->chan_ntargets = 2; 141 chan->chan_nluns = 1; 142 143 chp->atapibus = config_found(&ata_sc->sc_dev, chan, atapiprint); 144 } 145 146 void 147 wdc_atapi_minphys(bp) 148 struct buf *bp; 149 { 150 151 if (bp->b_bcount > MAX_SIZE) 152 bp->b_bcount = MAX_SIZE; 153 minphys(bp); 154 } 155 156 /* 157 * Kill off all pending xfers for a periph. 158 * 159 * Must be called at splbio(). 160 */ 161 void 162 wdc_atapi_kill_pending(periph) 163 struct scsipi_periph *periph; 164 { 165 struct wdc_softc *wdc = 166 (void *)periph->periph_channel->chan_adapter->adapt_dev; 167 struct channel_softc *chp = 168 wdc->channels[periph->periph_channel->chan_channel]; 169 170 wdc_kill_pending(chp); 171 } 172 173 void 174 wdc_atapi_kill_xfer(chp, xfer) 175 struct channel_softc *chp; 176 struct wdc_xfer *xfer; 177 { 178 struct scsipi_xfer *sc_xfer = xfer->cmd; 179 180 callout_stop(&chp->ch_callout); 181 /* remove this command from xfer queue */ 182 wdc_free_xfer(chp, xfer); 183 sc_xfer->error = XS_DRIVER_STUFFUP; 184 scsipi_done(sc_xfer); 185 } 186 187 int 188 wdc_atapi_get_params(chan, drive, id) 189 struct scsipi_channel *chan; 190 int drive; 191 struct ataparams *id; 192 { 193 struct wdc_softc *wdc = (void *)chan->chan_adapter->adapt_dev; 194 struct channel_softc *chp = wdc->channels[chan->chan_channel]; 195 struct wdc_command wdc_c; 196 197 /* if no ATAPI device detected at wdc attach time, skip */ 198 if ((chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) == 0) { 199 WDCDEBUG_PRINT(("wdc_atapi_get_params: drive %d not present\n", 200 drive), DEBUG_PROBE); 201 return -1; 202 } 203 204 memset(&wdc_c, 0, sizeof(struct wdc_command)); 205 wdc_c.r_command = ATAPI_SOFT_RESET; 206 wdc_c.r_st_bmask = 0; 207 wdc_c.r_st_pmask = 0; 208 wdc_c.flags = AT_POLL; 209 wdc_c.timeout = WDC_RESET_WAIT; 210 if (wdc_exec_command(&chp->ch_drive[drive], &wdc_c) != WDC_COMPLETE) { 211 printf("wdc_atapi_get_params: ATAPI_SOFT_RESET failed for" 212 " drive %s:%d:%d: driver failed\n", 213 chp->wdc->sc_dev.dv_xname, chp->channel, drive); 214 panic("wdc_atapi_get_params"); 215 } 216 if (wdc_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 217 WDCDEBUG_PRINT(("wdc_atapi_get_params: ATAPI_SOFT_RESET " 218 "failed for drive %s:%d:%d: error 0x%x\n", 219 chp->wdc->sc_dev.dv_xname, chp->channel, drive, 220 wdc_c.r_error), DEBUG_PROBE); 221 return -1; 222 } 223 chp->ch_drive[drive].state = 0; 224 225 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 226 227 /* Some ATAPI devices need a bit more time after software reset. */ 228 delay(5000); 229 if (ata_get_params(&chp->ch_drive[drive], AT_WAIT, id) != 0) { 230 WDCDEBUG_PRINT(("wdc_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 231 "failed for drive %s:%d:%d: error 0x%x\n", 232 chp->wdc->sc_dev.dv_xname, chp->channel, drive, 233 wdc_c.r_error), DEBUG_PROBE); 234 return -1; 235 } 236 return 0; 237 } 238 239 void 240 wdc_atapi_probe_device(sc, target) 241 struct atapibus_softc *sc; 242 int target; 243 { 244 struct scsipi_channel *chan = sc->sc_channel; 245 struct scsipi_periph *periph; 246 struct ataparams ids; 247 struct ataparams *id = &ids; 248 struct wdc_softc *wdc = (void *)chan->chan_adapter->adapt_dev; 249 struct channel_softc *chp = wdc->channels[chan->chan_channel]; 250 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 251 struct scsipibus_attach_args sa; 252 char serial_number[21], model[41], firmware_revision[9]; 253 254 /* skip if already attached */ 255 if (scsipi_lookup_periph(chan, target, 0) != NULL) 256 return; 257 258 if (wdc_atapi_get_params(chan, target, id) == 0) { 259 #ifdef ATAPI_DEBUG_PROBE 260 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 261 sc->sc_dev.dv_xname, target, 262 id->atap_config & ATAPI_CFG_CMD_MASK, 263 id->atap_config & ATAPI_CFG_DRQ_MASK); 264 #endif 265 periph = scsipi_alloc_periph(M_NOWAIT); 266 if (periph == NULL) { 267 printf("%s: unable to allocate periph for drive %d\n", 268 sc->sc_dev.dv_xname, target); 269 return; 270 } 271 periph->periph_dev = NULL; 272 periph->periph_channel = chan; 273 periph->periph_switch = &atapi_probe_periphsw; 274 periph->periph_target = target; 275 periph->periph_lun = 0; 276 periph->periph_quirks = PQUIRK_ONLYBIG; 277 278 #ifdef SCSIPI_DEBUG 279 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 280 SCSIPI_DEBUG_TARGET == target) 281 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 282 #endif 283 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 284 if (id->atap_config & ATAPI_CFG_REMOV) 285 periph->periph_flags |= PERIPH_REMOVABLE; 286 if (periph->periph_type == T_SEQUENTIAL) 287 drvp->drive_flags |= DRIVE_ATAPIST; 288 289 sa.sa_periph = periph; 290 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 291 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 292 T_REMOV : T_FIXED; 293 scsipi_strvis(model, 40, id->atap_model, 40); 294 scsipi_strvis(serial_number, 20, id->atap_serial, 20); 295 scsipi_strvis(firmware_revision, 8, id->atap_revision, 8); 296 sa.sa_inqbuf.vendor = model; 297 sa.sa_inqbuf.product = serial_number; 298 sa.sa_inqbuf.revision = firmware_revision; 299 300 /* 301 * Determine the operating mode capabilities of the device. 302 */ 303 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 304 periph->periph_cap |= PERIPH_CAP_CMD16; 305 /* XXX This is gross. */ 306 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 307 308 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 309 310 if (drvp->drv_softc) 311 wdc_probe_caps(drvp); 312 } 313 } 314 315 void 316 wdc_atapi_scsipi_request(chan, req, arg) 317 struct scsipi_channel *chan; 318 scsipi_adapter_req_t req; 319 void *arg; 320 { 321 struct scsipi_adapter *adapt = chan->chan_adapter; 322 struct scsipi_periph *periph; 323 struct scsipi_xfer *sc_xfer; 324 struct wdc_softc *wdc = (void *)adapt->adapt_dev; 325 struct wdc_xfer *xfer; 326 int channel = chan->chan_channel; 327 int drive, s; 328 329 switch (req) { 330 case ADAPTER_REQ_RUN_XFER: 331 sc_xfer = arg; 332 periph = sc_xfer->xs_periph; 333 drive = periph->periph_target; 334 335 WDCDEBUG_PRINT(("wdc_atapi_scsipi_request %s:%d:%d\n", 336 wdc->sc_dev.dv_xname, channel, drive), DEBUG_XFERS); 337 if ((wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 338 sc_xfer->error = XS_DRIVER_STUFFUP; 339 scsipi_done(sc_xfer); 340 return; 341 } 342 343 xfer = wdc_get_xfer(WDC_NOSLEEP); 344 if (xfer == NULL) { 345 sc_xfer->error = XS_RESOURCE_SHORTAGE; 346 scsipi_done(sc_xfer); 347 return; 348 } 349 350 if (sc_xfer->xs_control & XS_CTL_POLL) 351 xfer->c_flags |= C_POLL; 352 if ((wdc->channels[channel]->ch_drive[drive].drive_flags & 353 (DRIVE_DMA | DRIVE_UDMA)) && sc_xfer->datalen > 0) 354 xfer->c_flags |= C_DMA; 355 xfer->drive = drive; 356 xfer->c_flags |= C_ATAPI; 357 if (sc_xfer->cmd->opcode == GPCMD_REPORT_KEY || 358 sc_xfer->cmd->opcode == GPCMD_SEND_KEY || 359 sc_xfer->cmd->opcode == GPCMD_READ_DVD_STRUCTURE) { 360 /* 361 * DVD authentication commands must always be done in 362 * PIO mode. 363 */ 364 xfer->c_flags &= ~C_DMA; 365 } 366 /* 367 * DMA can't deal with transfers which are not a multiple of 368 * 2 bytes. It's a bug to request such transfers for ATAPI 369 * but as the request can come from userland, we have to 370 * protect against it. 371 * Also some devices seems to not handle DMA xfers of less than 372 * 4 bytes. 373 */ 374 if (sc_xfer->datalen < 4 || (sc_xfer->datalen & 0x01)) 375 xfer->c_flags &= ~C_DMA; 376 377 xfer->cmd = sc_xfer; 378 xfer->databuf = sc_xfer->data; 379 xfer->c_bcount = sc_xfer->datalen; 380 xfer->c_start = wdc_atapi_start; 381 xfer->c_intr = wdc_atapi_intr; 382 xfer->c_kill_xfer = wdc_atapi_kill_xfer; 383 xfer->c_dscpoll = 0; 384 s = splbio(); 385 wdc_exec_xfer(wdc->channels[channel], xfer); 386 #ifdef DIAGNOSTIC 387 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 388 (sc_xfer->xs_status & XS_STS_DONE) == 0) 389 panic("wdc_atapi_scsipi_request: polled command " 390 "not done"); 391 #endif 392 splx(s); 393 return; 394 395 default: 396 /* Not supported, nothing to do. */ 397 ; 398 } 399 } 400 401 void 402 wdc_atapi_start(chp, xfer) 403 struct channel_softc *chp; 404 struct wdc_xfer *xfer; 405 { 406 struct scsipi_xfer *sc_xfer = xfer->cmd; 407 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 408 int wait_flags = (sc_xfer->xs_control & XS_CTL_POLL) ? AT_POLL : 0; 409 char *errstring; 410 411 WDCDEBUG_PRINT(("wdc_atapi_start %s:%d:%d, scsi flags 0x%x \n", 412 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive, 413 sc_xfer->xs_control), DEBUG_XFERS); 414 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 415 drvp->n_xfers++; 416 /* Do control operations specially. */ 417 if (__predict_false(drvp->state < READY)) { 418 /* If it's not a polled command, we need the kenrel thread */ 419 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 && 420 (chp->ch_flags & WDCF_TH_RUN) == 0) { 421 chp->ch_queue->queue_freese++; 422 wakeup(&chp->thread); 423 return; 424 } 425 /* 426 * disable interrupts, all commands here should be quick 427 * enouth to be able to poll, and we don't go here that often 428 */ 429 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 430 WDCTL_4BIT | WDCTL_IDS); 431 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 432 chp->wdc->select(chp,xfer->drive); 433 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 434 WDSD_IBM | (xfer->drive << 4)); 435 /* Don't try to set mode if controller can't be adjusted */ 436 if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0) 437 goto ready; 438 /* Also don't try if the drive didn't report its mode */ 439 if ((drvp->drive_flags & DRIVE_MODE) == 0) 440 goto ready; 441 errstring = "unbusy"; 442 if (wait_for_unbusy(chp, ATAPI_DELAY, wait_flags)) 443 goto timeout; 444 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 445 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 446 errstring = "piomode"; 447 if (wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags)) 448 goto timeout; 449 if (chp->ch_status & WDCS_ERR) { 450 if (chp->ch_error == WDCE_ABRT) { 451 /* 452 * some ATAPI drives rejects pio settings. 453 * all we can do here is fall back to PIO 0 454 */ 455 drvp->drive_flags &= ~DRIVE_MODE; 456 drvp->drive_flags &= ~(DRIVE_DMA|DRIVE_UDMA); 457 drvp->PIO_mode = 0; 458 drvp->DMA_mode = 0; 459 printf("%s:%d:%d: pio setting rejected, " 460 "falling back to PIO mode 0\n", 461 chp->wdc->sc_dev.dv_xname, 462 chp->channel, xfer->drive); 463 chp->wdc->set_modes(chp); 464 goto ready; 465 } 466 goto error; 467 } 468 if (drvp->drive_flags & DRIVE_UDMA) { 469 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 470 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 471 } else if (drvp->drive_flags & DRIVE_DMA) { 472 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 473 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 474 } else { 475 goto ready; 476 } 477 errstring = "dmamode"; 478 if (wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags)) 479 goto timeout; 480 if (chp->ch_status & WDCS_ERR) 481 goto error; 482 ready: 483 drvp->state = READY; 484 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 485 WDCTL_4BIT); 486 } 487 /* start timeout machinery */ 488 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 489 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 490 wdctimeout, chp); 491 492 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 493 chp->wdc->select(chp,xfer->drive); 494 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 495 WDSD_IBM | (xfer->drive << 4)); 496 switch (wait_for_unbusy(chp, ATAPI_DELAY, wait_flags) < 0) { 497 case WDCWAIT_OK: 498 break; 499 case WDCWAIT_TOUT: 500 printf("wdc_atapi_start: not ready, st = %02x\n", 501 chp->ch_status); 502 sc_xfer->error = XS_TIMEOUT; 503 wdc_atapi_reset(chp, xfer); 504 return; 505 case WDCWAIT_THR: 506 return; 507 } 508 509 /* 510 * Even with WDCS_ERR, the device should accept a command packet 511 * Limit length to what can be stuffed into the cylinder register 512 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 513 * but not all devices do that and it's not obvious from the 514 * ATAPI spec that that behaviour should be expected. If more 515 * data is necessary, multiple data transfer phases will be done. 516 */ 517 518 wdccommand(chp, xfer->drive, ATAPI_PKT_CMD, 519 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 520 0, 0, 0, 521 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 522 523 /* 524 * If there is no interrupt for CMD input, busy-wait for it (done in 525 * the interrupt routine. If it is a polled command, call the interrupt 526 * routine until command is done. 527 */ 528 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 529 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) { 530 /* Wait for at last 400ns for status bit to be valid */ 531 DELAY(1); 532 if (chp->ch_flags & WDCF_DMA_WAIT) { 533 wdc_dmawait(chp, xfer, sc_xfer->timeout); 534 chp->ch_flags &= ~WDCF_DMA_WAIT; 535 } 536 wdc_atapi_intr(chp, xfer, 0); 537 } else { 538 chp->ch_flags |= WDCF_IRQ_WAIT; 539 } 540 if (sc_xfer->xs_control & XS_CTL_POLL) { 541 while ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 542 /* Wait for at last 400ns for status bit to be valid */ 543 DELAY(1); 544 wdc_atapi_intr(chp, xfer, 0); 545 } 546 } 547 return; 548 timeout: 549 printf("%s:%d:%d: %s timed out\n", 550 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, errstring); 551 sc_xfer->error = XS_TIMEOUT; 552 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 553 wdc_atapi_reset(chp, xfer); 554 return; 555 error: 556 printf("%s:%d:%d: %s ", 557 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 558 errstring); 559 printf("error (0x%x)\n", chp->ch_error); 560 sc_xfer->error = XS_SHORTSENSE; 561 sc_xfer->sense.atapi_sense = chp->ch_error; 562 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 563 wdc_atapi_reset(chp, xfer); 564 return; 565 } 566 567 int 568 wdc_atapi_intr(chp, xfer, irq) 569 struct channel_softc *chp; 570 struct wdc_xfer *xfer; 571 int irq; 572 { 573 struct scsipi_xfer *sc_xfer = xfer->cmd; 574 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 575 int len, phase, i, retries=0; 576 int ire; 577 int dma_flags = 0; 578 void *cmd; 579 580 WDCDEBUG_PRINT(("wdc_atapi_intr %s:%d:%d\n", 581 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), DEBUG_INTR); 582 583 /* Is it not a transfer, but a control operation? */ 584 if (drvp->state < READY) { 585 printf("%s:%d:%d: bad state %d in wdc_atapi_intr\n", 586 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 587 drvp->state); 588 panic("wdc_atapi_intr: bad state"); 589 } 590 /* 591 * If we missed an interrupt in a PIO transfer, reset and restart. 592 * Don't try to continue transfer, we may have missed cycles. 593 */ 594 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 595 sc_xfer->error = XS_TIMEOUT; 596 wdc_atapi_reset(chp, xfer); 597 return 1; 598 } 599 600 /* Ack interrupt done in wait_for_unbusy */ 601 if (chp->wdc->cap & WDC_CAPABILITY_SELECT) 602 chp->wdc->select(chp,xfer->drive); 603 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 604 WDSD_IBM | (xfer->drive << 4)); 605 if (wait_for_unbusy(chp, 606 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL) == WDCWAIT_TOUT) { 607 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 608 return 0; /* IRQ was not for us */ 609 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip=%d\n", 610 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 611 xfer->c_bcount, xfer->c_skip); 612 if (xfer->c_flags & C_DMA) { 613 ata_dmaerr(drvp, 614 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 615 } 616 sc_xfer->error = XS_TIMEOUT; 617 wdc_atapi_reset(chp, xfer); 618 return 1; 619 } 620 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 621 chp->wdc->irqack(chp); 622 623 /* 624 * If we missed an IRQ and were using DMA, flag it as a DMA error 625 * and reset device. 626 */ 627 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 628 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 629 sc_xfer->error = XS_RESET; 630 wdc_atapi_reset(chp, xfer); 631 return (1); 632 } 633 /* 634 * if the request sense command was aborted, report the short sense 635 * previously recorded, else continue normal processing 636 */ 637 638 if (xfer->c_flags & C_DMA) 639 dma_flags = (sc_xfer->xs_control & XS_CTL_DATA_IN) 640 ? WDC_DMA_READ : 0; 641 again: 642 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) + 643 256 * bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 644 ire = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_ireason); 645 phase = (ire & (WDCI_CMD | WDCI_IN)) | (chp->ch_status & WDCS_DRQ); 646 WDCDEBUG_PRINT(("wdc_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x " 647 "ire 0x%x :", xfer->c_bcount, 648 len, chp->ch_status, chp->ch_error, ire), DEBUG_INTR); 649 650 switch (phase) { 651 case PHASE_CMDOUT: 652 cmd = sc_xfer->cmd; 653 WDCDEBUG_PRINT(("PHASE_CMDOUT\n"), DEBUG_INTR); 654 /* Init the DMA channel if necessary */ 655 if (xfer->c_flags & C_DMA) { 656 if ((*chp->wdc->dma_init)(chp->wdc->dma_arg, 657 chp->channel, xfer->drive, 658 xfer->databuf, xfer->c_bcount, dma_flags) != 0) { 659 sc_xfer->error = XS_DRIVER_STUFFUP; 660 break; 661 } 662 } 663 /* send packet command */ 664 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 665 if ((chp->wdc->cap & WDC_CAPABILITY_ATAPI_NOSTREAM)) { 666 if (drvp->drive_flags & DRIVE_CAP32) 667 bus_space_write_multi_4(chp->data32iot, 668 chp->data32ioh, 0, (u_int32_t *)cmd, 669 sc_xfer->cmdlen >> 2); 670 else 671 bus_space_write_multi_2(chp->cmd_iot, 672 chp->cmd_ioh, wd_data, (u_int16_t *)cmd, 673 sc_xfer->cmdlen >> 1); 674 } else { 675 if (drvp->drive_flags & DRIVE_CAP32) 676 bus_space_write_multi_stream_4(chp->data32iot, 677 chp->data32ioh, 0, (u_int32_t *)cmd, 678 sc_xfer->cmdlen >> 2); 679 else 680 bus_space_write_multi_stream_2(chp->cmd_iot, 681 chp->cmd_ioh, wd_data, (u_int16_t *)cmd, 682 sc_xfer->cmdlen >> 1); 683 } 684 /* Start the DMA channel if necessary */ 685 if (xfer->c_flags & C_DMA) { 686 (*chp->wdc->dma_start)(chp->wdc->dma_arg, 687 chp->channel, xfer->drive); 688 chp->ch_flags |= WDCF_DMA_WAIT; 689 } 690 691 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) { 692 chp->ch_flags |= WDCF_IRQ_WAIT; 693 } 694 return 1; 695 696 case PHASE_DATAOUT: 697 /* write data */ 698 WDCDEBUG_PRINT(("PHASE_DATAOUT\n"), DEBUG_INTR); 699 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 700 (xfer->c_flags & C_DMA) != 0) { 701 printf("wdc_atapi_intr: bad data phase DATAOUT\n"); 702 if (xfer->c_flags & C_DMA) { 703 ata_dmaerr(drvp, 704 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 705 } 706 sc_xfer->error = XS_TIMEOUT; 707 wdc_atapi_reset(chp, xfer); 708 return 1; 709 } 710 if (xfer->c_bcount < len) { 711 printf("wdc_atapi_intr: warning: write only " 712 "%d of %d requested bytes\n", xfer->c_bcount, len); 713 if ((chp->wdc->cap & WDC_CAPABILITY_ATAPI_NOSTREAM)) { 714 bus_space_write_multi_2(chp->cmd_iot, 715 chp->cmd_ioh, wd_data, 716 (u_int16_t *)((char *)xfer->databuf + 717 xfer->c_skip), 718 xfer->c_bcount >> 1); 719 } else { 720 bus_space_write_multi_stream_2(chp->cmd_iot, 721 chp->cmd_ioh, wd_data, 722 (u_int16_t *)((char *)xfer->databuf + 723 xfer->c_skip), 724 xfer->c_bcount >> 1); 725 } 726 for (i = xfer->c_bcount; i < len; i += 2) 727 bus_space_write_2(chp->cmd_iot, chp->cmd_ioh, 728 wd_data, 0); 729 xfer->c_skip += xfer->c_bcount; 730 xfer->c_bcount = 0; 731 } else { 732 if (drvp->drive_flags & DRIVE_CAP32) { 733 if ((chp->wdc->cap & WDC_CAPABILITY_ATAPI_NOSTREAM)) 734 bus_space_write_multi_4(chp->data32iot, 735 chp->data32ioh, 0, 736 (u_int32_t *)((char *)xfer->databuf + 737 xfer->c_skip), 738 len >> 2); 739 else 740 bus_space_write_multi_stream_4(chp->data32iot, 741 chp->data32ioh, wd_data, 742 (u_int32_t *)((char *)xfer->databuf + 743 xfer->c_skip), 744 len >> 2); 745 746 xfer->c_skip += len & 0xfffffffc; 747 xfer->c_bcount -= len & 0xfffffffc; 748 len = len & 0x03; 749 } 750 if (len > 0) { 751 if ((chp->wdc->cap & WDC_CAPABILITY_ATAPI_NOSTREAM)) 752 bus_space_write_multi_2(chp->cmd_iot, 753 chp->cmd_ioh, wd_data, 754 (u_int16_t *)((char *)xfer->databuf + 755 xfer->c_skip), 756 len >> 1); 757 else 758 bus_space_write_multi_stream_2(chp->cmd_iot, 759 chp->cmd_ioh, wd_data, 760 (u_int16_t *)((char *)xfer->databuf + 761 xfer->c_skip), 762 len >> 1); 763 xfer->c_skip += len; 764 xfer->c_bcount -= len; 765 } 766 } 767 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) { 768 chp->ch_flags |= WDCF_IRQ_WAIT; 769 } 770 return 1; 771 772 case PHASE_DATAIN: 773 /* Read data */ 774 WDCDEBUG_PRINT(("PHASE_DATAIN\n"), DEBUG_INTR); 775 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 776 (xfer->c_flags & C_DMA) != 0) { 777 printf("wdc_atapi_intr: bad data phase DATAIN\n"); 778 if (xfer->c_flags & C_DMA) { 779 ata_dmaerr(drvp, 780 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 781 } 782 sc_xfer->error = XS_TIMEOUT; 783 wdc_atapi_reset(chp, xfer); 784 return 1; 785 } 786 if (xfer->c_bcount < len) { 787 printf("wdc_atapi_intr: warning: reading only " 788 "%d of %d bytes\n", xfer->c_bcount, len); 789 if ((chp->wdc->cap & WDC_CAPABILITY_ATAPI_NOSTREAM)) { 790 bus_space_read_multi_2(chp->cmd_iot, 791 chp->cmd_ioh, wd_data, 792 (u_int16_t *)((char *)xfer->databuf + 793 xfer->c_skip), 794 xfer->c_bcount >> 1); 795 } else { 796 bus_space_read_multi_stream_2(chp->cmd_iot, 797 chp->cmd_ioh, wd_data, 798 (u_int16_t *)((char *)xfer->databuf + 799 xfer->c_skip), 800 xfer->c_bcount >> 1); 801 } 802 wdcbit_bucket(chp, len - xfer->c_bcount); 803 xfer->c_skip += xfer->c_bcount; 804 xfer->c_bcount = 0; 805 } else { 806 if (drvp->drive_flags & DRIVE_CAP32) { 807 if ((chp->wdc->cap & WDC_CAPABILITY_ATAPI_NOSTREAM)) 808 bus_space_read_multi_4(chp->data32iot, 809 chp->data32ioh, 0, 810 (u_int32_t *)((char *)xfer->databuf + 811 xfer->c_skip), 812 len >> 2); 813 else 814 bus_space_read_multi_stream_4(chp->data32iot, 815 chp->data32ioh, wd_data, 816 (u_int32_t *)((char *)xfer->databuf + 817 xfer->c_skip), 818 len >> 2); 819 820 xfer->c_skip += len & 0xfffffffc; 821 xfer->c_bcount -= len & 0xfffffffc; 822 len = len & 0x03; 823 } 824 if (len > 0) { 825 if ((chp->wdc->cap & WDC_CAPABILITY_ATAPI_NOSTREAM)) 826 bus_space_read_multi_2(chp->cmd_iot, 827 chp->cmd_ioh, wd_data, 828 (u_int16_t *)((char *)xfer->databuf + 829 xfer->c_skip), 830 len >> 1); 831 else 832 bus_space_read_multi_stream_2(chp->cmd_iot, 833 chp->cmd_ioh, wd_data, 834 (u_int16_t *)((char *)xfer->databuf + 835 xfer->c_skip), 836 len >> 1); 837 xfer->c_skip += len; 838 xfer->c_bcount -=len; 839 } 840 } 841 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) { 842 chp->ch_flags |= WDCF_IRQ_WAIT; 843 } 844 return 1; 845 846 case PHASE_ABORTED: 847 case PHASE_COMPLETED: 848 WDCDEBUG_PRINT(("PHASE_COMPLETED\n"), DEBUG_INTR); 849 if (xfer->c_flags & C_DMA) { 850 xfer->c_bcount -= sc_xfer->datalen; 851 } 852 sc_xfer->resid = xfer->c_bcount; 853 wdc_atapi_phase_complete(xfer); 854 return(1); 855 856 default: 857 if (++retries<500) { 858 DELAY(100); 859 chp->ch_status = bus_space_read_1(chp->cmd_iot, 860 chp->cmd_ioh, wd_status); 861 chp->ch_error = bus_space_read_1(chp->cmd_iot, 862 chp->cmd_ioh, wd_error); 863 goto again; 864 } 865 printf("wdc_atapi_intr: unknown phase 0x%x\n", phase); 866 if (chp->ch_status & WDCS_ERR) { 867 sc_xfer->error = XS_SHORTSENSE; 868 sc_xfer->sense.atapi_sense = chp->ch_error; 869 } else { 870 if (xfer->c_flags & C_DMA) { 871 ata_dmaerr(drvp, 872 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 873 } 874 sc_xfer->error = XS_RESET; 875 wdc_atapi_reset(chp, xfer); 876 return (1); 877 } 878 } 879 WDCDEBUG_PRINT(("wdc_atapi_intr: wdc_atapi_done() (end), error 0x%x " 880 "sense 0x%x\n", sc_xfer->error, sc_xfer->sense.atapi_sense), 881 DEBUG_INTR); 882 wdc_atapi_done(chp, xfer); 883 return (1); 884 } 885 886 void 887 wdc_atapi_phase_complete(xfer) 888 struct wdc_xfer *xfer; 889 { 890 struct channel_softc *chp = xfer->chp; 891 struct scsipi_xfer *sc_xfer = xfer->cmd; 892 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 893 894 /* wait for DSC if needed */ 895 if (drvp->drive_flags & DRIVE_ATAPIST) { 896 WDCDEBUG_PRINT(("wdc_atapi_phase_complete(%s:%d:%d) " 897 "polldsc %d\n", chp->wdc->sc_dev.dv_xname, chp->channel, 898 xfer->drive, xfer->c_dscpoll), DEBUG_XFERS); 899 #if 1 900 if (cold) 901 panic("wdc_atapi_phase_complete: cold"); 902 #endif 903 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, 904 AT_POLL) == WDCWAIT_TOUT) { 905 /* 10ms not enough, try again in 1 tick */ 906 if (xfer->c_dscpoll++ > 907 mstohz(sc_xfer->timeout)) { 908 printf("%s:%d:%d: wait_for_dsc " 909 "failed\n", 910 chp->wdc->sc_dev.dv_xname, 911 chp->channel, xfer->drive); 912 sc_xfer->error = XS_TIMEOUT; 913 wdc_atapi_reset(chp, xfer); 914 return; 915 } else 916 callout_reset(&chp->ch_callout, 1, 917 wdc_atapi_polldsc, xfer); 918 return; 919 } 920 } 921 922 /* 923 * Some drive occasionally set WDCS_ERR with 924 * "ATA illegal length indication" in the error 925 * register. If we read some data the sense is valid 926 * anyway, so don't report the error. 927 */ 928 if (chp->ch_status & WDCS_ERR && 929 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 930 sc_xfer->resid == sc_xfer->datalen)) { 931 /* save the short sense */ 932 sc_xfer->error = XS_SHORTSENSE; 933 sc_xfer->sense.atapi_sense = chp->ch_error; 934 if ((sc_xfer->xs_periph->periph_quirks & 935 PQUIRK_NOSENSE) == 0) { 936 /* ask scsipi to send a REQUEST_SENSE */ 937 sc_xfer->error = XS_BUSY; 938 sc_xfer->status = SCSI_CHECK; 939 } else if (chp->wdc->dma_status & 940 (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 941 ata_dmaerr(drvp, 942 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 943 sc_xfer->error = XS_RESET; 944 wdc_atapi_reset(chp, xfer); 945 return; 946 } 947 } 948 if (xfer->c_bcount != 0) { 949 WDCDEBUG_PRINT(("wdc_atapi_intr: bcount value is " 950 "%d after io\n", xfer->c_bcount), DEBUG_XFERS); 951 } 952 #ifdef DIAGNOSTIC 953 if (xfer->c_bcount < 0) { 954 printf("wdc_atapi_intr warning: bcount value " 955 "is %d after io\n", xfer->c_bcount); 956 } 957 #endif 958 WDCDEBUG_PRINT(("wdc_atapi_phase_complete: wdc_atapi_done(), " 959 "error 0x%x sense 0x%x\n", sc_xfer->error, 960 sc_xfer->sense.atapi_sense), DEBUG_INTR); 961 wdc_atapi_done(chp, xfer); 962 } 963 964 void 965 wdc_atapi_done(chp, xfer) 966 struct channel_softc *chp; 967 struct wdc_xfer *xfer; 968 { 969 struct scsipi_xfer *sc_xfer = xfer->cmd; 970 971 WDCDEBUG_PRINT(("wdc_atapi_done %s:%d:%d: flags 0x%x\n", 972 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 973 (u_int)xfer->c_flags), DEBUG_XFERS); 974 callout_stop(&chp->ch_callout); 975 /* remove this command from xfer queue */ 976 wdc_free_xfer(chp, xfer); 977 978 WDCDEBUG_PRINT(("wdc_atapi_done: scsipi_done\n"), DEBUG_XFERS); 979 scsipi_done(sc_xfer); 980 WDCDEBUG_PRINT(("wdcstart from wdc_atapi_done, flags 0x%x\n", 981 chp->ch_flags), DEBUG_XFERS); 982 wdcstart(chp); 983 } 984 985 void 986 wdc_atapi_reset(chp, xfer) 987 struct channel_softc *chp; 988 struct wdc_xfer *xfer; 989 { 990 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 991 struct scsipi_xfer *sc_xfer = xfer->cmd; 992 993 wdccommandshort(chp, xfer->drive, ATAPI_SOFT_RESET); 994 drvp->state = 0; 995 if (wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL) != 0) { 996 printf("%s:%d:%d: reset failed\n", 997 chp->wdc->sc_dev.dv_xname, chp->channel, 998 xfer->drive); 999 sc_xfer->error = XS_SELTIMEOUT; 1000 } 1001 wdc_atapi_done(chp, xfer); 1002 return; 1003 } 1004 1005 static void 1006 wdc_atapi_polldsc(arg) 1007 void *arg; 1008 { 1009 wdc_atapi_phase_complete(arg); 1010 } 1011
Indexes created Tue Sep 23 01:09:51 GMT 2025