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sdmmcreg.h revision 1.29.6.1
      1  1.29.6.1       snj /*	$NetBSD: sdmmcreg.h,v 1.29.6.1 2017/07/01 08:45:03 snj Exp $	*/
      2       1.1    nonaka /*	$OpenBSD: sdmmcreg.h,v 1.4 2009/01/09 10:55:22 jsg Exp $	*/
      3       1.1    nonaka 
      4       1.1    nonaka /*
      5       1.1    nonaka  * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org>
      6       1.1    nonaka  *
      7       1.1    nonaka  * Permission to use, copy, modify, and distribute this software for any
      8       1.1    nonaka  * purpose with or without fee is hereby granted, provided that the above
      9       1.1    nonaka  * copyright notice and this permission notice appear in all copies.
     10       1.1    nonaka  *
     11       1.1    nonaka  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     12       1.1    nonaka  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     13       1.1    nonaka  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     14       1.1    nonaka  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     15       1.1    nonaka  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     16       1.1    nonaka  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     17       1.1    nonaka  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     18       1.1    nonaka  */
     19       1.1    nonaka 
     20       1.1    nonaka #ifndef	_SDMMCREG_H_
     21       1.1    nonaka #define	_SDMMCREG_H_
     22       1.1    nonaka 
     23       1.1    nonaka /* MMC commands */				/* response type */
     24       1.1    nonaka #define MMC_GO_IDLE_STATE		0	/* R0 */
     25       1.1    nonaka #define MMC_SEND_OP_COND		1	/* R3 */
     26       1.1    nonaka #define MMC_ALL_SEND_CID		2	/* R2 */
     27       1.2    nonaka #define MMC_SET_RELATIVE_ADDR 	  	3	/* R1 */
     28       1.2    nonaka #define MMC_SWITCH			6	/* R1b */
     29       1.1    nonaka #define MMC_SELECT_CARD			7	/* R1 */
     30       1.2    nonaka #define MMC_SEND_EXT_CSD		8	/* R1 */
     31       1.1    nonaka #define MMC_SEND_CSD			9	/* R2 */
     32       1.2    nonaka #define MMC_SEND_CID			10	/* R2 */
     33       1.1    nonaka #define MMC_STOP_TRANSMISSION		12	/* R1b */
     34       1.1    nonaka #define MMC_SEND_STATUS			13	/* R1 */
     35       1.1    nonaka #define MMC_INACTIVE_STATE		15	/* R0 */
     36       1.1    nonaka #define MMC_SET_BLOCKLEN		16	/* R1 */
     37       1.1    nonaka #define MMC_READ_BLOCK_SINGLE		17	/* R1 */
     38       1.1    nonaka #define MMC_READ_BLOCK_MULTIPLE		18	/* R1 */
     39      1.19  jmcneill #define MMC_SEND_TUNING_BLOCK		19	/* R1 */
     40      1.19  jmcneill #define MMC_SEND_TUNING_BLOCK_HS200	21	/* R1 */
     41       1.1    nonaka #define MMC_SET_BLOCK_COUNT		23	/* R1 */
     42       1.1    nonaka #define MMC_WRITE_BLOCK_SINGLE		24	/* R1 */
     43       1.1    nonaka #define MMC_WRITE_BLOCK_MULTIPLE	25	/* R1 */
     44       1.2    nonaka #define MMC_PROGRAM_CSD			27	/* R1 */
     45       1.2    nonaka #define MMC_SET_WRITE_PROT		28	/* R1b */
     46       1.2    nonaka #define MMC_SET_CLR_WRITE_PROT		29	/* R1b */
     47       1.2    nonaka #define MMC_SET_SEND_WRITE_PROT		30	/* R1 */
     48       1.2    nonaka #define MMC_TAG_SECTOR_START		32	/* R1 */
     49       1.2    nonaka #define MMC_TAG_SECTOR_END		33	/* R1 */
     50       1.2    nonaka #define MMC_UNTAG_SECTOR		34	/* R1 */
     51       1.2    nonaka #define MMC_TAG_ERASE_GROUP_START	35	/* R1 */
     52       1.2    nonaka #define MMC_TAG_ERASE_GROUP_END		36	/* R1 */
     53       1.2    nonaka #define MMC_UNTAG_ERASE_GROUP		37	/* R1 */
     54       1.2    nonaka #define MMC_ERASE			38	/* R1b */
     55       1.2    nonaka #define MMC_LOCK_UNLOCK			42	/* R1b */
     56       1.1    nonaka #define MMC_APP_CMD			55	/* R1 */
     57       1.2    nonaka #define MMC_READ_OCR			58	/* R3 */
     58       1.1    nonaka 
     59       1.2    nonaka /* SD commands */			/* response type */
     60       1.3    nonaka #define SD_SEND_RELATIVE_ADDR 	  	3	/* R6 */
     61       1.5  kiyohara #define SD_SEND_SWITCH_FUNC		6	/* R1 */
     62       1.1    nonaka #define SD_SEND_IF_COND			8	/* R7 */
     63      1.16  jmcneill #define SD_VOLTAGE_SWITCH		11	/* R1 */
     64  1.29.6.1       snj #define SD_ERASE_WR_BLK_START		32	/* R1 */
     65  1.29.6.1       snj #define SD_ERASE_WR_BLK_END		33	/* R1 */
     66       1.1    nonaka 
     67       1.1    nonaka /* SD application commands */			/* response type */
     68       1.1    nonaka #define SD_APP_SET_BUS_WIDTH		6	/* R1 */
     69       1.9  jakllsch #define SD_APP_SD_STATUS		13	/* R1 */
     70       1.1    nonaka #define SD_APP_OP_COND			41	/* R3 */
     71       1.2    nonaka #define SD_APP_SEND_SCR			51	/* R1 */
     72       1.1    nonaka 
     73  1.29.6.1       snj /* SD erase arguments */
     74  1.29.6.1       snj #define SD_ERASE_DISCARD		0x00000001
     75  1.29.6.1       snj #define SD_ERASE_FULE			0x00000002
     76  1.29.6.1       snj 
     77       1.1    nonaka /* OCR bits */
     78       1.1    nonaka #define MMC_OCR_MEM_READY		(1U<<31)/* memory power-up status bit */
     79      1.20  jmcneill #define MMC_OCR_HCS			(1<<30)	/* SD only */
     80      1.20  jmcneill #define MMC_OCR_ACCESS_MODE_MASK	(3<<29)	/* MMC only */
     81      1.20  jmcneill #define MMC_OCR_ACCESS_MODE_BYTE	(0<<29)	/* MMC only */
     82      1.20  jmcneill #define MMC_OCR_ACCESS_MODE_SECTOR	(2<<29)	/* MMC only */
     83      1.16  jmcneill #define MMC_OCR_S18A			(1<<24)
     84       1.1    nonaka #define MMC_OCR_3_5V_3_6V		(1<<23)
     85       1.1    nonaka #define MMC_OCR_3_4V_3_5V		(1<<22)
     86       1.1    nonaka #define MMC_OCR_3_3V_3_4V		(1<<21)
     87       1.1    nonaka #define MMC_OCR_3_2V_3_3V		(1<<20)
     88       1.1    nonaka #define MMC_OCR_3_1V_3_2V		(1<<19)
     89       1.1    nonaka #define MMC_OCR_3_0V_3_1V		(1<<18)
     90       1.1    nonaka #define MMC_OCR_2_9V_3_0V		(1<<17)
     91       1.1    nonaka #define MMC_OCR_2_8V_2_9V		(1<<16)
     92       1.1    nonaka #define MMC_OCR_2_7V_2_8V		(1<<15)
     93       1.1    nonaka #define MMC_OCR_2_6V_2_7V		(1<<14)
     94       1.1    nonaka #define MMC_OCR_2_5V_2_6V		(1<<13)
     95       1.1    nonaka #define MMC_OCR_2_4V_2_5V		(1<<12)
     96       1.1    nonaka #define MMC_OCR_2_3V_2_4V		(1<<11)
     97       1.1    nonaka #define MMC_OCR_2_2V_2_3V		(1<<10)
     98       1.1    nonaka #define MMC_OCR_2_1V_2_2V		(1<<9)
     99       1.1    nonaka #define MMC_OCR_2_0V_2_1V		(1<<8)
    100      1.22    nonaka #define MMC_OCR_1_65V_1_95V		(1<<7)
    101       1.1    nonaka 
    102       1.1    nonaka /* R1 response type bits */
    103       1.1    nonaka #define MMC_R1_READY_FOR_DATA		(1<<8)	/* ready for next transfer */
    104      1.21  jmcneill #define MMC_R1_SWITCH_ERROR		(1<<7)	/* switch command failed */
    105       1.1    nonaka #define MMC_R1_APP_CMD			(1<<5)	/* app. commands supported */
    106       1.1    nonaka 
    107       1.1    nonaka /* 48-bit response decoding (32 bits w/o CRC) */
    108       1.1    nonaka #define MMC_R1(resp)			((resp)[0])
    109       1.1    nonaka #define MMC_R3(resp)			((resp)[0])
    110       1.1    nonaka #define SD_R6(resp)			((resp)[0])
    111       1.1    nonaka #define MMC_R7(resp)			((resp)[0])
    112       1.4    nonaka #define MMC_SPI_R1(resp)		((resp)[0])
    113       1.4    nonaka #define MMC_SPI_R7(resp)		((resp)[1])
    114       1.1    nonaka 
    115       1.1    nonaka /* RCA argument and response */
    116       1.1    nonaka #define MMC_ARG_RCA(rca)		((rca) << 16)
    117       1.1    nonaka #define SD_R6_RCA(resp)			(SD_R6((resp)) >> 16)
    118       1.1    nonaka 
    119       1.1    nonaka /* bus width argument */
    120       1.1    nonaka #define SD_ARG_BUS_WIDTH_1		0
    121       1.1    nonaka #define SD_ARG_BUS_WIDTH_4		2
    122       1.1    nonaka 
    123       1.4    nonaka /* EXT_CSD fields */
    124      1.29    nonaka #define EXT_CSD_RST_N_FUNCTION		162	/* R/W */
    125      1.23    nonaka #define EXT_CSD_BUS_WIDTH		183	/* W/E_P */
    126      1.23    nonaka #define EXT_CSD_HS_TIMING		185	/* R/W/E_P */
    127      1.23    nonaka #define EXT_CSD_REV			192	/* R */
    128      1.23    nonaka #define EXT_CSD_STRUCTURE		194	/* R */
    129      1.23    nonaka #define EXT_CSD_CARD_TYPE		196	/* R */
    130      1.23    nonaka #define EXT_CSD_SEC_COUNT		212	/* R */
    131       1.4    nonaka 
    132       1.4    nonaka /* EXT_CSD field definitions */
    133       1.4    nonaka #define EXT_CSD_CMD_SET_NORMAL		(1U << 0)
    134       1.4    nonaka #define EXT_CSD_CMD_SET_SECURE		(1U << 1)
    135       1.4    nonaka #define EXT_CSD_CMD_SET_CPSECURE	(1U << 2)
    136       1.4    nonaka 
    137       1.4    nonaka /* EXT_CSD_BUS_WIDTH */
    138       1.4    nonaka #define EXT_CSD_BUS_WIDTH_1		0	/* 1 bit mode */
    139       1.4    nonaka #define EXT_CSD_BUS_WIDTH_4		1	/* 4 bit mode */
    140       1.4    nonaka #define EXT_CSD_BUS_WIDTH_8		2	/* 8 bit mode */
    141      1.24    nonaka #define EXT_CSD_BUS_WIDTH_4_DDR		5	/* 4 bit mode (DDR) */
    142      1.24    nonaka #define EXT_CSD_BUS_WIDTH_8_DDR		6	/* 8 bit mode (DDR) */
    143       1.4    nonaka 
    144      1.28    nonaka /* EXT_CSD_HS_TIMING */
    145      1.28    nonaka #define EXT_CSD_HS_TIMING_LEGACY	0
    146      1.28    nonaka #define EXT_CSD_HS_TIMING_HIGHSPEED	1
    147      1.28    nonaka #define EXT_CSD_HS_TIMING_HS200		2
    148      1.28    nonaka #define EXT_CSD_HS_TIMING_HS400		3
    149      1.28    nonaka 
    150       1.5  kiyohara /* EXT_CSD_STRUCTURE */
    151       1.5  kiyohara #define EXT_CSD_STRUCTURE_VER_1_0	0	/* CSD Version No.1.0 */
    152       1.5  kiyohara #define EXT_CSD_STRUCTURE_VER_1_1	1	/* CSD Version No.1.1 */
    153       1.5  kiyohara #define EXT_CSD_STRUCTURE_VER_1_2	2	/* Version 4.1-4.2-4.3 */
    154       1.5  kiyohara 
    155       1.5  kiyohara /* EXT_CSD_CARD_TYPE */
    156      1.25    nonaka #define EXT_CSD_CARD_TYPE_F_26M		(1 << 0) /* HS 26 MHz */
    157      1.25    nonaka #define EXT_CSD_CARD_TYPE_F_52M		(1 << 1) /* HS 52 MHz */
    158      1.27    nonaka #define EXT_CSD_CARD_TYPE_F_DDR52_1_8V	(1 << 2) /* HS DDR 52 MHz 1.8V or 3V */
    159      1.27    nonaka #define EXT_CSD_CARD_TYPE_F_DDR52_1_2V	(1 << 3) /* HS DDR 52 MHz 1.2V */
    160      1.25    nonaka #define EXT_CSD_CARD_TYPE_F_HS200_1_8V	(1 << 4) /* HS200 SDR 200 MHz 1.8V */
    161      1.25    nonaka #define EXT_CSD_CARD_TYPE_F_HS200_1_2V	(1 << 5) /* HS200 SDR 200 MHz 1.2V */
    162      1.25    nonaka #define EXT_CSD_CARD_TYPE_F_HS400_1_8V	(1 << 6) /* HS400 DDR 200 MHz 1.8V */
    163      1.25    nonaka #define EXT_CSD_CARD_TYPE_F_HS400_1_2V	(1 << 7) /* HS400 DDR 200 MHz 1.2V */
    164       1.5  kiyohara 
    165      1.29    nonaka /* EXT_CSD_RST_N_FUNCTION */
    166      1.29    nonaka #define	EXT_CSD_RST_N_TMP_DISABLED	0x00
    167      1.29    nonaka #define	EXT_CSD_RST_N_PERM_ENABLED	0x01
    168      1.29    nonaka #define	EXT_CSD_RST_N_PERM_DISABLED	0x02
    169      1.29    nonaka #define	EXT_CSD_RST_N_MASK		0x03
    170      1.29    nonaka 
    171       1.4    nonaka /* MMC_SWITCH access mode */
    172       1.4    nonaka #define MMC_SWITCH_MODE_CMD_SET		0x00	/* Change the command set */
    173       1.4    nonaka #define MMC_SWITCH_MODE_SET_BITS	0x01	/* Set bits in value */
    174       1.4    nonaka #define MMC_SWITCH_MODE_CLEAR_BITS	0x02	/* Clear bits in value */
    175       1.4    nonaka #define MMC_SWITCH_MODE_WRITE_BYTE	0x03	/* Set target to value */
    176       1.4    nonaka 
    177       1.4    nonaka /* SPI mode reports R1/R2(SEND_STATUS) status. */
    178       1.4    nonaka #define R1_SPI_IDLE		(1 << 0)
    179       1.4    nonaka #define R1_SPI_ERASE_RESET	(1 << 1)
    180       1.4    nonaka #define R1_SPI_ILLEGAL_COMMAND	(1 << 2)
    181       1.4    nonaka #define R1_SPI_COM_CRC		(1 << 3)
    182       1.4    nonaka #define R1_SPI_ERASE_SEQ	(1 << 4)
    183       1.4    nonaka #define R1_SPI_ADDRESS		(1 << 5)
    184       1.4    nonaka #define R1_SPI_PARAMETER	(1 << 6)
    185       1.4    nonaka /* R1 bit 7 is always zero */
    186       1.4    nonaka #define R2_SPI_CARD_LOCKED	(1 << 8)
    187       1.4    nonaka #define R2_SPI_WP_ERASE_SKIP	(1 << 9)	/* or lock/unlock fail */
    188       1.4    nonaka #define R2_SPI_LOCK_UNLOCK_FAIL	R2_SPI_WP_ERASE_SKIP
    189       1.4    nonaka #define R2_SPI_ERROR		(1 << 10)
    190       1.4    nonaka #define R2_SPI_CC_ERROR		(1 << 11)
    191       1.4    nonaka #define R2_SPI_CARD_ECC_ERROR	(1 << 12)
    192       1.4    nonaka #define R2_SPI_WP_VIOLATION	(1 << 13)
    193       1.4    nonaka #define R2_SPI_ERASE_PARAM	(1 << 14)
    194       1.4    nonaka #define R2_SPI_OUT_OF_RANGE	(1 << 15)	/* or CSD overwrite */
    195       1.4    nonaka #define R2_SPI_CSD_OVERWRITE	R2_SPI_OUT_OF_RANGE
    196       1.4    nonaka 
    197       1.1    nonaka /* MMC R2 response (CSD) */
    198       1.1    nonaka #define MMC_CSD_CSDVER(resp)		MMC_RSP_BITS((resp), 126, 2)
    199       1.6    nonaka #define  MMC_CSD_CSDVER_1_0		0
    200       1.6    nonaka #define  MMC_CSD_CSDVER_1_1		1
    201       1.6    nonaka #define  MMC_CSD_CSDVER_1_2		2 /* MMC 4.1 - 4.2 - 4.3 */
    202       1.7    nonaka #define  MMC_CSD_CSDVER_EXT_CSD		3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
    203       1.1    nonaka #define MMC_CSD_MMCVER(resp)		MMC_RSP_BITS((resp), 122, 4)
    204       1.1    nonaka #define  MMC_CSD_MMCVER_1_0		0 /* MMC 1.0 - 1.2 */
    205       1.1    nonaka #define  MMC_CSD_MMCVER_1_4		1 /* MMC 1.4 */
    206       1.1    nonaka #define  MMC_CSD_MMCVER_2_0		2 /* MMC 2.0 - 2.2 */
    207       1.1    nonaka #define  MMC_CSD_MMCVER_3_1		3 /* MMC 3.1 - 3.3 */
    208       1.6    nonaka #define  MMC_CSD_MMCVER_4_0		4 /* MMC 4.1 - 4.2 - 4.3 */
    209       1.1    nonaka #define MMC_CSD_TAAC(resp)		MMC_RSP_BITS((resp), 112, 8)
    210       1.1    nonaka #define MMC_CSD_TAAC_MANT(resp)		MMC_RSP_BITS((resp), 115, 4)
    211       1.1    nonaka #define MMC_CSD_TAAC_EXP(resp)		MMC_RSP_BITS((resp), 112, 3)
    212       1.1    nonaka #define MMC_CSD_NSAC(resp)		MMC_RSP_BITS((resp), 104, 8)
    213       1.1    nonaka #define MMC_CSD_TRAN_SPEED(resp)	MMC_RSP_BITS((resp), 96, 8)
    214       1.1    nonaka #define MMC_CSD_TRAN_SPEED_MANT(resp)	MMC_RSP_BITS((resp), 99, 4)
    215       1.1    nonaka #define MMC_CSD_TRAN_SPEED_EXP(resp)	MMC_RSP_BITS((resp), 96, 3)
    216       1.1    nonaka #define MMC_CSD_READ_BL_LEN(resp)	MMC_RSP_BITS((resp), 80, 4)
    217       1.1    nonaka #define MMC_CSD_C_SIZE(resp)		MMC_RSP_BITS((resp), 62, 12)
    218       1.1    nonaka #define MMC_CSD_CAPACITY(resp)		((MMC_CSD_C_SIZE((resp))+1) << \
    219       1.1    nonaka 					 (MMC_CSD_C_SIZE_MULT((resp))+2))
    220       1.1    nonaka #define MMC_CSD_C_SIZE_MULT(resp)	MMC_RSP_BITS((resp), 47, 3)
    221       1.1    nonaka #define MMC_CSD_R2W_FACTOR(resp)	MMC_RSP_BITS((resp), 26, 3)
    222       1.1    nonaka #define MMC_CSD_WRITE_BL_LEN(resp)	MMC_RSP_BITS((resp), 22, 4)
    223       1.1    nonaka 
    224       1.1    nonaka /* MMC v1 R2 response (CID) */
    225       1.1    nonaka #define MMC_CID_MID_V1(resp)		MMC_RSP_BITS((resp), 104, 24)
    226       1.1    nonaka #define MMC_CID_PNM_V1_CPY(resp, pnm)					\
    227       1.1    nonaka 	do {								\
    228       1.1    nonaka 		(pnm)[0] = MMC_RSP_BITS((resp), 96, 8);			\
    229       1.1    nonaka 		(pnm)[1] = MMC_RSP_BITS((resp), 88, 8);			\
    230       1.1    nonaka 		(pnm)[2] = MMC_RSP_BITS((resp), 80, 8);			\
    231       1.1    nonaka 		(pnm)[3] = MMC_RSP_BITS((resp), 72, 8);			\
    232       1.1    nonaka 		(pnm)[4] = MMC_RSP_BITS((resp), 64, 8);			\
    233       1.1    nonaka 		(pnm)[5] = MMC_RSP_BITS((resp), 56, 8);			\
    234       1.1    nonaka 		(pnm)[6] = MMC_RSP_BITS((resp), 48, 8);			\
    235       1.1    nonaka 		(pnm)[7] = '\0';					\
    236       1.1    nonaka 	} while (/*CONSTCOND*/0)
    237       1.1    nonaka #define MMC_CID_REV_V1(resp)		MMC_RSP_BITS((resp), 40, 8)
    238       1.1    nonaka #define MMC_CID_PSN_V1(resp)		MMC_RSP_BITS((resp), 16, 24)
    239       1.1    nonaka #define MMC_CID_MDT_V1(resp)		MMC_RSP_BITS((resp), 8, 8)
    240       1.1    nonaka 
    241       1.1    nonaka /* MMC v2 R2 response (CID) */
    242       1.1    nonaka #define MMC_CID_MID_V2(resp)		MMC_RSP_BITS((resp), 120, 8)
    243       1.1    nonaka #define MMC_CID_OID_V2(resp)		MMC_RSP_BITS((resp), 104, 16)
    244       1.1    nonaka #define MMC_CID_PNM_V2_CPY(resp, pnm)					\
    245       1.1    nonaka 	do {								\
    246       1.1    nonaka 		(pnm)[0] = MMC_RSP_BITS((resp), 96, 8);			\
    247       1.1    nonaka 		(pnm)[1] = MMC_RSP_BITS((resp), 88, 8);			\
    248       1.1    nonaka 		(pnm)[2] = MMC_RSP_BITS((resp), 80, 8);			\
    249       1.1    nonaka 		(pnm)[3] = MMC_RSP_BITS((resp), 72, 8);			\
    250       1.1    nonaka 		(pnm)[4] = MMC_RSP_BITS((resp), 64, 8);			\
    251       1.1    nonaka 		(pnm)[5] = MMC_RSP_BITS((resp), 56, 8);			\
    252       1.1    nonaka 		(pnm)[6] = '\0';					\
    253       1.1    nonaka 	} while (/*CONSTCOND*/0)
    254       1.1    nonaka #define MMC_CID_PSN_V2(resp)		MMC_RSP_BITS((resp), 16, 32)
    255       1.1    nonaka 
    256       1.1    nonaka /* SD R2 response (CSD) */
    257       1.1    nonaka #define SD_CSD_CSDVER(resp)		MMC_RSP_BITS((resp), 126, 2)
    258       1.1    nonaka #define  SD_CSD_CSDVER_1_0		0
    259       1.1    nonaka #define  SD_CSD_CSDVER_2_0		1
    260       1.1    nonaka #define SD_CSD_MMCVER(resp)		MMC_RSP_BITS((resp), 122, 4)
    261       1.1    nonaka #define SD_CSD_TAAC(resp)		MMC_RSP_BITS((resp), 112, 8)
    262       1.1    nonaka #define SD_CSD_TAAC_EXP(resp)		MMC_RSP_BITS((resp), 115, 4)
    263       1.1    nonaka #define SD_CSD_TAAC_MANT(resp)		MMC_RSP_BITS((resp), 112, 3)
    264       1.1    nonaka #define  SD_CSD_TAAC_1_5_MSEC		0x26
    265       1.1    nonaka #define SD_CSD_NSAC(resp)		MMC_RSP_BITS((resp), 104, 8)
    266       1.1    nonaka #define SD_CSD_SPEED(resp)		MMC_RSP_BITS((resp), 96, 8)
    267       1.1    nonaka #define SD_CSD_SPEED_MANT(resp)		MMC_RSP_BITS((resp), 99, 4)
    268       1.1    nonaka #define SD_CSD_SPEED_EXP(resp)		MMC_RSP_BITS((resp), 96, 3)
    269       1.1    nonaka #define  SD_CSD_SPEED_25_MHZ		0x32
    270       1.1    nonaka #define  SD_CSD_SPEED_50_MHZ		0x5a
    271       1.1    nonaka #define SD_CSD_CCC(resp)		MMC_RSP_BITS((resp), 84, 12)
    272       1.5  kiyohara #define  SD_CSD_CCC_BASIC		(1 << 0)	/* basic */
    273       1.5  kiyohara #define  SD_CSD_CCC_BR			(1 << 2)	/* block read */
    274       1.5  kiyohara #define  SD_CSD_CCC_BW			(1 << 4)	/* block write */
    275       1.5  kiyohara #define  SD_CSD_CCC_ERACE		(1 << 5)	/* erase */
    276       1.5  kiyohara #define  SD_CSD_CCC_WP			(1 << 6)	/* write protection */
    277       1.5  kiyohara #define  SD_CSD_CCC_LC			(1 << 7)	/* lock card */
    278       1.5  kiyohara #define  SD_CSD_CCC_AS			(1 << 8)	/*application specific*/
    279       1.5  kiyohara #define  SD_CSD_CCC_IOM			(1 << 9)	/* I/O mode */
    280       1.5  kiyohara #define  SD_CSD_CCC_SWITCH		(1 << 10)	/* switch */
    281       1.1    nonaka #define SD_CSD_READ_BL_LEN(resp)	MMC_RSP_BITS((resp), 80, 4)
    282       1.1    nonaka #define SD_CSD_READ_BL_PARTIAL(resp)	MMC_RSP_BITS((resp), 79, 1)
    283       1.1    nonaka #define SD_CSD_WRITE_BLK_MISALIGN(resp)	MMC_RSP_BITS((resp), 78, 1)
    284       1.1    nonaka #define SD_CSD_READ_BLK_MISALIGN(resp)	MMC_RSP_BITS((resp), 77, 1)
    285       1.1    nonaka #define SD_CSD_DSR_IMP(resp)		MMC_RSP_BITS((resp), 76, 1)
    286       1.1    nonaka #define SD_CSD_C_SIZE(resp)		MMC_RSP_BITS((resp), 62, 12)
    287       1.1    nonaka #define SD_CSD_CAPACITY(resp)		((SD_CSD_C_SIZE((resp))+1) << \
    288       1.1    nonaka 					 (SD_CSD_C_SIZE_MULT((resp))+2))
    289       1.1    nonaka #define SD_CSD_VDD_R_CURR_MIN(resp)	MMC_RSP_BITS((resp), 59, 3)
    290       1.1    nonaka #define SD_CSD_VDD_R_CURR_MAX(resp)	MMC_RSP_BITS((resp), 56, 3)
    291       1.1    nonaka #define SD_CSD_VDD_W_CURR_MIN(resp)	MMC_RSP_BITS((resp), 53, 3)
    292       1.1    nonaka #define SD_CSD_VDD_W_CURR_MAX(resp)	MMC_RSP_BITS((resp), 50, 3)
    293       1.1    nonaka #define  SD_CSD_VDD_RW_CURR_100mA	0x7
    294       1.1    nonaka #define  SD_CSD_VDD_RW_CURR_80mA	0x6
    295       1.1    nonaka #define SD_CSD_V2_C_SIZE(resp)		MMC_RSP_BITS((resp), 48, 22)
    296       1.1    nonaka #define SD_CSD_V2_CAPACITY(resp)	((SD_CSD_V2_C_SIZE((resp))+1) << 10)
    297       1.1    nonaka #define SD_CSD_V2_BL_LEN		0x9 /* 512 */
    298       1.1    nonaka #define SD_CSD_C_SIZE_MULT(resp)	MMC_RSP_BITS((resp), 47, 3)
    299       1.1    nonaka #define SD_CSD_ERASE_BLK_EN(resp)	MMC_RSP_BITS((resp), 46, 1)
    300       1.1    nonaka #define SD_CSD_SECTOR_SIZE(resp)	MMC_RSP_BITS((resp), 39, 7) /* +1 */
    301       1.1    nonaka #define SD_CSD_WP_GRP_SIZE(resp)	MMC_RSP_BITS((resp), 32, 7) /* +1 */
    302       1.1    nonaka #define SD_CSD_WP_GRP_ENABLE(resp)	MMC_RSP_BITS((resp), 31, 1)
    303       1.1    nonaka #define SD_CSD_R2W_FACTOR(resp)		MMC_RSP_BITS((resp), 26, 3)
    304       1.1    nonaka #define SD_CSD_WRITE_BL_LEN(resp)	MMC_RSP_BITS((resp), 22, 4)
    305       1.1    nonaka #define  SD_CSD_RW_BL_LEN_2G		0xa
    306       1.1    nonaka #define  SD_CSD_RW_BL_LEN_1G		0x9
    307       1.1    nonaka #define SD_CSD_WRITE_BL_PARTIAL(resp)	MMC_RSP_BITS((resp), 21, 1)
    308       1.1    nonaka #define SD_CSD_FILE_FORMAT_GRP(resp)	MMC_RSP_BITS((resp), 15, 1)
    309       1.1    nonaka #define SD_CSD_COPY(resp)		MMC_RSP_BITS((resp), 14, 1)
    310       1.1    nonaka #define SD_CSD_PERM_WRITE_PROTECT(resp)	MMC_RSP_BITS((resp), 13, 1)
    311       1.1    nonaka #define SD_CSD_TMP_WRITE_PROTECT(resp)	MMC_RSP_BITS((resp), 12, 1)
    312       1.1    nonaka #define SD_CSD_FILE_FORMAT(resp)	MMC_RSP_BITS((resp), 10, 2)
    313       1.1    nonaka 
    314       1.1    nonaka /* SD R2 response (CID) */
    315       1.1    nonaka #define SD_CID_MID(resp)		MMC_RSP_BITS((resp), 120, 8)
    316       1.1    nonaka #define SD_CID_OID(resp)		MMC_RSP_BITS((resp), 104, 16)
    317       1.1    nonaka #define SD_CID_PNM_CPY(resp, pnm)					\
    318       1.1    nonaka 	do {								\
    319       1.1    nonaka 		(pnm)[0] = MMC_RSP_BITS((resp), 96, 8);			\
    320       1.1    nonaka 		(pnm)[1] = MMC_RSP_BITS((resp), 88, 8);			\
    321       1.1    nonaka 		(pnm)[2] = MMC_RSP_BITS((resp), 80, 8);			\
    322       1.1    nonaka 		(pnm)[3] = MMC_RSP_BITS((resp), 72, 8);			\
    323       1.1    nonaka 		(pnm)[4] = MMC_RSP_BITS((resp), 64, 8);			\
    324       1.1    nonaka 		(pnm)[5] = '\0';					\
    325       1.1    nonaka 	} while (/*CONSTCOND*/0)
    326       1.1    nonaka #define SD_CID_REV(resp)		MMC_RSP_BITS((resp), 56, 8)
    327       1.1    nonaka #define SD_CID_PSN(resp)		MMC_RSP_BITS((resp), 24, 32)
    328       1.1    nonaka #define SD_CID_MDT(resp)		MMC_RSP_BITS((resp), 8, 12)
    329       1.1    nonaka 
    330       1.1    nonaka /* SCR (SD Configuration Register) */
    331       1.2    nonaka #define SCR_STRUCTURE(scr)		MMC_RSP_BITS((scr), 60, 4)
    332       1.2    nonaka #define  SCR_STRUCTURE_VER_1_0		0 /* Version 1.0 */
    333       1.2    nonaka #define SCR_SD_SPEC(scr)		MMC_RSP_BITS((scr), 56, 4)
    334       1.5  kiyohara #define  SCR_SD_SPEC_VER_1_0		0 /* Version 1.0 and 1.01 */
    335       1.5  kiyohara #define  SCR_SD_SPEC_VER_1_10		1 /* Version 1.10 */
    336       1.5  kiyohara #define  SCR_SD_SPEC_VER_2		2 /* Version 2.00 or Version 3.0X */
    337       1.2    nonaka #define SCR_DATA_STAT_AFTER_ERASE(scr)	MMC_RSP_BITS((scr), 55, 1)
    338       1.2    nonaka #define SCR_SD_SECURITY(scr)		MMC_RSP_BITS((scr), 52, 3)
    339       1.2    nonaka #define  SCR_SD_SECURITY_NONE		0 /* no security */
    340       1.2    nonaka #define  SCR_SD_SECURITY_1_0		1 /* security protocol 1.0 */
    341       1.2    nonaka #define  SCR_SD_SECURITY_1_0_2		2 /* security protocol 1.0 */
    342       1.2    nonaka #define SCR_SD_BUS_WIDTHS(scr)		MMC_RSP_BITS((scr), 48, 4)
    343       1.2    nonaka #define  SCR_SD_BUS_WIDTHS_1BIT		(1 << 0) /* 1bit (DAT0) */
    344       1.2    nonaka #define  SCR_SD_BUS_WIDTHS_4BIT		(1 << 2) /* 4bit (DAT0-3) */
    345      1.10      matt #define SCR_SD_SPEC3(scr)		MMC_RSP_BITS((scr), 47, 1)
    346      1.10      matt #define SCR_EX_SECURITY(scr)		MMC_RSP_BITS((scr), 43, 4)
    347      1.10      matt #define SCR_RESERVED(scr)		MMC_RSP_BITS((scr), 34, 9)
    348      1.10      matt #define SCR_CMD_SUPPORT_CMD23(scr)	MMC_RSP_BITS((scr), 33, 1)
    349      1.10      matt #define SCR_CMD_SUPPORT_CMD20(scr)	MMC_RSP_BITS((scr), 32, 1)
    350       1.2    nonaka #define SCR_RESERVED2(scr)		MMC_RSP_BITS((scr), 0, 32)
    351       1.1    nonaka 
    352  1.29.6.1       snj /* SSR (SD Status Register) */
    353  1.29.6.1       snj #define SSR_DAT_BUS_WIDTH(resp)		__bitfield((resp), 510, 2)
    354  1.29.6.1       snj #define  SSR_DAT_BUS_WIDTH_1		0
    355  1.29.6.1       snj #define  SSR_DAT_BUS_WIDTH_4		2
    356  1.29.6.1       snj #define SSR_SECURED_MODE(resp)		__bitfield((resp), 509, 1)
    357  1.29.6.1       snj #define SSR_SD_CARD_TYPE(resp)		__bitfield((resp), 480, 16)
    358  1.29.6.1       snj #define  SSR_SD_CARD_TYPE_RDWR		0
    359  1.29.6.1       snj #define  SSR_SD_CARD_TYPE_ROM		1
    360  1.29.6.1       snj #define  SSR_SD_CARD_TYPE_OTP		2
    361  1.29.6.1       snj #define SSR_SIZE_OF_PROTECTED_AREA(resp) __bitfield((resp), 448, 32)
    362  1.29.6.1       snj #define SSR_SPEED_CLASS(resp)		__bitfield((resp), 440, 8)
    363  1.29.6.1       snj #define  SSR_SPEED_CLASS_0		0
    364  1.29.6.1       snj #define  SSR_SPEED_CLASS_2		1
    365  1.29.6.1       snj #define  SSR_SPEED_CLASS_4		2
    366  1.29.6.1       snj #define  SSR_SPEED_CLASS_6		3
    367  1.29.6.1       snj #define  SSR_SPEED_CLASS_10		4
    368  1.29.6.1       snj #define SSR_PERFORMANCE_MOVE(resp)	__bitfield((resp), 432, 8)
    369  1.29.6.1       snj #define SSR_AU_SIZE(resp)		__bitfield((resp), 428, 4)
    370  1.29.6.1       snj #define SSR_ERASE_SIZE(resp)		__bitfield((resp), 408, 16)
    371  1.29.6.1       snj #define SSR_ERASE_TIMEOUT(resp)		__bitfield((resp), 402, 6)
    372  1.29.6.1       snj #define SSR_ERASE_OFFSET(resp)		__bitfield((resp), 400, 2)
    373  1.29.6.1       snj #define SSR_UHS_SPEED_GRADE(resp)	__bitfield((resp), 396, 4)
    374  1.29.6.1       snj #define  SSR_UHS_SPEED_GRADE_10MB	1
    375  1.29.6.1       snj #define  SSR_UHS_SPEED_GRADE_30MB	3
    376  1.29.6.1       snj #define SSR_UHS_AU_SIZE(resp)		__bitfield((resp), 392, 4)
    377  1.29.6.1       snj #define SSR_VIDEO_SPEED_CLASS(resp)	__bitfield((resp), 384, 8)
    378  1.29.6.1       snj #define SSR_VSC_AU_SIZE(resp)		__bitfield((resp), 368, 10)
    379  1.29.6.1       snj #define SSR_SUS_ADDR(resp)		__bitfield((resp), 346, 22)
    380  1.29.6.1       snj #define SSR_APP_PERF_CLASS(resp)	__bitfield((resp), 336, 4)
    381  1.29.6.1       snj #define  SSR_APP_PERF_CLASS_UNSUPPORTED	0
    382  1.29.6.1       snj #define  SSR_APP_PERF_CLASS_A1		1
    383  1.29.6.1       snj #define  SSR_APP_PERF_CLASS_A2		2
    384  1.29.6.1       snj #define SSR_PERFORMANCE_ENHANCE(resp)	__bitfield((resp), 328, 8)
    385  1.29.6.1       snj #define SSR_DISCARD_SUPPORT(resp)	__bitfield((resp), 313, 1)
    386  1.29.6.1       snj #define SSR_FULE_SUPPORT(resp)		__bitfield((resp), 312, 1)
    387  1.29.6.1       snj 
    388       1.5  kiyohara /* Status of Switch Function */
    389       1.5  kiyohara #define SFUNC_STATUS_GROUP(status, group) \
    390      1.13  jakllsch 	(__bitfield((uint32_t *)(status), 400 + (group - 1) * 16, 16))
    391       1.5  kiyohara 
    392      1.18  jmcneill #define SD_ACCESS_MODE_SDR12	0
    393      1.18  jmcneill #define SD_ACCESS_MODE_SDR25	1
    394      1.18  jmcneill #define SD_ACCESS_MODE_SDR50	2
    395      1.18  jmcneill #define SD_ACCESS_MODE_SDR104	3
    396      1.18  jmcneill #define SD_ACCESS_MODE_DDR50	4
    397      1.18  jmcneill 
    398      1.12      matt /* This assumes the response fields are in host byte order in 32-bit units.  */
    399       1.1    nonaka #define MMC_RSP_BITS(resp, start, len)	__bitfield((resp), (start)-8, (len))
    400      1.10      matt static inline uint32_t
    401      1.10      matt __bitfield(const uint32_t *src, size_t start, size_t len)
    402       1.1    nonaka {
    403      1.13  jakllsch 	if (start + len > 512 || len == 0 || len > 32)
    404      1.10      matt 		return 0;
    405      1.10      matt 
    406      1.10      matt 	src += start / 32;
    407      1.10      matt 	start %= 32;
    408       1.1    nonaka 
    409      1.11      matt 	uint32_t dst = src[0] >> start;
    410       1.1    nonaka 
    411      1.10      matt 	if (__predict_false((start + len - 1) / 32 != start / 32)) {
    412      1.11      matt 		dst |= src[1] << (32 - start);
    413       1.1    nonaka 	}
    414       1.1    nonaka 
    415      1.10      matt 	return dst & (__BIT(len) - 1);
    416       1.1    nonaka }
    417       1.1    nonaka 
    418       1.1    nonaka #endif	/* _SDMMCREG_H_ */
    419