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sdmmcreg.h revision 1.3.12.1
      1  1.3.12.1   rmind /*	$NetBSD: sdmmcreg.h,v 1.3.12.1 2010/05/30 05:17:43 rmind Exp $	*/
      2       1.1  nonaka /*	$OpenBSD: sdmmcreg.h,v 1.4 2009/01/09 10:55:22 jsg Exp $	*/
      3       1.1  nonaka 
      4       1.1  nonaka /*
      5       1.1  nonaka  * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org>
      6       1.1  nonaka  *
      7       1.1  nonaka  * Permission to use, copy, modify, and distribute this software for any
      8       1.1  nonaka  * purpose with or without fee is hereby granted, provided that the above
      9       1.1  nonaka  * copyright notice and this permission notice appear in all copies.
     10       1.1  nonaka  *
     11       1.1  nonaka  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     12       1.1  nonaka  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     13       1.1  nonaka  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     14       1.1  nonaka  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     15       1.1  nonaka  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     16       1.1  nonaka  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     17       1.1  nonaka  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     18       1.1  nonaka  */
     19       1.1  nonaka 
     20       1.1  nonaka #ifndef	_SDMMCREG_H_
     21       1.1  nonaka #define	_SDMMCREG_H_
     22       1.1  nonaka 
     23       1.1  nonaka /* MMC commands */				/* response type */
     24       1.1  nonaka #define MMC_GO_IDLE_STATE		0	/* R0 */
     25       1.1  nonaka #define MMC_SEND_OP_COND		1	/* R3 */
     26       1.1  nonaka #define MMC_ALL_SEND_CID		2	/* R2 */
     27       1.2  nonaka #define MMC_SET_RELATIVE_ADDR 	  	3	/* R1 */
     28       1.2  nonaka #define MMC_SWITCH			6	/* R1b */
     29       1.1  nonaka #define MMC_SELECT_CARD			7	/* R1 */
     30       1.2  nonaka #define MMC_SEND_EXT_CSD		8	/* R1 */
     31       1.1  nonaka #define MMC_SEND_CSD			9	/* R2 */
     32       1.2  nonaka #define MMC_SEND_CID			10	/* R2 */
     33       1.1  nonaka #define MMC_STOP_TRANSMISSION		12	/* R1b */
     34       1.1  nonaka #define MMC_SEND_STATUS			13	/* R1 */
     35       1.1  nonaka #define MMC_INACTIVE_STATE		15	/* R0 */
     36       1.1  nonaka #define MMC_SET_BLOCKLEN		16	/* R1 */
     37       1.1  nonaka #define MMC_READ_BLOCK_SINGLE		17	/* R1 */
     38       1.1  nonaka #define MMC_READ_BLOCK_MULTIPLE		18	/* R1 */
     39       1.1  nonaka #define MMC_SET_BLOCK_COUNT		23	/* R1 */
     40       1.1  nonaka #define MMC_WRITE_BLOCK_SINGLE		24	/* R1 */
     41       1.1  nonaka #define MMC_WRITE_BLOCK_MULTIPLE	25	/* R1 */
     42       1.2  nonaka #define MMC_PROGRAM_CSD			27	/* R1 */
     43       1.2  nonaka #define MMC_SET_WRITE_PROT		28	/* R1b */
     44       1.2  nonaka #define MMC_SET_CLR_WRITE_PROT		29	/* R1b */
     45       1.2  nonaka #define MMC_SET_SEND_WRITE_PROT		30	/* R1 */
     46       1.2  nonaka #define MMC_TAG_SECTOR_START		32	/* R1 */
     47       1.2  nonaka #define MMC_TAG_SECTOR_END		33	/* R1 */
     48       1.2  nonaka #define MMC_UNTAG_SECTOR		34	/* R1 */
     49       1.2  nonaka #define MMC_TAG_ERASE_GROUP_START	35	/* R1 */
     50       1.2  nonaka #define MMC_TAG_ERASE_GROUP_END		36	/* R1 */
     51       1.2  nonaka #define MMC_UNTAG_ERASE_GROUP		37	/* R1 */
     52       1.2  nonaka #define MMC_ERASE			38	/* R1b */
     53       1.2  nonaka #define MMC_LOCK_UNLOCK			42	/* R1b */
     54       1.1  nonaka #define MMC_APP_CMD			55	/* R1 */
     55       1.2  nonaka #define MMC_READ_OCR			58	/* R3 */
     56       1.1  nonaka 
     57       1.2  nonaka /* SD commands */			/* response type */
     58       1.3  nonaka #define SD_SEND_RELATIVE_ADDR 	  	3	/* R6 */
     59       1.1  nonaka #define SD_SEND_IF_COND			8	/* R7 */
     60       1.1  nonaka 
     61       1.1  nonaka /* SD application commands */			/* response type */
     62       1.1  nonaka #define SD_APP_SET_BUS_WIDTH		6	/* R1 */
     63       1.1  nonaka #define SD_APP_OP_COND			41	/* R3 */
     64       1.2  nonaka #define SD_APP_SEND_SCR			51	/* R1 */
     65       1.1  nonaka 
     66       1.1  nonaka /* OCR bits */
     67       1.1  nonaka #define MMC_OCR_MEM_READY		(1U<<31)/* memory power-up status bit */
     68       1.2  nonaka #define MMC_OCR_HCS			(1<<30)
     69       1.1  nonaka #define MMC_OCR_3_5V_3_6V		(1<<23)
     70       1.1  nonaka #define MMC_OCR_3_4V_3_5V		(1<<22)
     71       1.1  nonaka #define MMC_OCR_3_3V_3_4V		(1<<21)
     72       1.1  nonaka #define MMC_OCR_3_2V_3_3V		(1<<20)
     73       1.1  nonaka #define MMC_OCR_3_1V_3_2V		(1<<19)
     74       1.1  nonaka #define MMC_OCR_3_0V_3_1V		(1<<18)
     75       1.1  nonaka #define MMC_OCR_2_9V_3_0V		(1<<17)
     76       1.1  nonaka #define MMC_OCR_2_8V_2_9V		(1<<16)
     77       1.1  nonaka #define MMC_OCR_2_7V_2_8V		(1<<15)
     78       1.1  nonaka #define MMC_OCR_2_6V_2_7V		(1<<14)
     79       1.1  nonaka #define MMC_OCR_2_5V_2_6V		(1<<13)
     80       1.1  nonaka #define MMC_OCR_2_4V_2_5V		(1<<12)
     81       1.1  nonaka #define MMC_OCR_2_3V_2_4V		(1<<11)
     82       1.1  nonaka #define MMC_OCR_2_2V_2_3V		(1<<10)
     83       1.1  nonaka #define MMC_OCR_2_1V_2_2V		(1<<9)
     84       1.1  nonaka #define MMC_OCR_2_0V_2_1V		(1<<8)
     85       1.1  nonaka #define MMC_OCR_1_9V_2_0V		(1<<7)
     86       1.1  nonaka #define MMC_OCR_1_8V_1_9V		(1<<6)
     87       1.1  nonaka #define MMC_OCR_1_7V_1_8V		(1<<5)
     88       1.1  nonaka #define MMC_OCR_1_6V_1_7V		(1<<4)
     89       1.1  nonaka 
     90       1.1  nonaka /* R1 response type bits */
     91       1.1  nonaka #define MMC_R1_READY_FOR_DATA		(1<<8)	/* ready for next transfer */
     92       1.1  nonaka #define MMC_R1_APP_CMD			(1<<5)	/* app. commands supported */
     93       1.1  nonaka 
     94       1.1  nonaka /* 48-bit response decoding (32 bits w/o CRC) */
     95       1.1  nonaka #define MMC_R1(resp)			((resp)[0])
     96       1.1  nonaka #define MMC_R3(resp)			((resp)[0])
     97       1.1  nonaka #define SD_R6(resp)			((resp)[0])
     98       1.1  nonaka #define MMC_R7(resp)			((resp)[0])
     99  1.3.12.1   rmind #define MMC_SPI_R1(resp)		((resp)[0])
    100  1.3.12.1   rmind #define MMC_SPI_R7(resp)		((resp)[1])
    101       1.1  nonaka 
    102       1.1  nonaka /* RCA argument and response */
    103       1.1  nonaka #define MMC_ARG_RCA(rca)		((rca) << 16)
    104       1.1  nonaka #define SD_R6_RCA(resp)			(SD_R6((resp)) >> 16)
    105       1.1  nonaka 
    106       1.1  nonaka /* bus width argument */
    107       1.1  nonaka #define SD_ARG_BUS_WIDTH_1		0
    108       1.1  nonaka #define SD_ARG_BUS_WIDTH_4		2
    109       1.1  nonaka 
    110  1.3.12.1   rmind /* EXT_CSD fields */
    111  1.3.12.1   rmind #define EXT_CSD_BUS_WIDTH		183	/* R/W */
    112  1.3.12.1   rmind 
    113  1.3.12.1   rmind /* EXT_CSD field definitions */
    114  1.3.12.1   rmind #define EXT_CSD_CMD_SET_NORMAL		(1U << 0)
    115  1.3.12.1   rmind #define EXT_CSD_CMD_SET_SECURE		(1U << 1)
    116  1.3.12.1   rmind #define EXT_CSD_CMD_SET_CPSECURE	(1U << 2)
    117  1.3.12.1   rmind 
    118  1.3.12.1   rmind /* EXT_CSD_BUS_WIDTH */
    119  1.3.12.1   rmind #define EXT_CSD_BUS_WIDTH_1		0	/* 1 bit mode */
    120  1.3.12.1   rmind #define EXT_CSD_BUS_WIDTH_4		1	/* 4 bit mode */
    121  1.3.12.1   rmind #define EXT_CSD_BUS_WIDTH_8		2	/* 8 bit mode */
    122  1.3.12.1   rmind 
    123  1.3.12.1   rmind /* MMC_SWITCH access mode */
    124  1.3.12.1   rmind #define MMC_SWITCH_MODE_CMD_SET		0x00	/* Change the command set */
    125  1.3.12.1   rmind #define MMC_SWITCH_MODE_SET_BITS	0x01	/* Set bits in value */
    126  1.3.12.1   rmind #define MMC_SWITCH_MODE_CLEAR_BITS	0x02	/* Clear bits in value */
    127  1.3.12.1   rmind #define MMC_SWITCH_MODE_WRITE_BYTE	0x03	/* Set target to value */
    128  1.3.12.1   rmind 
    129  1.3.12.1   rmind /* SPI mode reports R1/R2(SEND_STATUS) status. */
    130  1.3.12.1   rmind #define R1_SPI_IDLE		(1 << 0)
    131  1.3.12.1   rmind #define R1_SPI_ERASE_RESET	(1 << 1)
    132  1.3.12.1   rmind #define R1_SPI_ILLEGAL_COMMAND	(1 << 2)
    133  1.3.12.1   rmind #define R1_SPI_COM_CRC		(1 << 3)
    134  1.3.12.1   rmind #define R1_SPI_ERASE_SEQ	(1 << 4)
    135  1.3.12.1   rmind #define R1_SPI_ADDRESS		(1 << 5)
    136  1.3.12.1   rmind #define R1_SPI_PARAMETER	(1 << 6)
    137  1.3.12.1   rmind /* R1 bit 7 is always zero */
    138  1.3.12.1   rmind #define R2_SPI_CARD_LOCKED	(1 << 8)
    139  1.3.12.1   rmind #define R2_SPI_WP_ERASE_SKIP	(1 << 9)	/* or lock/unlock fail */
    140  1.3.12.1   rmind #define R2_SPI_LOCK_UNLOCK_FAIL	R2_SPI_WP_ERASE_SKIP
    141  1.3.12.1   rmind #define R2_SPI_ERROR		(1 << 10)
    142  1.3.12.1   rmind #define R2_SPI_CC_ERROR		(1 << 11)
    143  1.3.12.1   rmind #define R2_SPI_CARD_ECC_ERROR	(1 << 12)
    144  1.3.12.1   rmind #define R2_SPI_WP_VIOLATION	(1 << 13)
    145  1.3.12.1   rmind #define R2_SPI_ERASE_PARAM	(1 << 14)
    146  1.3.12.1   rmind #define R2_SPI_OUT_OF_RANGE	(1 << 15)	/* or CSD overwrite */
    147  1.3.12.1   rmind #define R2_SPI_CSD_OVERWRITE	R2_SPI_OUT_OF_RANGE
    148  1.3.12.1   rmind 
    149       1.1  nonaka /* MMC R2 response (CSD) */
    150       1.1  nonaka #define MMC_CSD_CSDVER(resp)		MMC_RSP_BITS((resp), 126, 2)
    151       1.1  nonaka #define  MMC_CSD_CSDVER_1_0		1
    152       1.1  nonaka #define  MMC_CSD_CSDVER_2_0		2
    153       1.1  nonaka #define MMC_CSD_MMCVER(resp)		MMC_RSP_BITS((resp), 122, 4)
    154       1.1  nonaka #define  MMC_CSD_MMCVER_1_0		0 /* MMC 1.0 - 1.2 */
    155       1.1  nonaka #define  MMC_CSD_MMCVER_1_4		1 /* MMC 1.4 */
    156       1.1  nonaka #define  MMC_CSD_MMCVER_2_0		2 /* MMC 2.0 - 2.2 */
    157       1.1  nonaka #define  MMC_CSD_MMCVER_3_1		3 /* MMC 3.1 - 3.3 */
    158       1.1  nonaka #define  MMC_CSD_MMCVER_4_0		4 /* MMC 4 */
    159       1.1  nonaka #define MMC_CSD_TAAC(resp)		MMC_RSP_BITS((resp), 112, 8)
    160       1.1  nonaka #define MMC_CSD_TAAC_MANT(resp)		MMC_RSP_BITS((resp), 115, 4)
    161       1.1  nonaka #define MMC_CSD_TAAC_EXP(resp)		MMC_RSP_BITS((resp), 112, 3)
    162       1.1  nonaka #define MMC_CSD_NSAC(resp)		MMC_RSP_BITS((resp), 104, 8)
    163       1.1  nonaka #define MMC_CSD_TRAN_SPEED(resp)	MMC_RSP_BITS((resp), 96, 8)
    164       1.1  nonaka #define MMC_CSD_TRAN_SPEED_MANT(resp)	MMC_RSP_BITS((resp), 99, 4)
    165       1.1  nonaka #define MMC_CSD_TRAN_SPEED_EXP(resp)	MMC_RSP_BITS((resp), 96, 3)
    166       1.1  nonaka #define MMC_CSD_READ_BL_LEN(resp)	MMC_RSP_BITS((resp), 80, 4)
    167       1.1  nonaka #define MMC_CSD_C_SIZE(resp)		MMC_RSP_BITS((resp), 62, 12)
    168       1.1  nonaka #define MMC_CSD_CAPACITY(resp)		((MMC_CSD_C_SIZE((resp))+1) << \
    169       1.1  nonaka 					 (MMC_CSD_C_SIZE_MULT((resp))+2))
    170       1.1  nonaka #define MMC_CSD_C_SIZE_MULT(resp)	MMC_RSP_BITS((resp), 47, 3)
    171       1.1  nonaka #define MMC_CSD_R2W_FACTOR(resp)	MMC_RSP_BITS((resp), 26, 3)
    172       1.1  nonaka #define MMC_CSD_WRITE_BL_LEN(resp)	MMC_RSP_BITS((resp), 22, 4)
    173       1.1  nonaka 
    174       1.1  nonaka /* MMC v1 R2 response (CID) */
    175       1.1  nonaka #define MMC_CID_MID_V1(resp)		MMC_RSP_BITS((resp), 104, 24)
    176       1.1  nonaka #define MMC_CID_PNM_V1_CPY(resp, pnm)					\
    177       1.1  nonaka 	do {								\
    178       1.1  nonaka 		(pnm)[0] = MMC_RSP_BITS((resp), 96, 8);			\
    179       1.1  nonaka 		(pnm)[1] = MMC_RSP_BITS((resp), 88, 8);			\
    180       1.1  nonaka 		(pnm)[2] = MMC_RSP_BITS((resp), 80, 8);			\
    181       1.1  nonaka 		(pnm)[3] = MMC_RSP_BITS((resp), 72, 8);			\
    182       1.1  nonaka 		(pnm)[4] = MMC_RSP_BITS((resp), 64, 8);			\
    183       1.1  nonaka 		(pnm)[5] = MMC_RSP_BITS((resp), 56, 8);			\
    184       1.1  nonaka 		(pnm)[6] = MMC_RSP_BITS((resp), 48, 8);			\
    185       1.1  nonaka 		(pnm)[7] = '\0';					\
    186       1.1  nonaka 	} while (/*CONSTCOND*/0)
    187       1.1  nonaka #define MMC_CID_REV_V1(resp)		MMC_RSP_BITS((resp), 40, 8)
    188       1.1  nonaka #define MMC_CID_PSN_V1(resp)		MMC_RSP_BITS((resp), 16, 24)
    189       1.1  nonaka #define MMC_CID_MDT_V1(resp)		MMC_RSP_BITS((resp), 8, 8)
    190       1.1  nonaka 
    191       1.1  nonaka /* MMC v2 R2 response (CID) */
    192       1.1  nonaka #define MMC_CID_MID_V2(resp)		MMC_RSP_BITS((resp), 120, 8)
    193       1.1  nonaka #define MMC_CID_OID_V2(resp)		MMC_RSP_BITS((resp), 104, 16)
    194       1.1  nonaka #define MMC_CID_PNM_V2_CPY(resp, pnm)					\
    195       1.1  nonaka 	do {								\
    196       1.1  nonaka 		(pnm)[0] = MMC_RSP_BITS((resp), 96, 8);			\
    197       1.1  nonaka 		(pnm)[1] = MMC_RSP_BITS((resp), 88, 8);			\
    198       1.1  nonaka 		(pnm)[2] = MMC_RSP_BITS((resp), 80, 8);			\
    199       1.1  nonaka 		(pnm)[3] = MMC_RSP_BITS((resp), 72, 8);			\
    200       1.1  nonaka 		(pnm)[4] = MMC_RSP_BITS((resp), 64, 8);			\
    201       1.1  nonaka 		(pnm)[5] = MMC_RSP_BITS((resp), 56, 8);			\
    202       1.1  nonaka 		(pnm)[6] = '\0';					\
    203       1.1  nonaka 	} while (/*CONSTCOND*/0)
    204       1.1  nonaka #define MMC_CID_PSN_V2(resp)		MMC_RSP_BITS((resp), 16, 32)
    205       1.1  nonaka 
    206       1.1  nonaka /* SD R2 response (CSD) */
    207       1.1  nonaka #define SD_CSD_CSDVER(resp)		MMC_RSP_BITS((resp), 126, 2)
    208       1.1  nonaka #define  SD_CSD_CSDVER_1_0		0
    209       1.1  nonaka #define  SD_CSD_CSDVER_2_0		1
    210       1.1  nonaka #define SD_CSD_MMCVER(resp)		MMC_RSP_BITS((resp), 122, 4)
    211       1.1  nonaka #define SD_CSD_TAAC(resp)		MMC_RSP_BITS((resp), 112, 8)
    212       1.1  nonaka #define SD_CSD_TAAC_EXP(resp)		MMC_RSP_BITS((resp), 115, 4)
    213       1.1  nonaka #define SD_CSD_TAAC_MANT(resp)		MMC_RSP_BITS((resp), 112, 3)
    214       1.1  nonaka #define  SD_CSD_TAAC_1_5_MSEC		0x26
    215       1.1  nonaka #define SD_CSD_NSAC(resp)		MMC_RSP_BITS((resp), 104, 8)
    216       1.1  nonaka #define SD_CSD_SPEED(resp)		MMC_RSP_BITS((resp), 96, 8)
    217       1.1  nonaka #define SD_CSD_SPEED_MANT(resp)		MMC_RSP_BITS((resp), 99, 4)
    218       1.1  nonaka #define SD_CSD_SPEED_EXP(resp)		MMC_RSP_BITS((resp), 96, 3)
    219       1.1  nonaka #define  SD_CSD_SPEED_25_MHZ		0x32
    220       1.1  nonaka #define  SD_CSD_SPEED_50_MHZ		0x5a
    221       1.1  nonaka #define SD_CSD_CCC(resp)		MMC_RSP_BITS((resp), 84, 12)
    222       1.1  nonaka #define  SD_CSD_CCC_ALL			0x5f5
    223       1.1  nonaka #define SD_CSD_READ_BL_LEN(resp)	MMC_RSP_BITS((resp), 80, 4)
    224       1.1  nonaka #define SD_CSD_READ_BL_PARTIAL(resp)	MMC_RSP_BITS((resp), 79, 1)
    225       1.1  nonaka #define SD_CSD_WRITE_BLK_MISALIGN(resp)	MMC_RSP_BITS((resp), 78, 1)
    226       1.1  nonaka #define SD_CSD_READ_BLK_MISALIGN(resp)	MMC_RSP_BITS((resp), 77, 1)
    227       1.1  nonaka #define SD_CSD_DSR_IMP(resp)		MMC_RSP_BITS((resp), 76, 1)
    228       1.1  nonaka #define SD_CSD_C_SIZE(resp)		MMC_RSP_BITS((resp), 62, 12)
    229       1.1  nonaka #define SD_CSD_CAPACITY(resp)		((SD_CSD_C_SIZE((resp))+1) << \
    230       1.1  nonaka 					 (SD_CSD_C_SIZE_MULT((resp))+2))
    231       1.1  nonaka #define SD_CSD_VDD_R_CURR_MIN(resp)	MMC_RSP_BITS((resp), 59, 3)
    232       1.1  nonaka #define SD_CSD_VDD_R_CURR_MAX(resp)	MMC_RSP_BITS((resp), 56, 3)
    233       1.1  nonaka #define SD_CSD_VDD_W_CURR_MIN(resp)	MMC_RSP_BITS((resp), 53, 3)
    234       1.1  nonaka #define SD_CSD_VDD_W_CURR_MAX(resp)	MMC_RSP_BITS((resp), 50, 3)
    235       1.1  nonaka #define  SD_CSD_VDD_RW_CURR_100mA	0x7
    236       1.1  nonaka #define  SD_CSD_VDD_RW_CURR_80mA	0x6
    237       1.1  nonaka #define SD_CSD_V2_C_SIZE(resp)		MMC_RSP_BITS((resp), 48, 22)
    238       1.1  nonaka #define SD_CSD_V2_CAPACITY(resp)	((SD_CSD_V2_C_SIZE((resp))+1) << 10)
    239       1.1  nonaka #define SD_CSD_V2_BL_LEN		0x9 /* 512 */
    240       1.1  nonaka #define SD_CSD_C_SIZE_MULT(resp)	MMC_RSP_BITS((resp), 47, 3)
    241       1.1  nonaka #define SD_CSD_ERASE_BLK_EN(resp)	MMC_RSP_BITS((resp), 46, 1)
    242       1.1  nonaka #define SD_CSD_SECTOR_SIZE(resp)	MMC_RSP_BITS((resp), 39, 7) /* +1 */
    243       1.1  nonaka #define SD_CSD_WP_GRP_SIZE(resp)	MMC_RSP_BITS((resp), 32, 7) /* +1 */
    244       1.1  nonaka #define SD_CSD_WP_GRP_ENABLE(resp)	MMC_RSP_BITS((resp), 31, 1)
    245       1.1  nonaka #define SD_CSD_R2W_FACTOR(resp)		MMC_RSP_BITS((resp), 26, 3)
    246       1.1  nonaka #define SD_CSD_WRITE_BL_LEN(resp)	MMC_RSP_BITS((resp), 22, 4)
    247       1.1  nonaka #define  SD_CSD_RW_BL_LEN_2G		0xa
    248       1.1  nonaka #define  SD_CSD_RW_BL_LEN_1G		0x9
    249       1.1  nonaka #define SD_CSD_WRITE_BL_PARTIAL(resp)	MMC_RSP_BITS((resp), 21, 1)
    250       1.1  nonaka #define SD_CSD_FILE_FORMAT_GRP(resp)	MMC_RSP_BITS((resp), 15, 1)
    251       1.1  nonaka #define SD_CSD_COPY(resp)		MMC_RSP_BITS((resp), 14, 1)
    252       1.1  nonaka #define SD_CSD_PERM_WRITE_PROTECT(resp)	MMC_RSP_BITS((resp), 13, 1)
    253       1.1  nonaka #define SD_CSD_TMP_WRITE_PROTECT(resp)	MMC_RSP_BITS((resp), 12, 1)
    254       1.1  nonaka #define SD_CSD_FILE_FORMAT(resp)	MMC_RSP_BITS((resp), 10, 2)
    255       1.1  nonaka 
    256       1.1  nonaka /* SD R2 response (CID) */
    257       1.1  nonaka #define SD_CID_MID(resp)		MMC_RSP_BITS((resp), 120, 8)
    258       1.1  nonaka #define SD_CID_OID(resp)		MMC_RSP_BITS((resp), 104, 16)
    259       1.1  nonaka #define SD_CID_PNM_CPY(resp, pnm)					\
    260       1.1  nonaka 	do {								\
    261       1.1  nonaka 		(pnm)[0] = MMC_RSP_BITS((resp), 96, 8);			\
    262       1.1  nonaka 		(pnm)[1] = MMC_RSP_BITS((resp), 88, 8);			\
    263       1.1  nonaka 		(pnm)[2] = MMC_RSP_BITS((resp), 80, 8);			\
    264       1.1  nonaka 		(pnm)[3] = MMC_RSP_BITS((resp), 72, 8);			\
    265       1.1  nonaka 		(pnm)[4] = MMC_RSP_BITS((resp), 64, 8);			\
    266       1.1  nonaka 		(pnm)[5] = '\0';					\
    267       1.1  nonaka 	} while (/*CONSTCOND*/0)
    268       1.1  nonaka #define SD_CID_REV(resp)		MMC_RSP_BITS((resp), 56, 8)
    269       1.1  nonaka #define SD_CID_PSN(resp)		MMC_RSP_BITS((resp), 24, 32)
    270       1.1  nonaka #define SD_CID_MDT(resp)		MMC_RSP_BITS((resp), 8, 12)
    271       1.1  nonaka 
    272       1.1  nonaka /* SCR (SD Configuration Register) */
    273       1.2  nonaka #define SCR_STRUCTURE(scr)		MMC_RSP_BITS((scr), 60, 4)
    274       1.2  nonaka #define  SCR_STRUCTURE_VER_1_0		0 /* Version 1.0 */
    275       1.2  nonaka #define SCR_SD_SPEC(scr)		MMC_RSP_BITS((scr), 56, 4)
    276       1.2  nonaka #define  SCR_SD_SPEC_VER_1_0		0 /* Version 1.0 */
    277       1.2  nonaka #define SCR_DATA_STAT_AFTER_ERASE(scr)	MMC_RSP_BITS((scr), 55, 1)
    278       1.2  nonaka #define SCR_SD_SECURITY(scr)		MMC_RSP_BITS((scr), 52, 3)
    279       1.2  nonaka #define  SCR_SD_SECURITY_NONE		0 /* no security */
    280       1.2  nonaka #define  SCR_SD_SECURITY_1_0		1 /* security protocol 1.0 */
    281       1.2  nonaka #define  SCR_SD_SECURITY_1_0_2		2 /* security protocol 1.0 */
    282       1.2  nonaka #define SCR_SD_BUS_WIDTHS(scr)		MMC_RSP_BITS((scr), 48, 4)
    283       1.2  nonaka #define  SCR_SD_BUS_WIDTHS_1BIT		(1 << 0) /* 1bit (DAT0) */
    284       1.2  nonaka #define  SCR_SD_BUS_WIDTHS_4BIT		(1 << 2) /* 4bit (DAT0-3) */
    285       1.2  nonaka #define SCR_RESERVED(scr)		MMC_RSP_BITS((scr), 32, 16)
    286       1.2  nonaka #define SCR_RESERVED2(scr)		MMC_RSP_BITS((scr), 0, 32)
    287       1.1  nonaka 
    288       1.1  nonaka /* Might be slow, but it should work on big and little endian systems. */
    289       1.1  nonaka #define MMC_RSP_BITS(resp, start, len)	__bitfield((resp), (start)-8, (len))
    290       1.1  nonaka static inline int
    291       1.1  nonaka __bitfield(uint32_t *src, int start, int len)
    292       1.1  nonaka {
    293       1.1  nonaka 	uint8_t *sp;
    294       1.1  nonaka 	uint32_t dst, mask;
    295       1.1  nonaka 	int shift, bs, bc;
    296       1.1  nonaka 
    297       1.1  nonaka 	if (start < 0 || len < 0 || len > 32)
    298       1.1  nonaka 		return 0;
    299       1.1  nonaka 
    300       1.1  nonaka 	dst = 0;
    301       1.1  nonaka 	mask = len % 32 ? UINT_MAX >> (32 - (len % 32)) : UINT_MAX;
    302       1.1  nonaka 	shift = 0;
    303       1.1  nonaka 
    304       1.1  nonaka 	while (len > 0) {
    305       1.1  nonaka 		sp = (uint8_t *)src + start / 8;
    306       1.1  nonaka 		bs = start % 8;
    307       1.1  nonaka 		bc = 8 - bs;
    308       1.1  nonaka 		if (bc > len)
    309       1.1  nonaka 			bc = len;
    310       1.1  nonaka 		dst |= (*sp++ >> bs) << shift;
    311       1.1  nonaka 		shift += bc;
    312       1.1  nonaka 		start += bc;
    313       1.1  nonaka 		len -= bc;
    314       1.1  nonaka 	}
    315       1.1  nonaka 
    316       1.1  nonaka 	dst &= mask;
    317       1.1  nonaka 	return (int)dst;
    318       1.1  nonaka }
    319       1.1  nonaka 
    320       1.1  nonaka #endif	/* _SDMMCREG_H_ */
    321