sdmmcreg.h revision 1.14
1 /* $NetBSD: sdmmcreg.h,v 1.14 2013/05/03 16:38:35 matt Exp $ */ 2 /* $OpenBSD: sdmmcreg.h,v 1.4 2009/01/09 10:55:22 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _SDMMCREG_H_ 21 #define _SDMMCREG_H_ 22 23 /* MMC commands */ /* response type */ 24 #define MMC_GO_IDLE_STATE 0 /* R0 */ 25 #define MMC_SEND_OP_COND 1 /* R3 */ 26 #define MMC_ALL_SEND_CID 2 /* R2 */ 27 #define MMC_SET_RELATIVE_ADDR 3 /* R1 */ 28 #define MMC_SWITCH 6 /* R1b */ 29 #define MMC_SELECT_CARD 7 /* R1 */ 30 #define MMC_SEND_EXT_CSD 8 /* R1 */ 31 #define MMC_SEND_CSD 9 /* R2 */ 32 #define MMC_SEND_CID 10 /* R2 */ 33 #define MMC_STOP_TRANSMISSION 12 /* R1b */ 34 #define MMC_SEND_STATUS 13 /* R1 */ 35 #define MMC_INACTIVE_STATE 15 /* R0 */ 36 #define MMC_SET_BLOCKLEN 16 /* R1 */ 37 #define MMC_READ_BLOCK_SINGLE 17 /* R1 */ 38 #define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */ 39 #define MMC_SET_BLOCK_COUNT 23 /* R1 */ 40 #define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */ 41 #define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */ 42 #define MMC_PROGRAM_CSD 27 /* R1 */ 43 #define MMC_SET_WRITE_PROT 28 /* R1b */ 44 #define MMC_SET_CLR_WRITE_PROT 29 /* R1b */ 45 #define MMC_SET_SEND_WRITE_PROT 30 /* R1 */ 46 #define MMC_TAG_SECTOR_START 32 /* R1 */ 47 #define MMC_TAG_SECTOR_END 33 /* R1 */ 48 #define MMC_UNTAG_SECTOR 34 /* R1 */ 49 #define MMC_TAG_ERASE_GROUP_START 35 /* R1 */ 50 #define MMC_TAG_ERASE_GROUP_END 36 /* R1 */ 51 #define MMC_UNTAG_ERASE_GROUP 37 /* R1 */ 52 #define MMC_ERASE 38 /* R1b */ 53 #define MMC_LOCK_UNLOCK 42 /* R1b */ 54 #define MMC_APP_CMD 55 /* R1 */ 55 #define MMC_READ_OCR 58 /* R3 */ 56 57 /* SD commands */ /* response type */ 58 #define SD_SEND_RELATIVE_ADDR 3 /* R6 */ 59 #define SD_SEND_SWITCH_FUNC 6 /* R1 */ 60 #define SD_SEND_IF_COND 8 /* R7 */ 61 62 /* SD application commands */ /* response type */ 63 #define SD_APP_SET_BUS_WIDTH 6 /* R1 */ 64 #define SD_APP_SD_STATUS 13 /* R1 */ 65 #define SD_APP_OP_COND 41 /* R3 */ 66 #define SD_APP_SEND_SCR 51 /* R1 */ 67 68 /* OCR bits */ 69 #define MMC_OCR_MEM_READY (1U<<31)/* memory power-up status bit */ 70 #define MMC_OCR_HCS (1<<30) 71 #define MMC_OCR_3_5V_3_6V (1<<23) 72 #define MMC_OCR_3_4V_3_5V (1<<22) 73 #define MMC_OCR_3_3V_3_4V (1<<21) 74 #define MMC_OCR_3_2V_3_3V (1<<20) 75 #define MMC_OCR_3_1V_3_2V (1<<19) 76 #define MMC_OCR_3_0V_3_1V (1<<18) 77 #define MMC_OCR_2_9V_3_0V (1<<17) 78 #define MMC_OCR_2_8V_2_9V (1<<16) 79 #define MMC_OCR_2_7V_2_8V (1<<15) 80 #define MMC_OCR_2_6V_2_7V (1<<14) 81 #define MMC_OCR_2_5V_2_6V (1<<13) 82 #define MMC_OCR_2_4V_2_5V (1<<12) 83 #define MMC_OCR_2_3V_2_4V (1<<11) 84 #define MMC_OCR_2_2V_2_3V (1<<10) 85 #define MMC_OCR_2_1V_2_2V (1<<9) 86 #define MMC_OCR_2_0V_2_1V (1<<8) 87 #define MMC_OCR_1_9V_2_0V (1<<7) 88 #define MMC_OCR_1_8V_1_9V (1<<6) 89 #define MMC_OCR_1_7V_1_8V (1<<5) 90 #define MMC_OCR_1_6V_1_7V (1<<4) 91 92 /* R1 response type bits */ 93 #define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */ 94 #define MMC_R1_APP_CMD (1<<5) /* app. commands supported */ 95 96 /* 48-bit response decoding (32 bits w/o CRC) */ 97 #define MMC_R1(resp) ((resp)[0]) 98 #define MMC_R3(resp) ((resp)[0]) 99 #define SD_R6(resp) ((resp)[0]) 100 #define MMC_R7(resp) ((resp)[0]) 101 #define MMC_SPI_R1(resp) ((resp)[0]) 102 #define MMC_SPI_R7(resp) ((resp)[1]) 103 104 /* RCA argument and response */ 105 #define MMC_ARG_RCA(rca) ((rca) << 16) 106 #define SD_R6_RCA(resp) (SD_R6((resp)) >> 16) 107 108 /* bus width argument */ 109 #define SD_ARG_BUS_WIDTH_1 0 110 #define SD_ARG_BUS_WIDTH_4 2 111 112 /* EXT_CSD fields */ 113 #define EXT_CSD_BUS_WIDTH 183 /* WO */ 114 #define EXT_CSD_HS_TIMING 185 /* R/W */ 115 #define EXT_CSD_REV 192 /* RO */ 116 #define EXT_CSD_STRUCTURE 194 /* RO */ 117 #define EXT_CSD_CARD_TYPE 196 /* RO */ 118 119 /* EXT_CSD field definitions */ 120 #define EXT_CSD_CMD_SET_NORMAL (1U << 0) 121 #define EXT_CSD_CMD_SET_SECURE (1U << 1) 122 #define EXT_CSD_CMD_SET_CPSECURE (1U << 2) 123 124 /* EXT_CSD_BUS_WIDTH */ 125 #define EXT_CSD_BUS_WIDTH_1 0 /* 1 bit mode */ 126 #define EXT_CSD_BUS_WIDTH_4 1 /* 4 bit mode */ 127 #define EXT_CSD_BUS_WIDTH_8 2 /* 8 bit mode */ 128 129 /* EXT_CSD_STRUCTURE */ 130 #define EXT_CSD_STRUCTURE_VER_1_0 0 /* CSD Version No.1.0 */ 131 #define EXT_CSD_STRUCTURE_VER_1_1 1 /* CSD Version No.1.1 */ 132 #define EXT_CSD_STRUCTURE_VER_1_2 2 /* Version 4.1-4.2-4.3 */ 133 134 /* EXT_CSD_CARD_TYPE */ 135 /* The only currently valid values for this field are 0x01, 0x03, 0x07, 136 * 0x0B and 0x0F. */ 137 #define EXT_CSD_CARD_TYPE_F_26M (1 << 0) 138 #define EXT_CSD_CARD_TYPE_F_52M (1 << 1) 139 #define EXT_CSD_CARD_TYPE_F_52M_1_8V (1 << 2) 140 #define EXT_CSD_CARD_TYPE_F_52M_1_2V (1 << 3) 141 #define EXT_CSD_CARD_TYPE_26M 0x01 142 #define EXT_CSD_CARD_TYPE_52M 0x03 143 #define EXT_CSD_CARD_TYPE_52M_V18 0x07 144 #define EXT_CSD_CARD_TYPE_52M_V12 0x0b 145 #define EXT_CSD_CARD_TYPE_52M_V12_18 0x0f 146 147 /* MMC_SWITCH access mode */ 148 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 149 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in value */ 150 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in value */ 151 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ 152 153 /* SPI mode reports R1/R2(SEND_STATUS) status. */ 154 #define R1_SPI_IDLE (1 << 0) 155 #define R1_SPI_ERASE_RESET (1 << 1) 156 #define R1_SPI_ILLEGAL_COMMAND (1 << 2) 157 #define R1_SPI_COM_CRC (1 << 3) 158 #define R1_SPI_ERASE_SEQ (1 << 4) 159 #define R1_SPI_ADDRESS (1 << 5) 160 #define R1_SPI_PARAMETER (1 << 6) 161 /* R1 bit 7 is always zero */ 162 #define R2_SPI_CARD_LOCKED (1 << 8) 163 #define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ 164 #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP 165 #define R2_SPI_ERROR (1 << 10) 166 #define R2_SPI_CC_ERROR (1 << 11) 167 #define R2_SPI_CARD_ECC_ERROR (1 << 12) 168 #define R2_SPI_WP_VIOLATION (1 << 13) 169 #define R2_SPI_ERASE_PARAM (1 << 14) 170 #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ 171 #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE 172 173 /* MMC R2 response (CSD) */ 174 #define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2) 175 #define MMC_CSD_CSDVER_1_0 0 176 #define MMC_CSD_CSDVER_1_1 1 177 #define MMC_CSD_CSDVER_1_2 2 /* MMC 4.1 - 4.2 - 4.3 */ 178 #define MMC_CSD_CSDVER_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */ 179 #define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4) 180 #define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */ 181 #define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */ 182 #define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */ 183 #define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */ 184 #define MMC_CSD_MMCVER_4_0 4 /* MMC 4.1 - 4.2 - 4.3 */ 185 #define MMC_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8) 186 #define MMC_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 115, 4) 187 #define MMC_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 112, 3) 188 #define MMC_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8) 189 #define MMC_CSD_TRAN_SPEED(resp) MMC_RSP_BITS((resp), 96, 8) 190 #define MMC_CSD_TRAN_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4) 191 #define MMC_CSD_TRAN_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3) 192 #define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4) 193 #define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12) 194 #define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \ 195 (MMC_CSD_C_SIZE_MULT((resp))+2)) 196 #define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3) 197 #define MMC_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3) 198 #define MMC_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4) 199 200 /* MMC v1 R2 response (CID) */ 201 #define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24) 202 #define MMC_CID_PNM_V1_CPY(resp, pnm) \ 203 do { \ 204 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 205 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 206 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 207 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 208 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 209 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \ 210 (pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \ 211 (pnm)[7] = '\0'; \ 212 } while (/*CONSTCOND*/0) 213 #define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8) 214 #define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24) 215 #define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8) 216 217 /* MMC v2 R2 response (CID) */ 218 #define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8) 219 #define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16) 220 #define MMC_CID_PNM_V2_CPY(resp, pnm) \ 221 do { \ 222 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 223 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 224 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 225 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 226 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 227 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \ 228 (pnm)[6] = '\0'; \ 229 } while (/*CONSTCOND*/0) 230 #define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32) 231 232 /* SD R2 response (CSD) */ 233 #define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2) 234 #define SD_CSD_CSDVER_1_0 0 235 #define SD_CSD_CSDVER_2_0 1 236 #define SD_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4) 237 #define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8) 238 #define SD_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 115, 4) 239 #define SD_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 112, 3) 240 #define SD_CSD_TAAC_1_5_MSEC 0x26 241 #define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8) 242 #define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8) 243 #define SD_CSD_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4) 244 #define SD_CSD_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3) 245 #define SD_CSD_SPEED_25_MHZ 0x32 246 #define SD_CSD_SPEED_50_MHZ 0x5a 247 #define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12) 248 #define SD_CSD_CCC_BASIC (1 << 0) /* basic */ 249 #define SD_CSD_CCC_BR (1 << 2) /* block read */ 250 #define SD_CSD_CCC_BW (1 << 4) /* block write */ 251 #define SD_CSD_CCC_ERACE (1 << 5) /* erase */ 252 #define SD_CSD_CCC_WP (1 << 6) /* write protection */ 253 #define SD_CSD_CCC_LC (1 << 7) /* lock card */ 254 #define SD_CSD_CCC_AS (1 << 8) /*application specific*/ 255 #define SD_CSD_CCC_IOM (1 << 9) /* I/O mode */ 256 #define SD_CSD_CCC_SWITCH (1 << 10) /* switch */ 257 #define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4) 258 #define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1) 259 #define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1) 260 #define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1) 261 #define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1) 262 #define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12) 263 #define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \ 264 (SD_CSD_C_SIZE_MULT((resp))+2)) 265 #define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3) 266 #define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3) 267 #define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3) 268 #define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3) 269 #define SD_CSD_VDD_RW_CURR_100mA 0x7 270 #define SD_CSD_VDD_RW_CURR_80mA 0x6 271 #define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22) 272 #define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10) 273 #define SD_CSD_V2_BL_LEN 0x9 /* 512 */ 274 #define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3) 275 #define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1) 276 #define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */ 277 #define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */ 278 #define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1) 279 #define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3) 280 #define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4) 281 #define SD_CSD_RW_BL_LEN_2G 0xa 282 #define SD_CSD_RW_BL_LEN_1G 0x9 283 #define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1) 284 #define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1) 285 #define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1) 286 #define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1) 287 #define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1) 288 #define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2) 289 290 /* SD R2 response (CID) */ 291 #define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8) 292 #define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16) 293 #define SD_CID_PNM_CPY(resp, pnm) \ 294 do { \ 295 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 296 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 297 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 298 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 299 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 300 (pnm)[5] = '\0'; \ 301 } while (/*CONSTCOND*/0) 302 #define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8) 303 #define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32) 304 #define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12) 305 306 /* SCR (SD Configuration Register) */ 307 #define SCR_STRUCTURE(scr) MMC_RSP_BITS((scr), 60, 4) 308 #define SCR_STRUCTURE_VER_1_0 0 /* Version 1.0 */ 309 #define SCR_SD_SPEC(scr) MMC_RSP_BITS((scr), 56, 4) 310 #define SCR_SD_SPEC_VER_1_0 0 /* Version 1.0 and 1.01 */ 311 #define SCR_SD_SPEC_VER_1_10 1 /* Version 1.10 */ 312 #define SCR_SD_SPEC_VER_2 2 /* Version 2.00 or Version 3.0X */ 313 #define SCR_DATA_STAT_AFTER_ERASE(scr) MMC_RSP_BITS((scr), 55, 1) 314 #define SCR_SD_SECURITY(scr) MMC_RSP_BITS((scr), 52, 3) 315 #define SCR_SD_SECURITY_NONE 0 /* no security */ 316 #define SCR_SD_SECURITY_1_0 1 /* security protocol 1.0 */ 317 #define SCR_SD_SECURITY_1_0_2 2 /* security protocol 1.0 */ 318 #define SCR_SD_BUS_WIDTHS(scr) MMC_RSP_BITS((scr), 48, 4) 319 #define SCR_SD_BUS_WIDTHS_1BIT (1 << 0) /* 1bit (DAT0) */ 320 #define SCR_SD_BUS_WIDTHS_4BIT (1 << 2) /* 4bit (DAT0-3) */ 321 #define SCR_SD_SPEC3(scr) MMC_RSP_BITS((scr), 47, 1) 322 #define SCR_EX_SECURITY(scr) MMC_RSP_BITS((scr), 43, 4) 323 #define SCR_RESERVED(scr) MMC_RSP_BITS((scr), 34, 9) 324 #define SCR_CMD_SUPPORT_CMD23(scr) MMC_RSP_BITS((scr), 33, 1) 325 #define SCR_CMD_SUPPORT_CMD20(scr) MMC_RSP_BITS((scr), 32, 1) 326 #define SCR_RESERVED2(scr) MMC_RSP_BITS((scr), 0, 32) 327 328 /* Status of Switch Function */ 329 #define SFUNC_STATUS_GROUP(status, group) \ 330 (__bitfield((uint32_t *)(status), 400 + (group - 1) * 16, 16)) 331 332 /* This assumes the response fields are in host byte order in 32-bit units. */ 333 #define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start)-8, (len)) 334 static inline uint32_t 335 __bitfield(const uint32_t *src, size_t start, size_t len) 336 { 337 if (start + len > 512 || len == 0 || len > 32) 338 return 0; 339 340 src += start / 32; 341 start %= 32; 342 343 uint32_t dst = src[0] >> start; 344 345 if (__predict_false((start + len - 1) / 32 != start / 32)) { 346 dst |= src[1] << (32 - start); 347 } 348 349 return dst & (__BIT(len) - 1); 350 } 351 352 #endif /* _SDMMCREG_H_ */ 353
Indexes created Mon Sep 29 18:09:42 GMT 2025