1 /* $NetBSD: mcp23xxxgpio_spi.c,v 1.8 2025/09/13 14:10:44 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014, 2022 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank Kardel, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: mcp23xxxgpio_spi.c,v 1.8 2025/09/13 14:10:44 thorpej Exp $"); 34 35 /* 36 * Driver for Microchip serial I/O expanders: 37 * 38 * MCP23S08 8-bit, SPI interface 39 * MCP23S17 16-bit, SPI interface 40 * MCP23S18 16-bit (open-drain outputs), SPI interface 41 * 42 * Data sheet: 43 * 44 * https://ww1.microchip.com/downloads/en/DeviceDoc/20001952C.pdf 45 */ 46 47 #include "opt_fdt.h" 48 49 #include <sys/types.h> 50 #include <sys/bitops.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/mutex.h> 54 55 #include <dev/ic/mcp23xxxgpioreg.h> 56 #include <dev/ic/mcp23xxxgpiovar.h> 57 58 #include <dev/spi/spivar.h> 59 60 #ifdef FDT 61 #include <dev/fdt/fdtvar.h> 62 #endif 63 64 /* 65 * Multi-chip-on-select configurations appear to the upper layers like 66 * additional GPIO banks; mixing different chip types on the same chip 67 * select is not allowed. 68 * 69 * Some chips have 2 banks per chip, and we have up to 8 chips per chip 70 * select, it's a total of 16 banks per chip select / driver instance. 71 */ 72 #define MCPGPIO_SPI_MAXBANKS 16 73 74 struct mcpgpio_spi_softc { 75 struct mcpgpio_softc sc_mcpgpio; 76 77 kmutex_t sc_mutex; 78 spi_handle_t sc_sh; 79 uint8_t sc_ha[MCPGPIO_SPI_MAXBANKS]; 80 }; 81 82 /* 83 * SPI-specific commands (the serial interface on the I2C flavor of 84 * the chip uses the I2C protocol to infer this information). Careful 85 * readers will note that this ends up being exactly the same bits 86 * on the serial interface that the I2C flavor of the chip uses. 87 * 88 * The SPI version can have up to 4 (or 8) chips per chip-select, demuxed 89 * using the hardware address (selected by tying the 2 or 3 HA pins high/low 90 * as desired). 91 */ 92 #define OP_READ(ha) (0x41 | ((ha) << 1)) 93 #define OP_WRITE(ha) (0x40 | ((ha) << 1)) 94 95 #define MCPGPIO_TO_SPI(sc) \ 96 container_of((sc), struct mcpgpio_spi_softc, sc_mcpgpio) 97 98 static const struct mcpgpio_variant mcp23s08 = { 99 .name = "MCP23S08", 100 .type = MCPGPIO_TYPE_23x08, 101 }; 102 103 static const struct mcpgpio_variant mcp23s17 = { 104 .name = "MCP23S17", 105 .type = MCPGPIO_TYPE_23x17, 106 }; 107 108 static const struct mcpgpio_variant mcp23s18 = { 109 .name = "MCP23S18", 110 .type = MCPGPIO_TYPE_23x18, 111 }; 112 113 static const struct device_compatible_entry compat_data[] = { 114 { .compat = "microchip,mcp23s08", .data = &mcp23s08 }, 115 { .compat = "microchip,mcp23s17", .data = &mcp23s17 }, 116 { .compat = "microchip,mcp23s18", .data = &mcp23s18 }, 117 DEVICE_COMPAT_EOL 118 }; 119 120 static int 121 mcpgpio_spi_lock(struct mcpgpio_softc *sc) 122 { 123 struct mcpgpio_spi_softc *ssc = MCPGPIO_TO_SPI(sc); 124 125 mutex_enter(&ssc->sc_mutex); 126 return 0; 127 } 128 129 static void 130 mcpgpio_spi_unlock(struct mcpgpio_softc *sc) 131 { 132 struct mcpgpio_spi_softc *ssc = MCPGPIO_TO_SPI(sc); 133 134 mutex_exit(&ssc->sc_mutex); 135 } 136 137 static int 138 mcpgpio_spi_read(struct mcpgpio_softc *sc, unsigned int bank, 139 uint8_t reg, uint8_t *valp) 140 { 141 struct mcpgpio_spi_softc *ssc = MCPGPIO_TO_SPI(sc); 142 uint8_t buf[2]; 143 144 KASSERT(bank < (sc->sc_npins >> 3)); 145 146 buf[0] = OP_READ(ssc->sc_ha[bank]); 147 buf[1] = reg; 148 149 return spi_send_recv(ssc->sc_sh, 2, buf, 1, valp); 150 } 151 152 static int 153 mcpgpio_spi_write(struct mcpgpio_softc *sc, unsigned int bank, 154 uint8_t reg, uint8_t val) 155 { 156 struct mcpgpio_spi_softc *ssc = MCPGPIO_TO_SPI(sc); 157 uint8_t buf[3]; 158 159 KASSERT(bank < (sc->sc_npins >> 3)); 160 161 buf[0] = OP_WRITE(ssc->sc_ha[bank]); 162 buf[1] = reg; 163 buf[2] = val; 164 165 return spi_send(ssc->sc_sh, 3, buf); 166 } 167 168 static const struct mcpgpio_accessops mcpgpio_spi_accessops = { 169 .lock = mcpgpio_spi_lock, 170 .unlock = mcpgpio_spi_unlock, 171 .read = mcpgpio_spi_read, 172 .write = mcpgpio_spi_write, 173 }; 174 175 static const struct mcpgpio_variant * 176 mcpgpio_spi_lookup(const struct spi_attach_args *sa) 177 { 178 const struct device_compatible_entry *dce; 179 180 dce = spi_compatible_lookup(sa, compat_data); 181 if (dce == NULL) { 182 /* 183 * Legacy indirect-config-only version of the driver 184 * only supported MCP23S17, so that's what we go with. 185 * If you want to use something else, then use a proper 186 * device tree. 187 */ 188 return &mcp23s17; 189 } 190 return dce->data; 191 } 192 193 static int 194 mcpgpio_spi_match(device_t parent, cfdata_t cf, void *aux) 195 { 196 struct spi_attach_args *sa = aux; 197 int match_result; 198 199 if (spi_use_direct_match(sa, compat_data, &match_result)) { 200 return match_result; 201 } 202 203 return SPI_MATCH_DEFAULT; 204 } 205 206 #ifdef FDT 207 static uint32_t 208 mcpgpio_spi_present_mask_fdt(struct mcpgpio_softc *sc) 209 { 210 devhandle_t devhandle = device_handle(sc->sc_dev); 211 int phandle = devhandle_to_of(devhandle); 212 uint32_t val; 213 214 /* 215 * The number of devices sharing this chip select, along 216 * with their assigned addresses, is encoded in the 217 * "microchip,spi-present-mask" property. Note that this 218 * device tree binding means that we will just have a 219 * single driver instance for however many chips are on 220 * this chip select. We treat them logically as banks. 221 */ 222 if (of_getprop_uint32(phandle, "microchip,spi-present-mask", 223 &val) != 0 || 224 of_getprop_uint32(phandle, "mcp,spi-present-mask", &val) != 0) { 225 aprint_error_dev(sc->sc_dev, 226 "missing \"microchip,spi-present-mask\" property\n"); 227 return 0; 228 } 229 return val; 230 } 231 #endif /* FDT */ 232 233 static void 234 mcpgpio_spi_attach(device_t parent, device_t self, void *aux) 235 { 236 struct mcpgpio_spi_softc *ssc = device_private(self); 237 struct mcpgpio_softc *sc = &ssc->sc_mcpgpio; 238 devhandle_t devhandle = device_handle(self); 239 struct spi_attach_args *sa = aux; 240 uint32_t spi_present_mask; 241 int bank, nchips, error, ha; 242 243 mutex_init(&ssc->sc_mutex, MUTEX_DEFAULT, IPL_NONE); 244 ssc->sc_sh = sa->sa_handle; 245 246 sc->sc_dev = self; 247 sc->sc_variant = mcpgpio_spi_lookup(sa); 248 sc->sc_iocon = IOCON_HAEN | IOCON_SEQOP; 249 sc->sc_accessops = &mcpgpio_spi_accessops; 250 251 aprint_naive("\n"); 252 aprint_normal(": %s I/O Expander\n", sc->sc_variant->name); 253 254 /* run at 10MHz */ 255 error = spi_configure(self, sa->sa_handle, SPI_MODE_0, 256 SPI_FREQ_MHz(10)); 257 if (error) { 258 return; 259 } 260 261 /* 262 * Before we decode the topology information, ensure each 263 * chip has IOCON.HAEN set so that it will actually decode 264 * the address bits. 265 * 266 * XXX Going on blind faith that IOCON.BANK is already 0. 267 */ 268 if (sc->sc_variant->type == MCPGPIO_TYPE_23x08) { 269 error = mcpgpio_spi_write(sc, 0, REG_IOCON, sc->sc_iocon); 270 } else { 271 error = mcpgpio_spi_write(sc, 0, REGADDR_BANK0(0, REG_IOCON), 272 sc->sc_iocon); 273 if (error == 0) { 274 error = mcpgpio_spi_write(sc, 1, 275 REGADDR_BANK0(1, REG_IOCON), sc->sc_iocon); 276 } 277 } 278 if (error) { 279 aprint_error_dev(self, 280 "unable to initialize IOCON, error=%d\n", error); 281 return; 282 } 283 284 switch (devhandle_type(devhandle)) { 285 #ifdef FDT 286 case DEVHANDLE_TYPE_OF: 287 spi_present_mask = mcpgpio_spi_present_mask_fdt(sc); 288 if (spi_present_mask == 0) { 289 /* Error already displayed. */ 290 return; 291 } 292 break; 293 #endif /* FDT */ 294 default: 295 /* 296 * Legacy indirect-config-only only supported a single 297 * chip on the chip-select. 298 */ 299 spi_present_mask = __BIT(device_cfdata(self)->cf_flags & 0x7); 300 } 301 302 /* 303 * The 23S08 has 2 address pins (4 devices per chip select), 304 * and the others have 3 (8 devices per chip select). 305 */ 306 if (spi_present_mask == 0 || 307 (sc->sc_variant->type == MCPGPIO_TYPE_23x08 && 308 spi_present_mask >= __BIT(4)) || 309 (sc->sc_variant->type != MCPGPIO_TYPE_23x08 && 310 spi_present_mask >= __BIT(8))) { 311 aprint_error_dev(self, 312 "invalid \"microchip,spi-present-mask\" value: 0x%08x\n", 313 spi_present_mask); 314 return; 315 } 316 nchips = popcount32(spi_present_mask); 317 sc->sc_npins = nchips * 318 (sc->sc_variant->type == MCPGPIO_TYPE_23x08 ? MCP23x08_GPIO_NPINS 319 : MCP23x17_GPIO_NPINS); 320 321 /* Record the hardware addresses for each logical bank of 8 pins. */ 322 for (bank = 0; spi_present_mask != 0; spi_present_mask &= ~__BIT(ha)) { 323 int ha_first, ha_last; 324 325 ha = ffs32(spi_present_mask) - 1; 326 ha_first = bank * MCPGPIO_PINS_PER_BANK; 327 ssc->sc_ha[bank++] = ha; 328 if (sc->sc_variant->type != MCPGPIO_TYPE_23x08) { 329 ssc->sc_ha[bank++] = ha; 330 } 331 ha_last = (bank * MCPGPIO_PINS_PER_BANK) - 1; 332 aprint_verbose_dev(self, "pins %d..%d at HA %d\n", 333 ha_first, ha_last, ha); 334 } 335 KASSERT((bank * MCPGPIO_PINS_PER_BANK) == sc->sc_npins); 336 337 mcpgpio_attach(sc); 338 } 339 340 CFATTACH_DECL_NEW(mcpgpio_spi, sizeof(struct mcpgpio_spi_softc), 341 mcpgpio_spi_match, mcpgpio_spi_attach, NULL, NULL); 342
Indexes created Sat Sep 20 22:09:52 GMT 2025