1 /* $NetBSD: pxg.c,v 1.37 2022/07/20 15:45:28 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for DEC PixelStamp graphics accelerators with onboard SRAM and 34 * Intel i860 co-processor (PMAG-D, E and F). 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: pxg.c,v 1.37 2022/07/20 15:45:28 thorpej Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/proc.h> 46 #include <sys/kauth.h> 47 48 #if defined(pmax) 49 #include <mips/cpuregs.h> 50 #elif defined(alpha) 51 #include <alpha/alpha_cpu.h> 52 #endif 53 54 #include <machine/autoconf.h> 55 #include <sys/cpu.h> 56 #include <sys/bus.h> 57 58 #include <dev/cons.h> 59 60 #include <dev/wscons/wsconsio.h> 61 #include <dev/wscons/wsdisplayvar.h> 62 63 #include <dev/ic/bt459reg.h> 64 65 #include <dev/tc/tcvar.h> 66 #include <dev/tc/sticreg.h> 67 #include <dev/tc/sticio.h> 68 #include <dev/tc/sticvar.h> 69 #include <dev/tc/pxgvar.h> 70 71 #define PXG_STIC_POLL_OFFSET 0x000000 /* STIC DMA poll space */ 72 #define PXG_STAMP_OFFSET 0x0c0000 /* pixelstamp space on STIC */ 73 #define PXG_STIC_OFFSET 0x180000 /* STIC registers */ 74 #define PXG_SRAM_OFFSET 0x200000 /* 128 or 256kB of SRAM */ 75 #define PXG_HOST_INTR_OFFSET 0x280000 /* i860 host interrupt */ 76 #define PXG_COPROC_INTR_OFFSET 0x2c0000 /* i860 coprocessor interrupt */ 77 #define PXG_VDAC_OFFSET 0x300000 /* VDAC registers (bt459) */ 78 #define PXG_VDAC_RESET_OFFSET 0x340000 /* VDAC reset register */ 79 #define PXG_ROM_OFFSET 0x380000 /* ROM code */ 80 #define PXG_I860_START_OFFSET 0x380000 /* i860 start register */ 81 #define PXG_I860_RESET_OFFSET 0x3c0000 /* i860 stop register */ 82 83 static void pxg_attach(device_t, device_t, void *); 84 static int pxg_intr(void *); 85 static int pxg_match(device_t, cfdata_t, void *); 86 87 static void pxg_init(struct stic_info *); 88 static int pxg_ioctl(struct stic_info *, u_long, void *, int, struct lwp *); 89 static uint32_t *pxg_pbuf_get(struct stic_info *); 90 static int pxg_pbuf_post(struct stic_info *, uint32_t *); 91 static int pxg_probe_planes(struct stic_info *); 92 static int pxg_probe_sram(struct stic_info *); 93 94 void pxg_cnattach(tc_addr_t); 95 96 struct pxg_softc { 97 struct stic_info *pxg_si; 98 }; 99 100 CFATTACH_DECL_NEW(pxg, sizeof(struct pxg_softc), 101 pxg_match, pxg_attach, NULL, NULL); 102 103 static const char *pxg_types[] = { 104 "PMAG-DA ", 105 "PMAG-FA ", 106 "PMAG-FB ", 107 "PMAGB-FA", 108 "PMAGB-FB", 109 }; 110 111 static int 112 pxg_match(device_t parent, cfdata_t match, void *aux) 113 { 114 struct tc_attach_args *ta; 115 int i; 116 117 ta = aux; 118 119 for (i = 0; i < sizeof(pxg_types) / sizeof(pxg_types[0]); i++) 120 if (strncmp(pxg_types[i], ta->ta_modname, TC_ROM_LLEN) == 0) 121 return (1); 122 123 return (0); 124 } 125 126 static void 127 pxg_attach(device_t parent, device_t self, void *aux) 128 { 129 struct stic_info *si; 130 struct tc_attach_args *ta; 131 struct pxg_softc *pxg; 132 int console; 133 134 pxg = device_private(self); 135 ta = (struct tc_attach_args *)aux; 136 137 if (ta->ta_addr == stic_consinfo.si_slotbase) { 138 si = &stic_consinfo; 139 console = 1; 140 } else { 141 if (stic_consinfo.si_slotbase == 0) 142 si = &stic_consinfo; 143 else { 144 si = malloc(sizeof(*si), M_DEVBUF, M_WAITOK | M_ZERO); 145 } 146 si->si_slotbase = ta->ta_addr; 147 pxg_init(si); 148 console = 0; 149 } 150 151 pxg->pxg_si = si; 152 si->si_dv = self; 153 tc_intr_establish(parent, ta->ta_cookie, IPL_TTY, pxg_intr, si); 154 155 printf(": %d plane, %dx%d stamp, %dkB SRAM\n", si->si_depth, 156 si->si_stampw, si->si_stamph, (int)si->si_buf_size >> 10); 157 158 stic_attach(self, si, console); 159 160 #ifdef notyet 161 /* Load the co-processor "firmware". */ 162 for (i = 0; i < sizeof(pxg_fwsegs) / sizeof(pxg_fwsegs[0]); i++) 163 pxg_load_fwseg(si, &pxg_fwsegs[i]); 164 165 /* Start the i860. */ 166 si->si_slotbase[PXG_I860_START_OFFSET >> 2] = 1; 167 tc_syncbus(); 168 DELAY(40000); 169 #endif 170 } 171 172 void 173 pxg_cnattach(tc_addr_t addr) 174 { 175 struct stic_info *si; 176 177 si = &stic_consinfo; 178 si->si_slotbase = addr; 179 pxg_init(si); 180 stic_cnattach(si); 181 } 182 183 static void 184 pxg_init(struct stic_info *si) 185 { 186 volatile uint32_t *slot; 187 char *kva; 188 189 kva = (void *)si->si_slotbase; 190 191 si->si_vdac = (uint32_t *)(kva + PXG_VDAC_OFFSET); 192 si->si_vdac_reset = (uint32_t *)(kva + PXG_VDAC_RESET_OFFSET); 193 si->si_stic = (volatile struct stic_regs *)(kva + PXG_STIC_OFFSET); 194 si->si_stamp = (uint32_t *)(kva + PXG_STAMP_OFFSET); 195 si->si_buf = (uint32_t *)(kva + PXG_SRAM_OFFSET); 196 si->si_buf_phys = STIC_KSEG_TO_PHYS(si->si_buf); 197 si->si_buf_size = pxg_probe_sram(si); 198 si->si_disptype = WSDISPLAY_TYPE_PXG; 199 si->si_sxc = (volatile struct stic_xcomm *)si->si_buf; 200 201 si->si_pbuf_get = pxg_pbuf_get; 202 si->si_pbuf_post = pxg_pbuf_post; 203 si->si_ioctl = pxg_ioctl; 204 205 /* Disable the co-processor. */ 206 slot = (volatile uint32_t *)kva; 207 slot[PXG_I860_RESET_OFFSET >> 2] = 0; 208 tc_wmb(); 209 slot[PXG_HOST_INTR_OFFSET >> 2] = 0; 210 tc_syncbus(); 211 DELAY(40000); 212 213 /* XXX Check for a second PixelStamp. */ 214 if (((si->si_stic->sr_modcl & 0x600) >> 9) > 1) 215 si->si_depth = 24; 216 else 217 si->si_depth = pxg_probe_planes(si); 218 219 stic_init(si); 220 } 221 222 static int 223 pxg_probe_sram(struct stic_info *si) 224 { 225 volatile uint32_t *a, *b; 226 227 a = (volatile uint32_t *)si->si_slotbase + (PXG_SRAM_OFFSET >> 2); 228 b = a + (0x20000 >> 2); 229 *a = 4321; 230 *b = 1234; 231 tc_mb(); 232 return ((*a == *b) ? 0x20000 : 0x40000); 233 } 234 235 static int 236 pxg_probe_planes(struct stic_info *si) 237 { 238 volatile uint32_t *vdac; 239 int id; 240 241 /* 242 * For the visible framebuffer (# 0), we can cheat and use the VDAC 243 * ID. 244 */ 245 vdac = si->si_vdac; 246 vdac[BT459_REG_ADDR_LOW] = (BT459_IREG_ID & 0xff) | 247 ((BT459_IREG_ID & 0xff) << 8) | ((BT459_IREG_ID & 0xff) << 16); 248 vdac[BT459_REG_ADDR_HIGH] = ((BT459_IREG_ID & 0xff00) >> 8) | 249 (BT459_IREG_ID & 0xff00) | ((BT459_IREG_ID & 0xff00) << 8); 250 tc_mb(); 251 id = vdac[BT459_REG_IREG_DATA] & 0x00ffffff; 252 253 /* 3 VDACs */ 254 if (id == 0x004a4a4a) 255 return (24); 256 257 /* 1 VDAC */ 258 if ((id & 0xff0000) == 0x4a0000 || (id & 0x00ff00) == 0x004a00 || 259 (id & 0x0000ff) == 0x00004a) 260 return (8); 261 262 /* XXX Assume 8 planes. */ 263 printf("pxg_probe_planes: invalid VDAC ID %x\n", id); 264 return (8); 265 } 266 267 static int 268 pxg_intr(void *cookie) 269 { 270 #ifdef notyet 271 struct stic_info *si; 272 volatile struct stic_regs *sr; 273 volatile uint32_t *hi; 274 uint32_t state; 275 int it; 276 277 si = cookie; 278 sr = si->si_stic; 279 state = sr->sr_ipdvint; 280 hi = (volatile uint32_t *)si->si_slotbase + 281 (PXG_HOST_INTR_OFFSET / sizeof(uint32_t)); 282 283 /* Clear the interrupt condition */ 284 it = hi[0] & 15; 285 hi[0] = 0; 286 tc_wmb(); 287 hi[2] = 0; 288 tc_wmb(); 289 290 switch (it) { 291 case 3: 292 sr->sr_ipdvint = STIC_INT_V_WE | STIC_INT_V_EN; 293 tc_wmb(); 294 stic_flush(si); 295 break; 296 } 297 #else 298 printf("pxg_intr: how did this happen?\n"); 299 #endif 300 return (1); 301 } 302 303 static uint32_t * 304 pxg_pbuf_get(struct stic_info *si) 305 { 306 u_long off; 307 308 si->si_pbuf_select ^= STIC_PACKET_SIZE; 309 off = si->si_pbuf_select + STIC_XCOMM_SIZE; 310 return ((uint32_t *)((char *)si->si_buf + off)); 311 } 312 313 static int 314 pxg_pbuf_post(struct stic_info *si, uint32_t *buf) 315 { 316 volatile uint32_t *poll, junk; 317 volatile struct stic_regs *sr; 318 u_long v; 319 int c; 320 321 sr = si->si_stic; 322 323 /* Get address of poll register for this buffer. */ 324 v = ((u_long)buf - (u_long)si->si_buf) >> 9; 325 poll = (volatile uint32_t *)((char *)si->si_slotbase + v); 326 327 /* 328 * Read the poll register and make sure the stamp wants to accept 329 * our packet. This read will initiate the DMA. Don't wait for 330 * ever, just in case something's wrong. 331 */ 332 tc_mb(); 333 334 for (c = STAMP_RETRIES; c != 0; c--) { 335 if ((sr->sr_ipdvint & STIC_INT_P) != 0) { 336 sr->sr_ipdvint = STIC_INT_P_WE; 337 tc_wmb(); 338 junk = *poll; 339 __USE(junk); 340 return (0); 341 } 342 DELAY(STAMP_DELAY); 343 } 344 345 /* STIC has lost the plot, punish it. */ 346 stic_reset(si); 347 return (-1); 348 } 349 350 static int 351 pxg_ioctl(struct stic_info *si, u_long cmd, void *data, int flag, 352 struct lwp *l) 353 { 354 struct stic_xinfo *sxi; 355 volatile uint32_t *ptr = NULL; 356 int rv, s; 357 358 switch (cmd) { 359 case STICIO_START860: 360 case STICIO_RESET860: 361 if ((rv = kauth_authorize_machdep(l->l_cred, 362 KAUTH_MACHDEP_PXG, KAUTH_ARG(cmd == STICIO_START860 ? 1 : 0), 363 NULL, NULL, NULL)) != 0) 364 return (rv); 365 if (si->si_dispmode != WSDISPLAYIO_MODE_MAPPED) 366 return (EBUSY); 367 ptr = (volatile uint32_t *)si->si_slotbase; 368 break; 369 } 370 371 switch (cmd) { 372 case STICIO_START860: 373 s = spltty(); 374 ptr[PXG_I860_START_OFFSET >> 2] = 1; 375 tc_wmb(); 376 splx(s); 377 rv = 0; 378 break; 379 380 case STICIO_RESET860: 381 s = spltty(); 382 ptr[PXG_I860_RESET_OFFSET >> 2] = 0; 383 tc_wmb(); 384 splx(s); 385 rv = 0; 386 break; 387 388 case STICIO_GXINFO: 389 sxi = (struct stic_xinfo *)data; 390 sxi->sxi_unit = si->si_unit; 391 sxi->sxi_stampw = si->si_stampw; 392 sxi->sxi_stamph = si->si_stamph; 393 sxi->sxi_buf_size = si->si_buf_size; 394 sxi->sxi_buf_phys = 0; 395 sxi->sxi_buf_pktoff = STIC_XCOMM_SIZE; 396 sxi->sxi_buf_pktcnt = 2; 397 sxi->sxi_buf_imgoff = STIC_XCOMM_SIZE + STIC_PACKET_SIZE * 2; 398 rv = 0; 399 break; 400 401 default: 402 rv = EPASSTHROUGH; 403 break; 404 } 405 406 return (rv); 407 } 408 409 #ifdef notyet 410 void 411 pxg_load_fwseg(struct stic_info *si, struct pxg_fwseg *pfs) 412 { 413 const uint32_t *src; 414 uint32_t *dst; 415 u_int left, i; 416 417 dst = (uint32_t *)((void *)si->si_buf + pfs->pfs_addr); 418 src = pfs->pfs_data; 419 420 for (left = pfs->pfs_compsize; left != 0; left -= 4) { 421 if (src[0] == PXGFW_RLE_MAGIC) { 422 for (i = src[2]; i != 0; i--) 423 *dst++ = src[1]; 424 src += 3; 425 } else { 426 *dst++ = src[0]; 427 src++; 428 } 429 } 430 431 if (src == NULL) 432 memset(dst, 0, pfs->pfs_realsize); 433 } 434 #endif 435
Indexes created Sun Sep 21 16:09:51 GMT 2025