pxg.c revision 1.1
1 /* $NetBSD: pxg.c,v 1.1 2000/12/17 13:52:04 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Driver for DEC PixelStamp graphics accelerators with onboard SRAM and 41 * Intel i860 co-processor (PMAG-D, E and F). 42 */ 43 44 #include <sys/param.h> 45 #include <sys/types.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/malloc.h> 49 #include <sys/callout.h> 50 51 #if defined(pmax) 52 #include <mips/cpuregs.h> 53 #elif defined(alpha) 54 #include <alpha/alpha_cpu.h> 55 #endif 56 57 #include <machine/autoconf.h> 58 #include <machine/cpu.h> 59 #include <machine/bus.h> 60 61 #include <dev/cons.h> 62 63 #include <dev/wscons/wsconsio.h> 64 #include <dev/wscons/wsdisplayvar.h> 65 66 #include <dev/ic/bt459reg.h> 67 68 #include <dev/tc/tcvar.h> 69 #include <dev/tc/sticreg.h> 70 #include <dev/tc/sticvar.h> 71 72 #define PXG_STIC_POLL_OFFSET 0x000000 /* STIC DMA poll space */ 73 #define PXG_STAMP_OFFSET 0x0c0000 /* pixelstamp space on STIC */ 74 #define PXG_STIC_OFFSET 0x180000 /* STIC registers */ 75 #define PXG_SRAM_OFFSET 0x200000 /* N10 SRAM */ 76 #define PXG_HOST_INTR_OFFSET 0x280000 /* N10 host interrupt */ 77 #define PXG_COPROC_INTR_OFFSET 0x2c0000 /* N10 coprocessor interrupt */ 78 #define PXG_VDAC_OFFSET 0x300000 /* VDAC registers (bt459) */ 79 #define PXG_VDAC_RESET_OFFSET 0x340000 /* VDAC reset register */ 80 #define PXG_ROM_OFFSET 0x380000 /* ROM code */ 81 #define PXG_N10_START_OFFSET 0x380000 /* N10 start register */ 82 #define PXG_N10_RESET_OFFSET 0x3c0000 /* N10 stop register */ 83 84 static void pxg_attach(struct device *, struct device *, void *); 85 static int pxg_intr(void *); 86 static int pxg_match(struct device *, struct cfdata *, void *); 87 88 static void pxg_init(struct stic_info *); 89 static u_int32_t *pxg_pbuf_get(struct stic_info *); 90 static int pxg_pbuf_post(struct stic_info *, u_int32_t *); 91 static int pxg_probe_planes(struct stic_info *); 92 static int pxg_probe_sram(struct stic_info *); 93 94 void pxg_cnattach(tc_addr_t); 95 96 struct pxg_softc { 97 struct device pxg_dv; 98 struct stic_info *pxg_si; 99 }; 100 101 struct cfattach pxg_ca = { 102 sizeof(struct pxg_softc), pxg_match, pxg_attach 103 }; 104 105 static const char *pxg_types[] = { 106 "PMAG-DA ", "LM-3DA", 107 "PMAG-FA ", "HE-3DA", 108 "PMAG-FB ", "HE+3DA", 109 "PMAGB-FA", "HE+3DA", 110 "PMAGB-FB", "HE+3DA", 111 }; 112 113 static int 114 pxg_match(struct device *parent, struct cfdata *match, void *aux) 115 { 116 struct tc_attach_args *ta; 117 int i; 118 119 ta = aux; 120 121 for (i = 0; i < sizeof(pxg_types) / sizeof(pxg_types[0]); i += 2) 122 if (strncmp(pxg_types[i], ta->ta_modname, TC_ROM_LLEN) == 0) 123 return (1); 124 125 return (0); 126 } 127 128 static void 129 pxg_attach(struct device *parent, struct device *self, void *aux) 130 { 131 struct stic_info *si; 132 struct tc_attach_args *ta; 133 struct pxg_softc *pxg; 134 int console, i; 135 136 pxg = (struct pxg_softc *)self; 137 ta = (struct tc_attach_args *)aux; 138 139 if (ta->ta_addr == stic_consinfo.si_slotbase) { 140 si = &stic_consinfo; 141 console = 1; 142 } else { 143 if (stic_consinfo.si_slotbase == NULL) 144 si = &stic_consinfo; 145 else { 146 si = malloc(sizeof(*si), M_DEVBUF, M_NOWAIT); 147 memset(si, 0, sizeof(*si)); 148 } 149 si->si_slotbase = ta->ta_addr; 150 pxg_init(si); 151 console = 0; 152 } 153 154 pxg->pxg_si = si; 155 tc_intr_establish(parent, ta->ta_cookie, IPL_TTY, pxg_intr, si); 156 157 for (i = 0; i < sizeof(pxg_types) / sizeof(pxg_types[0]); i += 2) 158 if (strncmp(pxg_types[i], ta->ta_modname, TC_ROM_LLEN) == 0) 159 break; 160 161 printf(": %s, %d plane, %dx%d stamp, %dkB SRAM\n", pxg_types[i + 1], 162 si->si_depth, si->si_stampw, si->si_stamph, si->si_buf_size >> 10); 163 164 stic_attach(self, si, console); 165 } 166 167 void 168 pxg_cnattach(tc_addr_t addr) 169 { 170 struct stic_info *si; 171 172 si = &stic_consinfo; 173 si->si_slotbase = addr; 174 pxg_init(si); 175 stic_cnattach(si); 176 } 177 178 static void 179 pxg_init(struct stic_info *si) 180 { 181 volatile u_int32_t *slot; 182 caddr_t kva; 183 paddr_t bpa; 184 185 kva = (caddr_t)TC_PHYS_TO_UNCACHED(si->si_slotbase); 186 bpa = STIC_KSEG_TO_PHYS((caddr_t)kva + PXG_SRAM_OFFSET); 187 slot = (volatile u_int32_t *)kva; 188 189 si->si_slotkva = (u_int32_t *)kva; 190 si->si_vdac = (u_int32_t *)(kva + PXG_VDAC_OFFSET); 191 si->si_vdac_reset = (u_int32_t *)(kva + PXG_VDAC_RESET_OFFSET); 192 si->si_stic = (volatile struct stic_regs *)(kva + PXG_STIC_OFFSET); 193 si->si_stamp = (u_int32_t *)(kva + PXG_STAMP_OFFSET); 194 si->si_buf = (u_int32_t *)TC_PHYS_TO_UNCACHED(bpa); 195 si->si_buf_phys = bpa; 196 si->si_buf_size = pxg_probe_sram(si); 197 si->si_disptype = WSDISPLAY_TYPE_PXG; 198 199 si->si_pbuf_get = pxg_pbuf_get; 200 si->si_pbuf_post = pxg_pbuf_post; 201 202 /* Disable the co-processor. */ 203 slot[PXG_N10_RESET_OFFSET >> 2] = 0; 204 tc_syncbus(); 205 slot[PXG_HOST_INTR_OFFSET >> 2] = 0; 206 tc_syncbus(); 207 DELAY(40000); 208 209 /* XXX Check for a second PixelStamp. */ 210 if (((si->si_stic->sr_modcl & 0x600) >> 9) > 1) 211 si->si_depth = 24; 212 else 213 si->si_depth = pxg_probe_planes(si); 214 215 #ifdef notdef 216 /* Restart the co-processor and enable STIC interrupts */ 217 slot[PXG_N10_START_OFFSET >> 2] = 1; 218 tc_syncbus(); 219 DELAY(2000); 220 sr->sr_sticsr = STIC_INT_WE | STIC_INT_CLR; 221 tc_wmb(); 222 #endif 223 224 stic_init(si); 225 } 226 227 static int 228 pxg_probe_sram(struct stic_info *si) 229 { 230 volatile u_int32_t *a, *b; 231 232 a = si->si_slotkva + (PXG_SRAM_OFFSET >> 2); 233 b = a + (0x20000 >> 1); 234 *a = 4321; 235 *b = 1234; 236 tc_syncbus(); 237 return ((*a == *b) ? 0x20000 : 0x40000); 238 } 239 240 static int 241 pxg_probe_planes(struct stic_info *si) 242 { 243 volatile u_int32_t *vdac; 244 int id; 245 246 /* 247 * For the visible framebuffer (# 0), we can cheat and use the VDAC 248 * ID. 249 */ 250 vdac = si->si_vdac; 251 vdac[BT459_REG_ADDR_LOW] = (BT459_IREG_ID & 0xff) | 252 ((BT459_IREG_ID & 0xff) << 8) | ((BT459_IREG_ID & 0xff) << 16); 253 vdac[BT459_REG_ADDR_HIGH] = ((BT459_IREG_ID & 0xff00) >> 8) | 254 (BT459_IREG_ID & 0xff00) | ((BT459_IREG_ID & 0xff00) << 8); 255 tc_syncbus(); 256 id = vdac[BT459_REG_IREG_DATA] & 0x00ffffff; 257 258 /* 3 VDACs */ 259 if (id == 0x004a4a4a) 260 return (24); 261 262 /* 1 VDAC */ 263 if ((id & 0xff0000) == 0x4a0000 || (id & 0x00ff00) == 0x004a00 || 264 (id & 0x0000ff) == 0x00004a) 265 return (8); 266 267 /* XXX Assume 8 planes. */ 268 printf("pxg_probe_planes: invalid VDAC ID %x\n", id); 269 return (8); 270 } 271 272 static int 273 pxg_intr(void *cookie) 274 { 275 struct stic_info *si; 276 volatile struct stic_regs *sr; 277 volatile u_int32_t *hi; 278 u_int32_t state; 279 int it; 280 281 si = cookie; 282 sr = si->si_stic; 283 state = sr->sr_ipdvint; 284 hi = si->si_slotkva + (PXG_HOST_INTR_OFFSET / sizeof(u_int32_t)); 285 286 /* Clear the interrupt condition */ 287 it = hi[0] & 15; 288 hi[0] = 0; 289 tc_wmb(); 290 hi[2] = 0; 291 tc_wmb(); 292 293 /* 294 * Since we disable the co-processor, we won't get to see vblank 295 * interrupts (so in effect, this code is useless). 296 * 297 * Packet-done and error interrupts will only ever be seen by the 298 * co-processor (although ULTRIX seems to think that they're posted 299 * to us - more investigation required). 300 */ 301 if (it == 3) { 302 sr->sr_ipdvint = 303 STIC_INT_V_WE | (sr->sr_ipdvint & STIC_INT_V_EN); 304 tc_wmb(); 305 stic_flush(si); 306 } 307 308 return (1); 309 } 310 311 static u_int32_t * 312 pxg_pbuf_get(struct stic_info *si) 313 { 314 #ifdef notdef 315 volatile u_int32_t *poll; 316 317 /* Ask N10 which buffer to use */ 318 poll = si->si_slotkva; 319 poll += PXG_COPROC_INTR_OFFSET >> 2; 320 321 /* 322 * XXX These should be defined as constants. 0x30 is "pause 323 * coprocessor and interrupt." 324 */ 325 *poll = 0x30; 326 tc_wmb(); 327 328 for (i = 1000000; i; i--) { 329 DELAY(4); 330 switch(j = *poll) { 331 case 2: 332 si->si_pbuf_select = STIC_PACKET_SIZE; 333 break; 334 case 1: 335 si->si_pbuf_select = 0; 336 break; 337 default: 338 if (j == 0x30) 339 continue; 340 break; 341 } 342 break; 343 } 344 345 if (j != 1 || j != 2) { 346 /* STIC has lost the plot, punish it */ 347 stic_reset(si); 348 si->si_pbuf_select = 0; 349 } 350 #else 351 352 /* 353 * XXX We should be synchronizing with STIC_INT_P so that an ISR 354 * doesn't blow us up. 355 */ 356 si->si_pbuf_select ^= STIC_PACKET_SIZE; 357 #endif 358 return ((u_int32_t *)((caddr_t)si->si_buf + si->si_pbuf_select)); 359 } 360 361 static int 362 pxg_pbuf_post(struct stic_info *si, u_int32_t *buf) 363 { 364 volatile u_int32_t *poll; 365 u_long v; 366 int c; 367 368 /* Get address of poll register for this buffer. */ 369 v = ((u_long)buf - (u_long)si->si_buf) >> 9; 370 poll = (volatile u_int32_t *)((caddr_t)si->si_slotkva + v); 371 372 /* 373 * Read the poll register and make sure the stamp wants to accept 374 * our packet. This read will initiate the DMA. Don't wait for 375 * ever, just in case something's wrong. 376 */ 377 tc_syncbus(); 378 379 for (c = STAMP_RETRIES; c != 0; c--) { 380 if (*poll == STAMP_OK) { 381 #ifdef notdef 382 /* Tell the co-processor that we are done. */ 383 poll = si->si_slotkva + (PXG_HOST_INTR_OFFSET >> 2); 384 poll[0] = 0; 385 tc_wmb(); 386 poll[2] = 0; 387 tc_wmb(); 388 #endif 389 return (0); 390 } 391 392 DELAY(STAMP_DELAY); 393 } 394 395 /* STIC has lost the plot, punish it. */ 396 stic_reset(si); 397 return (-1); 398 } 399
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