pxg.c revision 1.13
1 /* $NetBSD: pxg.c,v 1.13 2002/10/02 16:53:05 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Driver for DEC PixelStamp graphics accelerators with onboard SRAM and 41 * Intel i860 co-processor (PMAG-D, E and F). 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: pxg.c,v 1.13 2002/10/02 16:53:05 thorpej Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 #include <sys/callout.h> 52 #include <sys/proc.h> 53 54 #if defined(pmax) 55 #include <mips/cpuregs.h> 56 #elif defined(alpha) 57 #include <alpha/alpha_cpu.h> 58 #endif 59 60 #include <machine/autoconf.h> 61 #include <machine/cpu.h> 62 #include <machine/bus.h> 63 64 #include <dev/cons.h> 65 66 #include <dev/wscons/wsconsio.h> 67 #include <dev/wscons/wsdisplayvar.h> 68 69 #include <dev/ic/bt459reg.h> 70 71 #include <dev/tc/tcvar.h> 72 #include <dev/tc/sticreg.h> 73 #include <dev/tc/sticio.h> 74 #include <dev/tc/sticvar.h> 75 #include <dev/tc/pxgvar.h> 76 77 #define PXG_STIC_POLL_OFFSET 0x000000 /* STIC DMA poll space */ 78 #define PXG_STAMP_OFFSET 0x0c0000 /* pixelstamp space on STIC */ 79 #define PXG_STIC_OFFSET 0x180000 /* STIC registers */ 80 #define PXG_SRAM_OFFSET 0x200000 /* 128 or 256kB of SRAM */ 81 #define PXG_HOST_INTR_OFFSET 0x280000 /* i860 host interrupt */ 82 #define PXG_COPROC_INTR_OFFSET 0x2c0000 /* i860 coprocessor interrupt */ 83 #define PXG_VDAC_OFFSET 0x300000 /* VDAC registers (bt459) */ 84 #define PXG_VDAC_RESET_OFFSET 0x340000 /* VDAC reset register */ 85 #define PXG_ROM_OFFSET 0x380000 /* ROM code */ 86 #define PXG_I860_START_OFFSET 0x380000 /* i860 start register */ 87 #define PXG_I860_RESET_OFFSET 0x3c0000 /* i860 stop register */ 88 89 void pxg_attach(struct device *, struct device *, void *); 90 int pxg_intr(void *); 91 int pxg_match(struct device *, struct cfdata *, void *); 92 93 void pxg_init(struct stic_info *); 94 int pxg_ioctl(struct stic_info *, u_long, caddr_t, int, struct proc *); 95 u_int32_t *pxg_pbuf_get(struct stic_info *); 96 int pxg_pbuf_post(struct stic_info *, u_int32_t *); 97 int pxg_probe_planes(struct stic_info *); 98 int pxg_probe_sram(struct stic_info *); 99 100 void pxg_cnattach(tc_addr_t); 101 102 struct pxg_softc { 103 struct device pxg_dv; 104 struct stic_info *pxg_si; 105 }; 106 107 CFATTACH_DECL(pxg, sizeof(struct pxg_softc), 108 pxg_match, pxg_attach, NULL, NULL); 109 110 static const char *pxg_types[] = { 111 "PMAG-DA ", 112 "PMAG-FA ", 113 "PMAG-FB ", 114 "PMAGB-FA", 115 "PMAGB-FB", 116 }; 117 118 int 119 pxg_match(struct device *parent, struct cfdata *match, void *aux) 120 { 121 struct tc_attach_args *ta; 122 int i; 123 124 ta = aux; 125 126 for (i = 0; i < sizeof(pxg_types) / sizeof(pxg_types[0]); i++) 127 if (strncmp(pxg_types[i], ta->ta_modname, TC_ROM_LLEN) == 0) 128 return (1); 129 130 return (0); 131 } 132 133 void 134 pxg_attach(struct device *parent, struct device *self, void *aux) 135 { 136 struct stic_info *si; 137 struct tc_attach_args *ta; 138 struct pxg_softc *pxg; 139 int console; 140 141 pxg = (struct pxg_softc *)self; 142 ta = (struct tc_attach_args *)aux; 143 144 if (ta->ta_addr == stic_consinfo.si_slotbase) { 145 si = &stic_consinfo; 146 console = 1; 147 } else { 148 if (stic_consinfo.si_slotbase == NULL) 149 si = &stic_consinfo; 150 else { 151 si = malloc(sizeof(*si), M_DEVBUF, M_NOWAIT|M_ZERO); 152 } 153 si->si_slotbase = ta->ta_addr; 154 pxg_init(si); 155 console = 0; 156 } 157 158 pxg->pxg_si = si; 159 si->si_dv = self; 160 tc_intr_establish(parent, ta->ta_cookie, IPL_TTY, pxg_intr, si); 161 162 printf(": %d plane, %dx%d stamp, %dkB SRAM\n", si->si_depth, 163 si->si_stampw, si->si_stamph, (int)si->si_buf_size >> 10); 164 165 stic_attach(self, si, console); 166 167 #ifdef notyet 168 /* Load the co-processor "firmware". */ 169 for (i = 0; i < sizeof(pxg_fwsegs) / sizeof(pxg_fwsegs[0]); i++) 170 pxg_load_fwseg(si, &pxg_fwsegs[i]); 171 172 /* Start the i860. */ 173 si->si_slotbase[PXG_I860_START_OFFSET >> 2] = 1; 174 tc_wmb(); 175 tc_syncbus(); 176 DELAY(40000); 177 #endif 178 } 179 180 void 181 pxg_cnattach(tc_addr_t addr) 182 { 183 struct stic_info *si; 184 185 si = &stic_consinfo; 186 si->si_slotbase = addr; 187 pxg_init(si); 188 stic_cnattach(si); 189 } 190 191 void 192 pxg_init(struct stic_info *si) 193 { 194 volatile u_int32_t *slot; 195 caddr_t kva; 196 197 kva = (caddr_t)si->si_slotbase; 198 199 si->si_vdac = (u_int32_t *)(kva + PXG_VDAC_OFFSET); 200 si->si_vdac_reset = (u_int32_t *)(kva + PXG_VDAC_RESET_OFFSET); 201 si->si_stic = (volatile struct stic_regs *)(kva + PXG_STIC_OFFSET); 202 si->si_stamp = (u_int32_t *)(kva + PXG_STAMP_OFFSET); 203 si->si_buf = (u_int32_t *)(kva + PXG_SRAM_OFFSET); 204 si->si_buf_phys = STIC_KSEG_TO_PHYS(si->si_buf); 205 si->si_buf_size = pxg_probe_sram(si); 206 si->si_disptype = WSDISPLAY_TYPE_PXG; 207 si->si_sxc = (volatile struct stic_xcomm *)si->si_buf; 208 209 si->si_pbuf_get = pxg_pbuf_get; 210 si->si_pbuf_post = pxg_pbuf_post; 211 si->si_ioctl = pxg_ioctl; 212 213 /* Disable the co-processor. */ 214 slot = (volatile u_int32_t *)kva; 215 slot[PXG_I860_RESET_OFFSET >> 2] = 0; 216 tc_wmb(); 217 slot[PXG_HOST_INTR_OFFSET >> 2] = 0; 218 tc_wmb(); 219 tc_syncbus(); 220 DELAY(40000); 221 222 /* XXX Check for a second PixelStamp. */ 223 if (((si->si_stic->sr_modcl & 0x600) >> 9) > 1) 224 si->si_depth = 24; 225 else 226 si->si_depth = pxg_probe_planes(si); 227 228 stic_init(si); 229 } 230 231 int 232 pxg_probe_sram(struct stic_info *si) 233 { 234 volatile u_int32_t *a, *b; 235 236 a = (volatile u_int32_t *)si->si_slotbase + (PXG_SRAM_OFFSET >> 2); 237 b = a + (0x20000 >> 2); 238 *a = 4321; 239 *b = 1234; 240 tc_mb(); 241 return ((*a == *b) ? 0x20000 : 0x40000); 242 } 243 244 int 245 pxg_probe_planes(struct stic_info *si) 246 { 247 volatile u_int32_t *vdac; 248 int id; 249 250 /* 251 * For the visible framebuffer (# 0), we can cheat and use the VDAC 252 * ID. 253 */ 254 vdac = si->si_vdac; 255 vdac[BT459_REG_ADDR_LOW] = (BT459_IREG_ID & 0xff) | 256 ((BT459_IREG_ID & 0xff) << 8) | ((BT459_IREG_ID & 0xff) << 16); 257 vdac[BT459_REG_ADDR_HIGH] = ((BT459_IREG_ID & 0xff00) >> 8) | 258 (BT459_IREG_ID & 0xff00) | ((BT459_IREG_ID & 0xff00) << 8); 259 tc_mb(); 260 id = vdac[BT459_REG_IREG_DATA] & 0x00ffffff; 261 262 /* 3 VDACs */ 263 if (id == 0x004a4a4a) 264 return (24); 265 266 /* 1 VDAC */ 267 if ((id & 0xff0000) == 0x4a0000 || (id & 0x00ff00) == 0x004a00 || 268 (id & 0x0000ff) == 0x00004a) 269 return (8); 270 271 /* XXX Assume 8 planes. */ 272 printf("pxg_probe_planes: invalid VDAC ID %x\n", id); 273 return (8); 274 } 275 276 int 277 pxg_intr(void *cookie) 278 { 279 #ifdef notyet 280 struct stic_info *si; 281 volatile struct stic_regs *sr; 282 volatile u_int32_t *hi; 283 u_int32_t state; 284 int it; 285 286 si = cookie; 287 sr = si->si_stic; 288 state = sr->sr_ipdvint; 289 hi = (volatile u_int32_t *)si->si_slotbase + 290 (PXG_HOST_INTR_OFFSET / sizeof(u_int32_t)); 291 292 /* Clear the interrupt condition */ 293 it = hi[0] & 15; 294 hi[0] = 0; 295 tc_wmb(); 296 hi[2] = 0; 297 tc_wmb(); 298 299 switch (it) { 300 case 3: 301 sr->sr_ipdvint = STIC_INT_V_WE | STIC_INT_V_EN; 302 tc_wmb(); 303 stic_flush(si); 304 break; 305 } 306 #else 307 printf("pxg_intr: how did this happen?\n"); 308 #endif 309 return (1); 310 } 311 312 u_int32_t * 313 pxg_pbuf_get(struct stic_info *si) 314 { 315 u_long off; 316 317 si->si_pbuf_select ^= STIC_PACKET_SIZE; 318 off = si->si_pbuf_select + STIC_XCOMM_SIZE; 319 return ((u_int32_t *)((caddr_t)si->si_buf + off)); 320 } 321 322 int 323 pxg_pbuf_post(struct stic_info *si, u_int32_t *buf) 324 { 325 volatile u_int32_t *poll, junk; 326 volatile struct stic_regs *sr; 327 u_long v; 328 int c; 329 330 sr = si->si_stic; 331 332 /* Get address of poll register for this buffer. */ 333 v = ((u_long)buf - (u_long)si->si_buf) >> 9; 334 poll = (volatile u_int32_t *)((caddr_t)si->si_slotbase + v); 335 336 /* 337 * Read the poll register and make sure the stamp wants to accept 338 * our packet. This read will initiate the DMA. Don't wait for 339 * ever, just in case something's wrong. 340 */ 341 tc_mb(); 342 343 for (c = STAMP_RETRIES; c != 0; c--) { 344 if ((sr->sr_ipdvint & STIC_INT_P) != 0) { 345 sr->sr_ipdvint = STIC_INT_P_WE; 346 tc_wmb(); 347 junk = *poll; 348 return (0); 349 } 350 DELAY(STAMP_DELAY); 351 } 352 353 /* STIC has lost the plot, punish it. */ 354 stic_reset(si); 355 return (-1); 356 } 357 358 int 359 pxg_ioctl(struct stic_info *si, u_long cmd, caddr_t data, int flag, 360 struct proc *p) 361 { 362 struct stic_xinfo *sxi; 363 volatile u_int32_t *ptr; 364 int rv, s; 365 366 switch (cmd) { 367 case STICIO_START860: 368 case STICIO_RESET860: 369 if ((rv = suser(p->p_ucred, &p->p_acflag)) != 0) 370 return (rv); 371 if (si->si_dispmode != WSDISPLAYIO_MODE_MAPPED) 372 return (EBUSY); 373 ptr = (volatile u_int32_t *)si->si_slotbase; 374 break; 375 } 376 377 switch (cmd) { 378 case STICIO_START860: 379 s = spltty(); 380 ptr[PXG_I860_START_OFFSET >> 2] = 1; 381 tc_wmb(); 382 splx(s); 383 rv = 0; 384 break; 385 386 case STICIO_RESET860: 387 s = spltty(); 388 ptr[PXG_I860_RESET_OFFSET >> 2] = 0; 389 tc_wmb(); 390 splx(s); 391 rv = 0; 392 break; 393 394 case STICIO_GXINFO: 395 sxi = (struct stic_xinfo *)data; 396 sxi->sxi_unit = si->si_unit; 397 sxi->sxi_stampw = si->si_stampw; 398 sxi->sxi_stamph = si->si_stamph; 399 sxi->sxi_buf_size = si->si_buf_size; 400 sxi->sxi_buf_phys = 0; 401 sxi->sxi_buf_pktoff = STIC_XCOMM_SIZE; 402 sxi->sxi_buf_pktcnt = 2; 403 sxi->sxi_buf_imgoff = STIC_XCOMM_SIZE + STIC_PACKET_SIZE * 2; 404 rv = 0; 405 break; 406 407 default: 408 rv = EPASSTHROUGH; 409 break; 410 } 411 412 return (rv); 413 } 414 415 #ifdef notyet 416 void 417 pxg_load_fwseg(struct stic_info *si, struct pxg_fwseg *pfs) 418 { 419 const u_int32_t *src; 420 u_int32_t *dst; 421 u_int left, i; 422 423 dst = (u_int32_t *)((caddr_t)si->si_buf + pfs->pfs_addr); 424 src = pfs->pfs_data; 425 426 for (left = pfs->pfs_compsize; left != 0; left -= 4) { 427 if (src[0] == PXGFW_RLE_MAGIC) { 428 for (i = src[2]; i != 0; i--) 429 *dst++ = src[1]; 430 src += 3; 431 } else { 432 *dst++ = src[0]; 433 src++; 434 } 435 } 436 437 if (src == NULL) 438 memset(dst, 0, pfs->pfs_realsize); 439 } 440 #endif 441
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