pxg.c revision 1.2.2.2
1 /* $NetBSD: pxg.c,v 1.2.2.2 2001/01/05 17:36:28 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Driver for DEC PixelStamp graphics accelerators with onboard SRAM and 41 * Intel i860 co-processor (PMAG-D, E and F). 42 */ 43 44 #include <sys/param.h> 45 #include <sys/types.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/malloc.h> 49 #include <sys/callout.h> 50 #include <sys/proc.h> 51 52 #if defined(pmax) 53 #include <mips/cpuregs.h> 54 #elif defined(alpha) 55 #include <alpha/alpha_cpu.h> 56 #endif 57 58 #include <machine/autoconf.h> 59 #include <machine/cpu.h> 60 #include <machine/bus.h> 61 62 #include <dev/cons.h> 63 64 #include <dev/wscons/wsconsio.h> 65 #include <dev/wscons/wsdisplayvar.h> 66 67 #include <dev/ic/bt459reg.h> 68 69 #include <dev/tc/tcvar.h> 70 #include <dev/tc/sticreg.h> 71 #include <dev/tc/sticvar.h> 72 73 #define PXG_STIC_POLL_OFFSET 0x000000 /* STIC DMA poll space */ 74 #define PXG_STAMP_OFFSET 0x0c0000 /* pixelstamp space on STIC */ 75 #define PXG_STIC_OFFSET 0x180000 /* STIC registers */ 76 #define PXG_SRAM_OFFSET 0x200000 /* i860 SRAM */ 77 #define PXG_HOST_INTR_OFFSET 0x280000 /* i860 host interrupt */ 78 #define PXG_COPROC_INTR_OFFSET 0x2c0000 /* i860 coprocessor interrupt */ 79 #define PXG_VDAC_OFFSET 0x300000 /* VDAC registers (bt459) */ 80 #define PXG_VDAC_RESET_OFFSET 0x340000 /* VDAC reset register */ 81 #define PXG_ROM_OFFSET 0x380000 /* ROM code */ 82 #define PXG_I860_START_OFFSET 0x380000 /* i860 start register */ 83 #define PXG_I860_RESET_OFFSET 0x3c0000 /* i860 stop register */ 84 85 static void pxg_attach(struct device *, struct device *, void *); 86 static int pxg_intr(void *); 87 static int pxg_match(struct device *, struct cfdata *, void *); 88 89 static void pxg_init(struct stic_info *); 90 static int pxg_ioctl(struct stic_info *, u_long, caddr_t, int, 91 struct proc *); 92 static u_int32_t *pxg_pbuf_get(struct stic_info *); 93 static int pxg_pbuf_post(struct stic_info *, u_int32_t *); 94 static int pxg_probe_planes(struct stic_info *); 95 static int pxg_probe_sram(struct stic_info *); 96 97 void pxg_cnattach(tc_addr_t); 98 99 struct pxg_softc { 100 struct device pxg_dv; 101 struct stic_info *pxg_si; 102 }; 103 104 struct cfattach pxg_ca = { 105 sizeof(struct pxg_softc), pxg_match, pxg_attach 106 }; 107 108 static const char *pxg_types[] = { 109 "PMAG-DA ", "LM-3DA", 110 "PMAG-FA ", "HE-3DA", 111 "PMAG-FB ", "HE+3DA", 112 "PMAGB-FA", "HE+3DA", 113 "PMAGB-FB", "HE+3DA", 114 }; 115 116 static int 117 pxg_match(struct device *parent, struct cfdata *match, void *aux) 118 { 119 struct tc_attach_args *ta; 120 int i; 121 122 ta = aux; 123 124 for (i = 0; i < sizeof(pxg_types) / sizeof(pxg_types[0]); i += 2) 125 if (strncmp(pxg_types[i], ta->ta_modname, TC_ROM_LLEN) == 0) 126 return (1); 127 128 return (0); 129 } 130 131 static void 132 pxg_attach(struct device *parent, struct device *self, void *aux) 133 { 134 struct stic_info *si; 135 struct tc_attach_args *ta; 136 struct pxg_softc *pxg; 137 int console, i; 138 139 pxg = (struct pxg_softc *)self; 140 ta = (struct tc_attach_args *)aux; 141 142 if (ta->ta_addr == stic_consinfo.si_slotbase) { 143 si = &stic_consinfo; 144 console = 1; 145 } else { 146 if (stic_consinfo.si_slotbase == NULL) 147 si = &stic_consinfo; 148 else { 149 si = malloc(sizeof(*si), M_DEVBUF, M_NOWAIT); 150 memset(si, 0, sizeof(*si)); 151 } 152 si->si_slotbase = ta->ta_addr; 153 pxg_init(si); 154 console = 0; 155 } 156 157 pxg->pxg_si = si; 158 tc_intr_establish(parent, ta->ta_cookie, IPL_TTY, pxg_intr, si); 159 160 for (i = 0; i < sizeof(pxg_types) / sizeof(pxg_types[0]); i += 2) 161 if (strncmp(pxg_types[i], ta->ta_modname, TC_ROM_LLEN) == 0) 162 break; 163 164 printf(": %s, %d plane, %dx%d stamp, %dkB SRAM\n", pxg_types[i + 1], 165 si->si_depth, si->si_stampw, si->si_stamph, si->si_buf_size >> 10); 166 167 stic_attach(self, si, console); 168 } 169 170 void 171 pxg_cnattach(tc_addr_t addr) 172 { 173 struct stic_info *si; 174 175 si = &stic_consinfo; 176 si->si_slotbase = addr; 177 pxg_init(si); 178 stic_cnattach(si); 179 } 180 181 static void 182 pxg_init(struct stic_info *si) 183 { 184 volatile u_int32_t *slot; 185 caddr_t kva; 186 paddr_t bpa; 187 188 kva = (caddr_t)TC_PHYS_TO_UNCACHED(si->si_slotbase); 189 bpa = STIC_KSEG_TO_PHYS((caddr_t)kva + PXG_SRAM_OFFSET); 190 slot = (volatile u_int32_t *)kva; 191 192 si->si_slotkva = (u_int32_t *)kva; 193 si->si_vdac = (u_int32_t *)(kva + PXG_VDAC_OFFSET); 194 si->si_vdac_reset = (u_int32_t *)(kva + PXG_VDAC_RESET_OFFSET); 195 si->si_stic = (volatile struct stic_regs *)(kva + PXG_STIC_OFFSET); 196 si->si_stamp = (u_int32_t *)(kva + PXG_STAMP_OFFSET); 197 si->si_buf = (u_int32_t *)TC_PHYS_TO_UNCACHED(bpa); 198 si->si_buf_phys = bpa; 199 si->si_buf_size = pxg_probe_sram(si); 200 si->si_disptype = WSDISPLAY_TYPE_PXG; 201 202 si->si_pbuf_get = pxg_pbuf_get; 203 si->si_pbuf_post = pxg_pbuf_post; 204 si->si_ioctl = pxg_ioctl; 205 206 /* Disable the co-processor. */ 207 slot[PXG_I860_RESET_OFFSET >> 2] = 0; 208 tc_syncbus(); 209 slot[PXG_HOST_INTR_OFFSET >> 2] = 0; 210 tc_syncbus(); 211 DELAY(40000); 212 213 /* XXX Check for a second PixelStamp. */ 214 if (((si->si_stic->sr_modcl & 0x600) >> 9) > 1) 215 si->si_depth = 24; 216 else 217 si->si_depth = pxg_probe_planes(si); 218 219 #ifdef notdef 220 /* Restart the co-processor and enable STIC interrupts */ 221 slot[PXG_I860_START_OFFSET >> 2] = 1; 222 tc_syncbus(); 223 DELAY(2000); 224 sr->sr_sticsr = STIC_INT_WE | STIC_INT_CLR; 225 tc_wmb(); 226 #endif 227 228 stic_init(si); 229 } 230 231 static int 232 pxg_probe_sram(struct stic_info *si) 233 { 234 volatile u_int32_t *a, *b; 235 236 a = si->si_slotkva + (PXG_SRAM_OFFSET >> 2); 237 b = a + (0x20000 >> 1); 238 *a = 4321; 239 *b = 1234; 240 tc_syncbus(); 241 return ((*a == *b) ? 0x20000 : 0x40000); 242 } 243 244 static int 245 pxg_probe_planes(struct stic_info *si) 246 { 247 volatile u_int32_t *vdac; 248 int id; 249 250 /* 251 * For the visible framebuffer (# 0), we can cheat and use the VDAC 252 * ID. 253 */ 254 vdac = si->si_vdac; 255 vdac[BT459_REG_ADDR_LOW] = (BT459_IREG_ID & 0xff) | 256 ((BT459_IREG_ID & 0xff) << 8) | ((BT459_IREG_ID & 0xff) << 16); 257 vdac[BT459_REG_ADDR_HIGH] = ((BT459_IREG_ID & 0xff00) >> 8) | 258 (BT459_IREG_ID & 0xff00) | ((BT459_IREG_ID & 0xff00) << 8); 259 tc_syncbus(); 260 id = vdac[BT459_REG_IREG_DATA] & 0x00ffffff; 261 262 /* 3 VDACs */ 263 if (id == 0x004a4a4a) 264 return (24); 265 266 /* 1 VDAC */ 267 if ((id & 0xff0000) == 0x4a0000 || (id & 0x00ff00) == 0x004a00 || 268 (id & 0x0000ff) == 0x00004a) 269 return (8); 270 271 /* XXX Assume 8 planes. */ 272 printf("pxg_probe_planes: invalid VDAC ID %x\n", id); 273 return (8); 274 } 275 276 static int 277 pxg_intr(void *cookie) 278 { 279 struct stic_info *si; 280 volatile struct stic_regs *sr; 281 volatile u_int32_t *hi; 282 u_int32_t state; 283 int it; 284 285 si = cookie; 286 sr = si->si_stic; 287 state = sr->sr_ipdvint; 288 hi = si->si_slotkva + (PXG_HOST_INTR_OFFSET / sizeof(u_int32_t)); 289 290 /* Clear the interrupt condition */ 291 it = hi[0] & 15; 292 hi[0] = 0; 293 tc_wmb(); 294 hi[2] = 0; 295 tc_wmb(); 296 297 /* 298 * Since we disable the co-processor, we won't get to see vblank 299 * interrupts (so in effect, this code is useless). 300 * 301 * Packet-done and error interrupts will only ever be seen by the 302 * co-processor (although ULTRIX seems to think that they're posted 303 * to us - more investigation required). 304 */ 305 if (it == 3) { 306 sr->sr_ipdvint = 307 STIC_INT_V_WE | (sr->sr_ipdvint & STIC_INT_V_EN); 308 tc_wmb(); 309 stic_flush(si); 310 } 311 312 return (1); 313 } 314 315 static u_int32_t * 316 pxg_pbuf_get(struct stic_info *si) 317 { 318 #ifdef notdef 319 volatile u_int32_t *poll; 320 321 /* Ask i860 which buffer to use */ 322 poll = si->si_slotkva; 323 poll += PXG_COPROC_INTR_OFFSET >> 2; 324 325 /* 326 * XXX These should be defined as constants. 0x30 is "pause 327 * coprocessor and interrupt." 328 */ 329 *poll = 0x30; 330 tc_wmb(); 331 332 for (i = 1000000; i; i--) { 333 DELAY(4); 334 switch(j = *poll) { 335 case 2: 336 si->si_pbuf_select = STIC_PACKET_SIZE; 337 break; 338 case 1: 339 si->si_pbuf_select = 0; 340 break; 341 default: 342 if (j == 0x30) 343 continue; 344 break; 345 } 346 break; 347 } 348 349 if (j != 1 || j != 2) { 350 /* STIC has lost the plot, punish it */ 351 stic_reset(si); 352 si->si_pbuf_select = 0; 353 } 354 #else 355 356 /* 357 * XXX We should be synchronizing with STIC_INT_P so that an ISR 358 * doesn't blow us up. 359 */ 360 si->si_pbuf_select ^= STIC_PACKET_SIZE; 361 #endif 362 return ((u_int32_t *)((caddr_t)si->si_buf + si->si_pbuf_select)); 363 } 364 365 static int 366 pxg_pbuf_post(struct stic_info *si, u_int32_t *buf) 367 { 368 volatile u_int32_t *poll; 369 u_long v; 370 int c; 371 372 /* Get address of poll register for this buffer. */ 373 v = ((u_long)buf - (u_long)si->si_buf) >> 9; 374 poll = (volatile u_int32_t *)((caddr_t)si->si_slotkva + v); 375 376 /* 377 * Read the poll register and make sure the stamp wants to accept 378 * our packet. This read will initiate the DMA. Don't wait for 379 * ever, just in case something's wrong. 380 */ 381 tc_syncbus(); 382 383 for (c = STAMP_RETRIES; c != 0; c--) { 384 if (*poll == STAMP_OK) { 385 #ifdef notdef 386 /* Tell the co-processor that we are done. */ 387 poll = si->si_slotkva + (PXG_HOST_INTR_OFFSET >> 2); 388 poll[0] = 0; 389 tc_wmb(); 390 poll[2] = 0; 391 tc_wmb(); 392 #endif 393 return (0); 394 } 395 396 DELAY(STAMP_DELAY); 397 } 398 399 /* STIC has lost the plot, punish it. */ 400 stic_reset(si); 401 return (-1); 402 } 403 404 static int 405 pxg_ioctl(struct stic_info *si, u_long cmd, caddr_t data, int flag, 406 struct proc *p) 407 { 408 int rv; 409 410 if (cmd == STICIO_START860 || cmd == STICIO_RESET860) { 411 if ((rv = suser(p->p_ucred, &p->p_acflag)) != 0) 412 return (rv); 413 if (cmd == STICIO_START860) 414 si->si_slotkva[PXG_I860_START_OFFSET >> 2] = 1; 415 else 416 si->si_slotkva[PXG_I860_RESET_OFFSET >> 2] = 0; 417 tc_syncbus(); 418 rv = 0; 419 } else 420 rv = ENOTTY; 421 422 return (rv); 423 } 424
Indexes created Wed Oct 15 03:09:54 GMT 2025