pxg.c revision 1.4.2.4
1 /* $NetBSD: pxg.c,v 1.4.2.4 2002/01/08 00:32:01 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Driver for DEC PixelStamp graphics accelerators with onboard SRAM and 41 * Intel i860 co-processor (PMAG-D, E and F). 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: pxg.c,v 1.4.2.4 2002/01/08 00:32:01 nathanw Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 #include <sys/callout.h> 52 #include <sys/proc.h> 53 54 #if defined(pmax) 55 #include <mips/cpuregs.h> 56 #elif defined(alpha) 57 #include <alpha/alpha_cpu.h> 58 #endif 59 60 #include <machine/autoconf.h> 61 #include <machine/cpu.h> 62 #include <machine/bus.h> 63 64 #include <dev/cons.h> 65 66 #include <dev/wscons/wsconsio.h> 67 #include <dev/wscons/wsdisplayvar.h> 68 69 #include <dev/ic/bt459reg.h> 70 71 #include <dev/tc/tcvar.h> 72 #include <dev/tc/sticreg.h> 73 #include <dev/tc/sticio.h> 74 #include <dev/tc/sticvar.h> 75 #include <dev/tc/pxgvar.h> 76 77 #define PXG_STIC_POLL_OFFSET 0x000000 /* STIC DMA poll space */ 78 #define PXG_STAMP_OFFSET 0x0c0000 /* pixelstamp space on STIC */ 79 #define PXG_STIC_OFFSET 0x180000 /* STIC registers */ 80 #define PXG_SRAM_OFFSET 0x200000 /* 128 or 256kB of SRAM */ 81 #define PXG_HOST_INTR_OFFSET 0x280000 /* i860 host interrupt */ 82 #define PXG_COPROC_INTR_OFFSET 0x2c0000 /* i860 coprocessor interrupt */ 83 #define PXG_VDAC_OFFSET 0x300000 /* VDAC registers (bt459) */ 84 #define PXG_VDAC_RESET_OFFSET 0x340000 /* VDAC reset register */ 85 #define PXG_ROM_OFFSET 0x380000 /* ROM code */ 86 #define PXG_I860_START_OFFSET 0x380000 /* i860 start register */ 87 #define PXG_I860_RESET_OFFSET 0x3c0000 /* i860 stop register */ 88 89 void pxg_attach(struct device *, struct device *, void *); 90 int pxg_intr(void *); 91 int pxg_match(struct device *, struct cfdata *, void *); 92 93 void pxg_init(struct stic_info *); 94 int pxg_ioctl(struct stic_info *, u_long, caddr_t, int, struct proc *); 95 u_int32_t *pxg_pbuf_get(struct stic_info *); 96 int pxg_pbuf_post(struct stic_info *, u_int32_t *); 97 int pxg_probe_planes(struct stic_info *); 98 int pxg_probe_sram(struct stic_info *); 99 100 void pxg_cnattach(tc_addr_t); 101 102 struct pxg_softc { 103 struct device pxg_dv; 104 struct stic_info *pxg_si; 105 }; 106 107 struct cfattach pxg_ca = { 108 sizeof(struct pxg_softc), pxg_match, pxg_attach 109 }; 110 111 static const char *pxg_types[] = { 112 "PMAG-DA ", 113 "PMAG-FA ", 114 "PMAG-FB ", 115 "PMAGB-FA", 116 "PMAGB-FB", 117 }; 118 119 int 120 pxg_match(struct device *parent, struct cfdata *match, void *aux) 121 { 122 struct tc_attach_args *ta; 123 int i; 124 125 ta = aux; 126 127 for (i = 0; i < sizeof(pxg_types) / sizeof(pxg_types[0]); i++) 128 if (strncmp(pxg_types[i], ta->ta_modname, TC_ROM_LLEN) == 0) 129 return (1); 130 131 return (0); 132 } 133 134 void 135 pxg_attach(struct device *parent, struct device *self, void *aux) 136 { 137 struct stic_info *si; 138 struct tc_attach_args *ta; 139 struct pxg_softc *pxg; 140 int console; 141 142 pxg = (struct pxg_softc *)self; 143 ta = (struct tc_attach_args *)aux; 144 145 if (ta->ta_addr == stic_consinfo.si_slotbase) { 146 si = &stic_consinfo; 147 console = 1; 148 } else { 149 if (stic_consinfo.si_slotbase == NULL) 150 si = &stic_consinfo; 151 else { 152 si = malloc(sizeof(*si), M_DEVBUF, M_NOWAIT); 153 memset(si, 0, sizeof(*si)); 154 } 155 si->si_slotbase = ta->ta_addr; 156 pxg_init(si); 157 console = 0; 158 } 159 160 pxg->pxg_si = si; 161 si->si_dv = self; 162 tc_intr_establish(parent, ta->ta_cookie, IPL_TTY, pxg_intr, si); 163 164 printf(": %d plane, %dx%d stamp, %dkB SRAM\n", si->si_depth, 165 si->si_stampw, si->si_stamph, (int)si->si_buf_size >> 10); 166 167 stic_attach(self, si, console); 168 169 #ifdef notyet 170 /* Load the co-processor "firmware". */ 171 for (i = 0; i < sizeof(pxg_fwsegs) / sizeof(pxg_fwsegs[0]); i++) 172 pxg_load_fwseg(si, &pxg_fwsegs[i]); 173 174 /* Start the i860. */ 175 si->si_slotbase[PXG_I860_START_OFFSET >> 2] = 1; 176 tc_wmb(); 177 tc_syncbus(); 178 DELAY(40000); 179 #endif 180 } 181 182 void 183 pxg_cnattach(tc_addr_t addr) 184 { 185 struct stic_info *si; 186 187 si = &stic_consinfo; 188 si->si_slotbase = addr; 189 pxg_init(si); 190 stic_cnattach(si); 191 } 192 193 void 194 pxg_init(struct stic_info *si) 195 { 196 volatile u_int32_t *slot; 197 caddr_t kva; 198 199 kva = (caddr_t)si->si_slotbase; 200 201 si->si_vdac = (u_int32_t *)(kva + PXG_VDAC_OFFSET); 202 si->si_vdac_reset = (u_int32_t *)(kva + PXG_VDAC_RESET_OFFSET); 203 si->si_stic = (volatile struct stic_regs *)(kva + PXG_STIC_OFFSET); 204 si->si_stamp = (u_int32_t *)(kva + PXG_STAMP_OFFSET); 205 si->si_buf = (u_int32_t *)(kva + PXG_SRAM_OFFSET); 206 si->si_buf_phys = STIC_KSEG_TO_PHYS(si->si_buf); 207 si->si_buf_size = pxg_probe_sram(si); 208 si->si_disptype = WSDISPLAY_TYPE_PXG; 209 si->si_sxc = (volatile struct stic_xcomm *)si->si_buf; 210 211 si->si_pbuf_get = pxg_pbuf_get; 212 si->si_pbuf_post = pxg_pbuf_post; 213 si->si_ioctl = pxg_ioctl; 214 215 /* Disable the co-processor. */ 216 slot = (volatile u_int32_t *)kva; 217 slot[PXG_I860_RESET_OFFSET >> 2] = 0; 218 tc_wmb(); 219 slot[PXG_HOST_INTR_OFFSET >> 2] = 0; 220 tc_wmb(); 221 tc_syncbus(); 222 DELAY(40000); 223 224 /* XXX Check for a second PixelStamp. */ 225 if (((si->si_stic->sr_modcl & 0x600) >> 9) > 1) 226 si->si_depth = 24; 227 else 228 si->si_depth = pxg_probe_planes(si); 229 230 stic_init(si); 231 } 232 233 int 234 pxg_probe_sram(struct stic_info *si) 235 { 236 volatile u_int32_t *a, *b; 237 238 a = (volatile u_int32_t *)si->si_slotbase + (PXG_SRAM_OFFSET >> 2); 239 b = a + (0x20000 >> 2); 240 *a = 4321; 241 *b = 1234; 242 tc_mb(); 243 return ((*a == *b) ? 0x20000 : 0x40000); 244 } 245 246 int 247 pxg_probe_planes(struct stic_info *si) 248 { 249 volatile u_int32_t *vdac; 250 int id; 251 252 /* 253 * For the visible framebuffer (# 0), we can cheat and use the VDAC 254 * ID. 255 */ 256 vdac = si->si_vdac; 257 vdac[BT459_REG_ADDR_LOW] = (BT459_IREG_ID & 0xff) | 258 ((BT459_IREG_ID & 0xff) << 8) | ((BT459_IREG_ID & 0xff) << 16); 259 vdac[BT459_REG_ADDR_HIGH] = ((BT459_IREG_ID & 0xff00) >> 8) | 260 (BT459_IREG_ID & 0xff00) | ((BT459_IREG_ID & 0xff00) << 8); 261 tc_mb(); 262 id = vdac[BT459_REG_IREG_DATA] & 0x00ffffff; 263 264 /* 3 VDACs */ 265 if (id == 0x004a4a4a) 266 return (24); 267 268 /* 1 VDAC */ 269 if ((id & 0xff0000) == 0x4a0000 || (id & 0x00ff00) == 0x004a00 || 270 (id & 0x0000ff) == 0x00004a) 271 return (8); 272 273 /* XXX Assume 8 planes. */ 274 printf("pxg_probe_planes: invalid VDAC ID %x\n", id); 275 return (8); 276 } 277 278 int 279 pxg_intr(void *cookie) 280 { 281 #ifdef notyet 282 struct stic_info *si; 283 volatile struct stic_regs *sr; 284 volatile u_int32_t *hi; 285 u_int32_t state; 286 int it; 287 288 si = cookie; 289 sr = si->si_stic; 290 state = sr->sr_ipdvint; 291 hi = (volatile u_int32_t *)si->si_slotbase + 292 (PXG_HOST_INTR_OFFSET / sizeof(u_int32_t)); 293 294 /* Clear the interrupt condition */ 295 it = hi[0] & 15; 296 hi[0] = 0; 297 tc_wmb(); 298 hi[2] = 0; 299 tc_wmb(); 300 301 switch (it) { 302 case 3: 303 sr->sr_ipdvint = STIC_INT_V_WE | STIC_INT_V_EN; 304 tc_wmb(); 305 stic_flush(si); 306 break; 307 } 308 #else 309 printf("pxg_intr: how did this happen?\n"); 310 #endif 311 return (1); 312 } 313 314 u_int32_t * 315 pxg_pbuf_get(struct stic_info *si) 316 { 317 u_long off; 318 319 si->si_pbuf_select ^= STIC_PACKET_SIZE; 320 off = si->si_pbuf_select + STIC_XCOMM_SIZE; 321 return ((u_int32_t *)((caddr_t)si->si_buf + off)); 322 } 323 324 int 325 pxg_pbuf_post(struct stic_info *si, u_int32_t *buf) 326 { 327 volatile u_int32_t *poll, junk; 328 volatile struct stic_regs *sr; 329 u_long v; 330 int c; 331 332 sr = si->si_stic; 333 334 /* Get address of poll register for this buffer. */ 335 v = ((u_long)buf - (u_long)si->si_buf) >> 9; 336 poll = (volatile u_int32_t *)((caddr_t)si->si_slotbase + v); 337 338 /* 339 * Read the poll register and make sure the stamp wants to accept 340 * our packet. This read will initiate the DMA. Don't wait for 341 * ever, just in case something's wrong. 342 */ 343 tc_mb(); 344 345 for (c = STAMP_RETRIES; c != 0; c--) { 346 if ((sr->sr_ipdvint & STIC_INT_P) != 0) { 347 sr->sr_ipdvint = STIC_INT_P_WE; 348 tc_wmb(); 349 junk = *poll; 350 return (0); 351 } 352 DELAY(STAMP_DELAY); 353 } 354 355 /* STIC has lost the plot, punish it. */ 356 stic_reset(si); 357 return (-1); 358 } 359 360 int 361 pxg_ioctl(struct stic_info *si, u_long cmd, caddr_t data, int flag, 362 struct proc *p) 363 { 364 struct stic_xinfo *sxi; 365 volatile u_int32_t *ptr; 366 int rv, s; 367 368 switch (cmd) { 369 case STICIO_START860: 370 case STICIO_RESET860: 371 if ((rv = suser(p->p_ucred, &p->p_acflag)) != 0) 372 return (rv); 373 if (si->si_dispmode != WSDISPLAYIO_MODE_MAPPED) 374 return (EBUSY); 375 ptr = (volatile u_int32_t *)si->si_slotbase; 376 break; 377 } 378 379 switch (cmd) { 380 case STICIO_START860: 381 s = spltty(); 382 ptr[PXG_I860_START_OFFSET >> 2] = 1; 383 tc_wmb(); 384 splx(s); 385 rv = 0; 386 break; 387 388 case STICIO_RESET860: 389 s = spltty(); 390 ptr[PXG_I860_RESET_OFFSET >> 2] = 0; 391 tc_wmb(); 392 splx(s); 393 rv = 0; 394 break; 395 396 case STICIO_GXINFO: 397 sxi = (struct stic_xinfo *)data; 398 sxi->sxi_unit = si->si_unit; 399 sxi->sxi_stampw = si->si_stampw; 400 sxi->sxi_stamph = si->si_stamph; 401 sxi->sxi_buf_size = si->si_buf_size; 402 sxi->sxi_buf_phys = 0; 403 sxi->sxi_buf_pktoff = STIC_XCOMM_SIZE; 404 sxi->sxi_buf_pktcnt = 2; 405 sxi->sxi_buf_imgoff = STIC_XCOMM_SIZE + STIC_PACKET_SIZE * 2; 406 rv = 0; 407 break; 408 409 default: 410 rv = ENOTTY; 411 break; 412 } 413 414 return (rv); 415 } 416 417 #ifdef notyet 418 void 419 pxg_load_fwseg(struct stic_info *si, struct pxg_fwseg *pfs) 420 { 421 const u_int32_t *src; 422 u_int32_t *dst; 423 u_int left, i; 424 425 dst = (u_int32_t *)((caddr_t)si->si_buf + pfs->pfs_addr); 426 src = pfs->pfs_data; 427 428 for (left = pfs->pfs_compsize; left != 0; left -= 4) { 429 if (src[0] == PXGFW_RLE_MAGIC) { 430 for (i = src[2]; i != 0; i--) 431 *dst++ = src[1]; 432 src += 3; 433 } else { 434 *dst++ = src[0]; 435 src++; 436 } 437 } 438 439 if (src == NULL) 440 memset(dst, 0, pfs->pfs_realsize); 441 } 442 #endif 443
Indexes created Tue Oct 14 11:09:46 GMT 2025