pxg.c revision 1.7
1 /* $NetBSD: pxg.c,v 1.7 2001/11/13 06:26:10 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Driver for DEC PixelStamp graphics accelerators with onboard SRAM and 41 * Intel i860 co-processor (PMAG-D, E and F). 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: pxg.c,v 1.7 2001/11/13 06:26:10 lukem Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/types.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/malloc.h> 52 #include <sys/callout.h> 53 #include <sys/proc.h> 54 55 #if defined(pmax) 56 #include <mips/cpuregs.h> 57 #elif defined(alpha) 58 #include <alpha/alpha_cpu.h> 59 #endif 60 61 #include <machine/autoconf.h> 62 #include <machine/cpu.h> 63 #include <machine/bus.h> 64 65 #include <dev/cons.h> 66 67 #include <dev/wscons/wsconsio.h> 68 #include <dev/wscons/wsdisplayvar.h> 69 70 #include <dev/ic/bt459reg.h> 71 72 #include <dev/tc/tcvar.h> 73 #include <dev/tc/sticreg.h> 74 #include <dev/tc/sticio.h> 75 #include <dev/tc/sticvar.h> 76 #include <dev/tc/pxgvar.h> 77 78 #define PXG_STIC_POLL_OFFSET 0x000000 /* STIC DMA poll space */ 79 #define PXG_STAMP_OFFSET 0x0c0000 /* pixelstamp space on STIC */ 80 #define PXG_STIC_OFFSET 0x180000 /* STIC registers */ 81 #define PXG_SRAM_OFFSET 0x200000 /* 128 or 256kB of SRAM */ 82 #define PXG_HOST_INTR_OFFSET 0x280000 /* i860 host interrupt */ 83 #define PXG_COPROC_INTR_OFFSET 0x2c0000 /* i860 coprocessor interrupt */ 84 #define PXG_VDAC_OFFSET 0x300000 /* VDAC registers (bt459) */ 85 #define PXG_VDAC_RESET_OFFSET 0x340000 /* VDAC reset register */ 86 #define PXG_ROM_OFFSET 0x380000 /* ROM code */ 87 #define PXG_I860_START_OFFSET 0x380000 /* i860 start register */ 88 #define PXG_I860_RESET_OFFSET 0x3c0000 /* i860 stop register */ 89 90 void pxg_attach(struct device *, struct device *, void *); 91 int pxg_intr(void *); 92 int pxg_match(struct device *, struct cfdata *, void *); 93 94 void pxg_init(struct stic_info *); 95 int pxg_ioctl(struct stic_info *, u_long, caddr_t, int, struct proc *); 96 u_int32_t *pxg_pbuf_get(struct stic_info *); 97 int pxg_pbuf_post(struct stic_info *, u_int32_t *); 98 int pxg_probe_planes(struct stic_info *); 99 int pxg_probe_sram(struct stic_info *); 100 101 void pxg_cnattach(tc_addr_t); 102 103 struct pxg_softc { 104 struct device pxg_dv; 105 struct stic_info *pxg_si; 106 }; 107 108 struct cfattach pxg_ca = { 109 sizeof(struct pxg_softc), pxg_match, pxg_attach 110 }; 111 112 static const char *pxg_types[] = { 113 "PMAG-DA ", 114 "PMAG-FA ", 115 "PMAG-FB ", 116 "PMAGB-FA", 117 "PMAGB-FB", 118 }; 119 120 int 121 pxg_match(struct device *parent, struct cfdata *match, void *aux) 122 { 123 struct tc_attach_args *ta; 124 int i; 125 126 ta = aux; 127 128 for (i = 0; i < sizeof(pxg_types) / sizeof(pxg_types[0]); i++) 129 if (strncmp(pxg_types[i], ta->ta_modname, TC_ROM_LLEN) == 0) 130 return (1); 131 132 return (0); 133 } 134 135 void 136 pxg_attach(struct device *parent, struct device *self, void *aux) 137 { 138 struct stic_info *si; 139 struct tc_attach_args *ta; 140 struct pxg_softc *pxg; 141 int console; 142 143 pxg = (struct pxg_softc *)self; 144 ta = (struct tc_attach_args *)aux; 145 146 if (ta->ta_addr == stic_consinfo.si_slotbase) { 147 si = &stic_consinfo; 148 console = 1; 149 } else { 150 if (stic_consinfo.si_slotbase == NULL) 151 si = &stic_consinfo; 152 else { 153 si = malloc(sizeof(*si), M_DEVBUF, M_NOWAIT); 154 memset(si, 0, sizeof(*si)); 155 } 156 si->si_slotbase = ta->ta_addr; 157 pxg_init(si); 158 console = 0; 159 } 160 161 pxg->pxg_si = si; 162 si->si_dv = self; 163 tc_intr_establish(parent, ta->ta_cookie, IPL_TTY, pxg_intr, si); 164 165 printf(": %d plane, %dx%d stamp, %dkB SRAM\n", si->si_depth, 166 si->si_stampw, si->si_stamph, (int)si->si_buf_size >> 10); 167 168 stic_attach(self, si, console); 169 170 #ifdef notyet 171 /* Load the co-processor "firmware". */ 172 for (i = 0; i < sizeof(pxg_fwsegs) / sizeof(pxg_fwsegs[0]); i++) 173 pxg_load_fwseg(si, &pxg_fwsegs[i]); 174 175 /* Start the i860. */ 176 si->si_slotbase[PXG_I860_START_OFFSET >> 2] = 1; 177 tc_wmb(); 178 tc_syncbus(); 179 DELAY(40000); 180 #endif 181 } 182 183 void 184 pxg_cnattach(tc_addr_t addr) 185 { 186 struct stic_info *si; 187 188 si = &stic_consinfo; 189 si->si_slotbase = addr; 190 pxg_init(si); 191 stic_cnattach(si); 192 } 193 194 void 195 pxg_init(struct stic_info *si) 196 { 197 volatile u_int32_t *slot; 198 caddr_t kva; 199 200 kva = (caddr_t)si->si_slotbase; 201 202 si->si_vdac = (u_int32_t *)(kva + PXG_VDAC_OFFSET); 203 si->si_vdac_reset = (u_int32_t *)(kva + PXG_VDAC_RESET_OFFSET); 204 si->si_stic = (volatile struct stic_regs *)(kva + PXG_STIC_OFFSET); 205 si->si_stamp = (u_int32_t *)(kva + PXG_STAMP_OFFSET); 206 si->si_buf = (u_int32_t *)(kva + PXG_SRAM_OFFSET); 207 si->si_buf_phys = STIC_KSEG_TO_PHYS(si->si_buf); 208 si->si_buf_size = pxg_probe_sram(si); 209 si->si_disptype = WSDISPLAY_TYPE_PXG; 210 si->si_sxc = (volatile struct stic_xcomm *)si->si_buf; 211 212 si->si_pbuf_get = pxg_pbuf_get; 213 si->si_pbuf_post = pxg_pbuf_post; 214 si->si_ioctl = pxg_ioctl; 215 216 /* Disable the co-processor. */ 217 slot = (volatile u_int32_t *)kva; 218 slot[PXG_I860_RESET_OFFSET >> 2] = 0; 219 tc_wmb(); 220 slot[PXG_HOST_INTR_OFFSET >> 2] = 0; 221 tc_wmb(); 222 tc_syncbus(); 223 DELAY(40000); 224 225 /* XXX Check for a second PixelStamp. */ 226 if (((si->si_stic->sr_modcl & 0x600) >> 9) > 1) 227 si->si_depth = 24; 228 else 229 si->si_depth = pxg_probe_planes(si); 230 231 stic_init(si); 232 } 233 234 int 235 pxg_probe_sram(struct stic_info *si) 236 { 237 volatile u_int32_t *a, *b; 238 239 a = (volatile u_int32_t *)si->si_slotbase + (PXG_SRAM_OFFSET >> 2); 240 b = a + (0x20000 >> 2); 241 *a = 4321; 242 *b = 1234; 243 tc_mb(); 244 return ((*a == *b) ? 0x20000 : 0x40000); 245 } 246 247 int 248 pxg_probe_planes(struct stic_info *si) 249 { 250 volatile u_int32_t *vdac; 251 int id; 252 253 /* 254 * For the visible framebuffer (# 0), we can cheat and use the VDAC 255 * ID. 256 */ 257 vdac = si->si_vdac; 258 vdac[BT459_REG_ADDR_LOW] = (BT459_IREG_ID & 0xff) | 259 ((BT459_IREG_ID & 0xff) << 8) | ((BT459_IREG_ID & 0xff) << 16); 260 vdac[BT459_REG_ADDR_HIGH] = ((BT459_IREG_ID & 0xff00) >> 8) | 261 (BT459_IREG_ID & 0xff00) | ((BT459_IREG_ID & 0xff00) << 8); 262 tc_mb(); 263 id = vdac[BT459_REG_IREG_DATA] & 0x00ffffff; 264 265 /* 3 VDACs */ 266 if (id == 0x004a4a4a) 267 return (24); 268 269 /* 1 VDAC */ 270 if ((id & 0xff0000) == 0x4a0000 || (id & 0x00ff00) == 0x004a00 || 271 (id & 0x0000ff) == 0x00004a) 272 return (8); 273 274 /* XXX Assume 8 planes. */ 275 printf("pxg_probe_planes: invalid VDAC ID %x\n", id); 276 return (8); 277 } 278 279 int 280 pxg_intr(void *cookie) 281 { 282 #ifdef notyet 283 struct stic_info *si; 284 volatile struct stic_regs *sr; 285 volatile u_int32_t *hi; 286 u_int32_t state; 287 int it; 288 289 si = cookie; 290 sr = si->si_stic; 291 state = sr->sr_ipdvint; 292 hi = (volatile u_int32_t *)si->si_slotbase + 293 (PXG_HOST_INTR_OFFSET / sizeof(u_int32_t)); 294 295 /* Clear the interrupt condition */ 296 it = hi[0] & 15; 297 hi[0] = 0; 298 tc_wmb(); 299 hi[2] = 0; 300 tc_wmb(); 301 302 switch (it) { 303 case 3: 304 sr->sr_ipdvint = STIC_INT_V_WE | STIC_INT_V_EN; 305 tc_wmb(); 306 stic_flush(si); 307 break; 308 } 309 #else 310 printf("pxg_intr: how did this happen?\n"); 311 #endif 312 return (1); 313 } 314 315 u_int32_t * 316 pxg_pbuf_get(struct stic_info *si) 317 { 318 u_long off; 319 320 si->si_pbuf_select ^= STIC_PACKET_SIZE; 321 off = si->si_pbuf_select + STIC_XCOMM_SIZE; 322 return ((u_int32_t *)((caddr_t)si->si_buf + off)); 323 } 324 325 int 326 pxg_pbuf_post(struct stic_info *si, u_int32_t *buf) 327 { 328 volatile u_int32_t *poll, junk; 329 volatile struct stic_regs *sr; 330 u_long v; 331 int c; 332 333 sr = si->si_stic; 334 335 /* Get address of poll register for this buffer. */ 336 v = ((u_long)buf - (u_long)si->si_buf) >> 9; 337 poll = (volatile u_int32_t *)((caddr_t)si->si_slotbase + v); 338 339 /* 340 * Read the poll register and make sure the stamp wants to accept 341 * our packet. This read will initiate the DMA. Don't wait for 342 * ever, just in case something's wrong. 343 */ 344 tc_mb(); 345 346 for (c = STAMP_RETRIES; c != 0; c--) { 347 if ((sr->sr_ipdvint & STIC_INT_P) != 0) { 348 sr->sr_ipdvint = STIC_INT_P_WE; 349 tc_wmb(); 350 junk = *poll; 351 return (0); 352 } 353 DELAY(STAMP_DELAY); 354 } 355 356 /* STIC has lost the plot, punish it. */ 357 stic_reset(si); 358 return (-1); 359 } 360 361 int 362 pxg_ioctl(struct stic_info *si, u_long cmd, caddr_t data, int flag, 363 struct proc *p) 364 { 365 struct stic_xinfo *sxi; 366 volatile u_int32_t *ptr; 367 int rv, s; 368 369 switch (cmd) { 370 case STICIO_START860: 371 case STICIO_RESET860: 372 if ((rv = suser(p->p_ucred, &p->p_acflag)) != 0) 373 return (rv); 374 if (si->si_dispmode != WSDISPLAYIO_MODE_MAPPED) 375 return (EBUSY); 376 ptr = (volatile u_int32_t *)si->si_slotbase; 377 break; 378 } 379 380 switch (cmd) { 381 case STICIO_START860: 382 s = spltty(); 383 ptr[PXG_I860_START_OFFSET >> 2] = 1; 384 tc_wmb(); 385 splx(s); 386 rv = 0; 387 break; 388 389 case STICIO_RESET860: 390 s = spltty(); 391 ptr[PXG_I860_RESET_OFFSET >> 2] = 0; 392 tc_wmb(); 393 splx(s); 394 rv = 0; 395 break; 396 397 case STICIO_GXINFO: 398 sxi = (struct stic_xinfo *)data; 399 sxi->sxi_unit = si->si_unit; 400 sxi->sxi_stampw = si->si_stampw; 401 sxi->sxi_stamph = si->si_stamph; 402 sxi->sxi_buf_size = si->si_buf_size; 403 sxi->sxi_buf_phys = 0; 404 sxi->sxi_buf_pktoff = STIC_XCOMM_SIZE; 405 sxi->sxi_buf_pktcnt = 2; 406 sxi->sxi_buf_imgoff = STIC_XCOMM_SIZE + STIC_PACKET_SIZE * 2; 407 rv = 0; 408 break; 409 410 default: 411 rv = ENOTTY; 412 break; 413 } 414 415 return (rv); 416 } 417 418 #ifdef notyet 419 void 420 pxg_load_fwseg(struct stic_info *si, struct pxg_fwseg *pfs) 421 { 422 const u_int32_t *src; 423 u_int32_t *dst; 424 u_int left, i; 425 426 dst = (u_int32_t *)((caddr_t)si->si_buf + pfs->pfs_addr); 427 src = pfs->pfs_data; 428 429 for (left = pfs->pfs_compsize; left != 0; left -= 4) { 430 if (src[0] == PXGFW_RLE_MAGIC) { 431 for (i = src[2]; i != 0; i--) 432 *dst++ = src[1]; 433 src += 3; 434 } else { 435 *dst++ = src[0]; 436 src++; 437 } 438 } 439 440 if (src == NULL) 441 memset(dst, 0, pfs->pfs_realsize); 442 } 443 #endif 444
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