1 /* $NetBSD: if_athn_usb.h,v 1.6 2019/09/14 12:36:35 maxv Exp $ */ 2 /* $OpenBSD: if_athn_usb.h,v 1.3 2012/11/10 14:35:06 mikeb Exp $ */ 3 4 /*- 5 * Copyright (c) 2011 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _IF_ATHN_USB_H_ 21 #define _IF_ATHN_USB_H_ 22 23 /* Maximum number of STAs firmware can handle. */ 24 #define AR_USB_MAX_STA 8 25 26 #define AR_USB_DEFAULT_NF (-95) 27 28 /* USB requests. */ 29 #define AR_FW_DOWNLOAD 0x30 30 #define AR_FW_DOWNLOAD_COMP 0x31 31 32 /* USB endpoints addresses. */ 33 #define AR_PIPE_TX_DATA (UE_DIR_OUT | 1) 34 #define AR_PIPE_RX_DATA (UE_DIR_IN | 2) 35 #define AR_PIPE_RX_INTR (UE_DIR_IN | 3) 36 #define AR_PIPE_TX_INTR (UE_DIR_OUT | 4) 37 38 /* Wireless module interface commands. */ 39 #define AR_WMI_CMD_ECHO 0x001 40 #define AR_WMI_CMD_ACCESS_MEMORY 0x002 41 #define AR_WMI_CMD_DISABLE_INTR 0x003 42 #define AR_WMI_CMD_ENABLE_INTR 0x004 43 #define AR_WMI_CMD_RX_LINK 0x005 44 #define AR_WMI_CMD_ATH_INIT 0x006 45 #define AR_WMI_CMD_ABORT_TXQ 0x007 46 #define AR_WMI_CMD_STOP_TX_DMA 0x008 47 #define AR_WMI_CMD_STOP_DMA_RECV 0x009 48 #define AR_WMI_CMD_ABORT_TX_DMA 0x00a 49 #define AR_WMI_CMD_DRAIN_TXQ 0x00b 50 #define AR_WMI_CMD_DRAIN_TXQ_ALL 0x00c 51 #define AR_WMI_CMD_START_RECV 0x00d 52 #define AR_WMI_CMD_STOP_RECV 0x00e 53 #define AR_WMI_CMD_FLUSH_RECV 0x00f 54 #define AR_WMI_CMD_SET_MODE 0x010 55 #define AR_WMI_CMD_RESET 0x011 56 #define AR_WMI_CMD_NODE_CREATE 0x012 57 #define AR_WMI_CMD_NODE_REMOVE 0x013 58 #define AR_WMI_CMD_VAP_REMOVE 0x014 59 #define AR_WMI_CMD_VAP_CREATE 0x015 60 #define AR_WMI_CMD_BEACON_UPDATE 0x016 61 #define AR_WMI_CMD_REG_READ 0x017 62 #define AR_WMI_CMD_REG_WRITE 0x018 63 #define AR_WMI_CMD_RC_STATE_CHANGE 0x019 64 #define AR_WMI_CMD_RC_RATE_UPDATE 0x01a 65 #define AR_WMI_CMD_DEBUG_INFO 0x01b 66 #define AR_WMI_CMD_HOST_ATTACH 0x01c 67 #define AR_WMI_CMD_TARGET_IC_UPDATE 0x01d 68 #define AR_WMI_CMD_TGT_STATS 0x01e 69 #define AR_WMI_CMD_TX_AGGR_ENABLE 0x01f 70 #define AR_WMI_CMD_TGT_DETACH 0x020 71 #define AR_WMI_CMD_TGT_TXQ_ENABLE 0x021 72 #define AR_WMI_CMD_AGGR_LIMIT 0x026 73 /* Wireless module interface events. */ 74 /* 75 * XXX: the 3.7.4 Linux kernel differs with this. This matches the 76 * 2.6.36 kernel. 77 */ 78 #if 1 /* Linux 2.6.26 */ 79 #define AR_WMI_EVT_TGT_RDY 0x001 80 #define AR_WMI_EVT_SWBA 0x002 81 #define AR_WMI_EVT_FATAL 0x003 82 #define AR_WMI_EVT_TXTO 0x004 83 #define AR_WMI_EVT_BMISS 0x005 84 #define AR_WMI_EVT_WLAN_TXCOMP 0x006 85 #define AR_WMI_EVT_DELBA 0x007 86 #define AR_WMI_EVT_TXRATE 0x008 87 #else /* Linux 3.7.4 */ 88 #define AR_WMI_EVT_TGT_RDY 0x001 89 #define AR_WMI_EVT_SWBA 0x002 90 #define AR_WMI_EVT_FATAL 0x003 91 #define AR_WMI_EVT_TXTO 0x004 92 #define AR_WMI_EVT_BMISS 0x005 93 #define AR_WMI_EVT_DELBA 0x006 94 #define AR_WMI_EVT_TXSTATUS 0x007 95 #endif 96 97 /* Structure for service AR_SVC_WMI_CONTROL. */ 98 struct ar_wmi_cmd_hdr { 99 uint16_t cmd_id; 100 #define AR_WMI_EVT_FLAG 0x1000 101 102 uint16_t seq_no; 103 } __packed; 104 105 /* Values for AR_WMI_CMD_SET_MODE. */ 106 #define AR_HTC_MODE_AUTO 0 107 #define AR_HTC_MODE_11A 1 108 #define AR_HTC_MODE_11B 2 109 #define AR_HTC_MODE_11G 3 110 #define AR_HTC_MODE_FH 4 111 #define AR_HTC_MODE_TURBO_A 5 112 #define AR_HTC_MODE_TURBO_G 6 113 #define AR_HTC_MODE_11NA 7 114 #define AR_HTC_MODE_11NG 8 115 116 #define AR_MAX_WRITE_COUNT 32 117 /* Structure for command AR_WMI_CMD_REG_WRITE. */ 118 struct ar_wmi_cmd_reg_write { 119 uint32_t addr; 120 uint32_t val; 121 } __packed; 122 123 /* Structure for command AR_WMI_CMD_NODE_{CREATE,REMOVE}. */ 124 struct ar_htc_target_sta { 125 uint16_t associd; 126 uint16_t txpower; 127 uint32_t pariwisekey; 128 uint8_t macaddr[IEEE80211_ADDR_LEN]; 129 uint8_t bssid[IEEE80211_ADDR_LEN]; 130 uint8_t sta_index; 131 uint8_t vif_index; 132 uint8_t vif_sta; 133 uint16_t flags; 134 #define AR_HTC_STA_AUTH 0x0001 135 #define AR_HTC_STA_QOS 0x0002 136 #define AR_HTC_STA_ERP 0x0004 137 #define AR_HTC_STA_HT 0x0008 138 139 uint16_t htcap; 140 uint8_t valid; 141 uint16_t capinfo; 142 uint32_t reserved[2]; 143 uint16_t txseqmgmt; 144 uint8_t is_vif_sta; 145 uint16_t maxampdu; 146 uint16_t iv16; 147 uint32_t iv32; 148 } __packed; 149 150 /* Structures for command AR_WMI_CMD_RC_RATE_UPDATE. */ 151 #define AR_HTC_RATE_MAX 30 152 struct ar_htc_rateset { 153 uint8_t rs_nrates; 154 uint8_t rs_rates[AR_HTC_RATE_MAX]; 155 } __packed; 156 157 struct ar_htc_target_rate { 158 uint8_t sta_index; 159 uint8_t isnew; 160 uint32_t capflags; 161 #define AR_RC_DS_FLAG 0x00000001 162 #define AR_RC_TS_FLAG 0x00000002 163 #define AR_RC_40_FLAG 0x00000004 164 #define AR_RC_SGI_FLAG 0x00000008 165 #define AR_RC_HT_FLAG 0x00000010 166 167 struct ar_htc_rateset lg_rates; 168 struct ar_htc_rateset ht_rates; 169 } __packed; 170 171 /* Structure for command AR_WMI_CMD_TX_AGGR_ENABLE. */ 172 struct ar_htc_target_aggr { 173 uint8_t sta_index; 174 uint8_t tidno; 175 uint8_t aggr_enable; 176 uint8_t padding; 177 } __packed; 178 179 /* Structure for command AR_WMI_CMD_VAP_CREATE. */ 180 struct ar_htc_target_vif { 181 uint8_t index; 182 uint8_t des_bssid[IEEE80211_ADDR_LEN]; 183 uint32_t opmode; 184 #define AR_HTC_M_IBSS 0 185 #define AR_HTC_M_STA 1 186 #define AR_HTC_M_WDS 2 187 #define AR_HTC_M_AHDEMO 3 188 #define AR_HTC_M_HOSTAP 6 189 #define AR_HTC_M_MONITOR 8 190 191 uint8_t myaddr[IEEE80211_ADDR_LEN]; 192 uint8_t bssid[IEEE80211_ADDR_LEN]; 193 uint32_t flags; 194 uint32_t flags_ext; 195 uint16_t ps_sta; 196 uint16_t rtsthreshold; 197 uint8_t ath_cap; 198 int8_t mcast_rate; 199 } __packed; 200 201 /* Structure for command AM_WMI_CMD_TARGET_IC_UPDATE. */ 202 struct ar_htc_cap_target { 203 uint32_t flags; 204 uint32_t flags_ext; 205 uint32_t ampdu_limit; 206 uint8_t ampdu_subframes; 207 uint8_t ht_txchainmask; 208 uint8_t lg_txchainmask; 209 uint8_t rtscts_ratecode; 210 uint8_t protmode; 211 } __packed; 212 213 /* Structure for event AR_WMI_EVT_TXRATE. */ 214 struct ar_wmi_evt_txrate { 215 uint32_t txrate; 216 uint8_t rssi_thresh; 217 uint8_t per; 218 } __packed; 219 220 /* HTC header. */ 221 struct ar_htc_frame_hdr { 222 uint8_t endpoint_id; 223 uint8_t flags; 224 #define AR_HTC_FLAG_TRAILER 0x02 225 226 uint16_t payload_len; 227 uint8_t control[4]; 228 } __packed; 229 230 /* Structure for HTC enpoint id 0. */ 231 struct ar_htc_msg_hdr { 232 uint16_t msg_id; 233 #define AR_HTC_MSG_READY 0x0001 234 #define AR_HTC_MSG_CONN_SVC 0x0002 235 #define AR_HTC_MSG_CONN_SVC_RSP 0x0003 236 #define AR_HTC_MSG_SETUP_COMPLETE 0x0004 237 #define AR_HTC_MSG_CONF_PIPE 0x0005 238 #define AR_HTC_MSG_CONF_PIPE_RSP 0x0006 239 } __packed; 240 241 /* Structure for services AR_SVC_WMI_DATA_{VO,VI,BE,BK}. */ 242 struct ar_tx_frame { 243 uint8_t data_type; 244 #define AR_HTC_AMPDU 1 245 #define AR_HTC_NORMAL 2 246 247 uint8_t node_idx; 248 uint8_t vif_idx; 249 uint8_t tid; 250 uint32_t flags; 251 #define AR_HTC_TX_CTSONLY 0x00000001 252 #define AR_HTC_TX_RTSCTS 0x00000002 253 #define AR_HTC_TX_USE_MIN_RATE 0x00000100 254 255 uint8_t key_type; 256 uint8_t key_idx; 257 uint8_t reserved[26]; 258 } __packed; 259 260 /* Structure for service AR_SVC_WMI_MGMT. */ 261 struct ar_tx_mgmt { 262 uint8_t node_idx; 263 uint8_t vif_idx; 264 uint8_t tid; 265 uint8_t flags; 266 uint8_t key_type; 267 uint8_t key_idx; 268 uint16_t reserved; 269 } __packed; 270 271 /* Structure for service AR_SVC_WMI_BEACON. */ 272 struct ar_tx_bcn { 273 uint8_t len_changed; 274 uint8_t vif_idx; 275 uint16_t rev; 276 } __packed; 277 278 /* Structure for message AR_HTC_MSG_READY. */ 279 struct ar_htc_msg_ready { 280 uint16_t credits; 281 uint16_t credits_size; 282 uint8_t max_endpoints; 283 uint8_t reserved; 284 } __packed; 285 286 /* Structure for message AR_HTC_MSG_CONF_PIPE. */ 287 struct ar_htc_msg_config_pipe { 288 uint8_t pipe_id; 289 uint8_t credits; 290 } __packed; 291 292 /* Structure for message AR_HTC_MSG_CONN_SVC. */ 293 struct ar_htc_msg_conn_svc { 294 uint16_t svc_id; 295 uint16_t conn_flags; 296 uint8_t dl_pipeid; 297 uint8_t ul_pipeid; 298 uint8_t svc_meta_len; 299 uint8_t reserved; 300 } __packed; 301 302 /* Structure for message AR_HTC_MSG_CONN_SVC_RSP. */ 303 struct ar_htc_msg_conn_svc_rsp { 304 uint16_t svc_id; 305 uint8_t status; 306 #define AR_HTC_SVC_SUCCESS 0 307 #define AR_HTC_SVC_NOT_FOUND 1 308 #define AR_HTC_SVC_FAILED 2 309 #define AR_HTC_SVC_NO_RESOURCES 3 310 #define AR_HTC_SVC_NO_MORE_EP 4 311 312 uint8_t endpoint_id; 313 uint16_t max_msg_len; 314 uint8_t svc_meta_len; 315 uint8_t reserved; 316 } __packed; 317 318 #define AR_SVC(grp, idx) ((grp) << 8 | (idx)) 319 #define AR_SVC_IDX(svc) ((svc) & 0xff) 320 /* Service groups. */ 321 #define AR_SVC_GRP_RSVD 0 322 #define AR_SVC_GRP_WMI 1 323 /* Service identifiers for WMI group. */ 324 #define AR_SVC_WMI_CONTROL AR_SVC(AR_SVC_GRP_WMI, 0) 325 #define AR_SVC_WMI_BEACON AR_SVC(AR_SVC_GRP_WMI, 1) 326 #define AR_SVC_WMI_CAB AR_SVC(AR_SVC_GRP_WMI, 2) 327 #define AR_SVC_WMI_UAPSD AR_SVC(AR_SVC_GRP_WMI, 3) 328 #define AR_SVC_WMI_MGMT AR_SVC(AR_SVC_GRP_WMI, 4) 329 #define AR_SVC_WMI_DATA_VO AR_SVC(AR_SVC_GRP_WMI, 5) 330 #define AR_SVC_WMI_DATA_VI AR_SVC(AR_SVC_GRP_WMI, 6) 331 #define AR_SVC_WMI_DATA_BE AR_SVC(AR_SVC_GRP_WMI, 7) 332 #define AR_SVC_WMI_DATA_BK AR_SVC(AR_SVC_GRP_WMI, 8) 333 334 struct ar_stream_hdr { 335 uint16_t len; 336 uint16_t tag; 337 #define AR_USB_RX_STREAM_TAG 0x4e00 338 #define AR_USB_TX_STREAM_TAG 0x697e 339 } __packed __attribute__((aligned(4))); 340 341 #define AR_MAX_CHAINS 3 342 343 /* Rx descriptor. */ 344 struct ar_rx_status { 345 uint64_t rs_tstamp; 346 uint16_t rs_datalen; 347 uint8_t rs_status; 348 uint8_t rs_phyerr; 349 int8_t rs_rssi; 350 int8_t rs_rssi_ctl[AR_MAX_CHAINS]; 351 int8_t rs_rssi_ext[AR_MAX_CHAINS]; 352 uint8_t rs_keyix; 353 uint8_t rs_rate; 354 uint8_t rs_antenna; 355 uint8_t rs_more; 356 uint8_t rs_isaggr; 357 uint8_t rs_moreaggr; 358 uint8_t rs_num_delims; 359 uint8_t rs_flags; 360 #define AR_RXS_FLAG_GI 0x04 361 #define AR_RXS_FLAG_2040 0x08 362 363 uint8_t rs_dummy; 364 uint32_t rs_evm[AR_MAX_CHAINS]; 365 } __packed __attribute__((aligned(4))); 366 367 368 /* 369 * Driver definitions. 370 */ 371 #define ATHN_USB_RX_LIST_COUNT 1 372 #define ATHN_USB_TX_LIST_COUNT (8 + 1) /* NB: +1 for beacons. */ 373 374 #define ATHN_USB_HOST_CMD_RING_COUNT 32 375 376 #define ATHN_USB_RXBUFSZ (8 * 1024) /* XXX Linux 16K */ 377 #define ATHN_USB_TXBUFSZ \ 378 ((sizeof(struct ar_stream_hdr) + \ 379 sizeof(struct ar_htc_frame_hdr) + \ 380 sizeof(struct ar_tx_frame) + \ 381 IEEE80211_MAX_LEN + 3) & ~3) 382 #define ATHN_USB_TXCMDSZ 512 383 384 #define ATHN_USB_TX_TIMEOUT 5000 /* ms */ 385 #define ATHN_USB_CMD_TIMEOUT 1000 /* ms */ 386 387 struct athn_usb_softc; 388 389 struct athn_usb_rx_stream { 390 struct mbuf *m; 391 int moff; 392 int left; 393 }; 394 395 struct athn_usb_rx_data { 396 struct athn_usb_softc *sc; 397 struct usbd_xfer *xfer; 398 uint8_t *buf; 399 }; 400 401 struct athn_usb_tx_data { 402 struct athn_usb_softc *sc; 403 struct usbd_xfer *xfer; 404 uint8_t *buf; 405 TAILQ_ENTRY(athn_usb_tx_data) next; 406 }; 407 408 struct athn_usb_host_cmd { 409 void (*cb)(struct athn_usb_softc *, void *); 410 uint8_t data[256]; 411 }; 412 413 struct athn_usb_cmd_newstate { 414 enum ieee80211_state state; 415 int arg; 416 }; 417 418 struct athn_usb_cmd_key { 419 struct ieee80211_node *ni; 420 struct ieee80211_key *key; 421 }; 422 423 struct athn_usb_aggr_cmd { 424 uint8_t sta_index; 425 uint8_t tid; 426 }; 427 428 struct athn_usb_host_cmd_ring { 429 struct athn_usb_host_cmd cmd[ATHN_USB_HOST_CMD_RING_COUNT]; 430 int cur; 431 int next; 432 int queued; 433 }; 434 435 struct athn_usb_node { 436 struct athn_node aun_an; 437 /* our stuff */ 438 }; 439 440 struct athn_usb_softc { 441 struct athn_softc usc_sc; 442 #define usc_dev usc_sc.sc_dev 443 444 enum { 445 ATHN_INIT_NONE, 446 ATHN_INIT_INITED 447 } usc_init_state; 448 int usc_athn_attached; 449 450 kmutex_t usc_lock; 451 kcondvar_t usc_wmi_cv; 452 kcondvar_t usc_htc_cv; 453 454 kmutex_t usc_msg_mtx; 455 kcondvar_t usc_msg_cv; 456 kmutex_t usc_cmd_mtx; 457 kcondvar_t usc_cmd_cv; 458 459 kcondvar_t usc_task_cv; 460 kmutex_t usc_task_mtx; 461 kmutex_t usc_tx_mtx; 462 463 /* USB specific goo. */ 464 struct usbd_device *usc_udev; 465 struct usbd_interface *usc_iface; 466 struct usb_task usc_task; 467 int usc_dying; 468 469 u_int usc_flags; 470 #define ATHN_USB_FLAG_NONE 0x00 471 #define ATHN_USB_FLAG_AR7010 0x01 472 473 struct athn_usb_rx_stream usc_rx_stream; 474 475 struct usbd_pipe *usc_tx_data_pipe; 476 struct usbd_pipe *usc_rx_data_pipe; 477 struct usbd_pipe *usc_rx_intr_pipe; 478 struct usbd_pipe *usc_tx_intr_pipe; 479 uint8_t *usc_ibuf; 480 size_t usc_ibufsize; 481 482 struct ar_wmi_cmd_reg_write usc_wbuf[AR_MAX_WRITE_COUNT]; 483 int usc_wcount; 484 485 bool usc_wmiactive; 486 bool usc_htcactive; 487 uint16_t usc_wmi_seq_no; 488 uint16_t usc_wait_cmd_id; 489 uint16_t usc_wait_msg_id; 490 void *usc_obuf; 491 struct ar_htc_msg_conn_svc_rsp *usc_msg_conn_svc_rsp; 492 493 struct athn_usb_host_cmd_ring usc_cmdq; 494 struct athn_usb_rx_data usc_rx_data[ATHN_USB_RX_LIST_COUNT]; 495 struct athn_usb_tx_data usc_tx_data[ATHN_USB_TX_LIST_COUNT]; 496 TAILQ_HEAD(, athn_usb_tx_data) usc_tx_free_list; 497 struct athn_usb_tx_data usc_tx_cmd; 498 struct athn_usb_tx_data usc_tx_msg; 499 struct athn_usb_tx_data *usc_tx_bcn; 500 501 uint8_t usc_ep_ctrl; 502 uint8_t usc_ep_bcn; 503 uint8_t usc_ep_cab; 504 uint8_t usc_ep_uapsd; 505 uint8_t usc_ep_mgmt; 506 uint8_t usc_ep_data[WME_NUM_AC]; 507 void (*usc_node_cleanup)(struct ieee80211_node *); 508 }; 509 510 #endif /* _IF_ATHN_USB_H_ */ 511
Indexes created Tue Sep 23 07:09:52 GMT 2025