1 /* $NetBSD: uhcireg.h,v 1.22 2016/04/23 10:15:32 skrll Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/uhcireg.h,v 1.12 1999/11/17 22:33:42 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_USB_UHCIREG_H_ 35 #define _DEV_USB_UHCIREG_H_ 36 37 /*** PCI config registers ***/ 38 39 #define PCI_USBREV 0x60 /* USB protocol revision */ 40 #define PCI_USBREV_MASK 0xff 41 #define PCI_USBREV_PRE_1_0 0x00 42 #define PCI_USBREV_1_0 0x10 43 #define PCI_USBREV_1_1 0x11 44 45 #define PCI_LEGSUP 0xc0 /* Legacy Support register */ 46 #define PCI_LEGSUP_A20PTS __BIT(15) /* End of A20GATE passthru status */ 47 #define PCI_LEGSUP_USBPIRQDEN __BIT(13) /* USB PIRQ D Enable */ 48 #define PCI_LEGSUP_USBIRQS __BIT(12) /* USB IRQ status */ 49 #define PCI_LEGSUP_TBY64W __BIT(11) /* Trap by 64h write status */ 50 #define PCI_LEGSUP_TBY64R __BIT(10) /* Trap by 64h read status */ 51 #define PCI_LEGSUP_TBY60W __BIT(9) /* Trap by 60h write status */ 52 #define PCI_LEGSUP_TBY60R __BIT(8) /* Trap by 60h read status */ 53 #define PCI_LEGSUP_SMIEPTE __BIT(7) /* SMI at end of passthru enable */ 54 #define PCI_LEGSUP_PSS __BIT(6) /* Passthru status */ 55 #define PCI_LEGSUP_A20PTEN __BIT(5) /* A20GATE passthru enable */ 56 #define PCI_LEGSUP_USBSMIEN __BIT(4) /* Enable SMI# generation */ 57 58 #define PCI_CBIO 0x20 /* configuration base IO */ 59 60 #define PCI_INTERFACE_UHCI 0x00 61 62 /*** UHCI registers ***/ 63 64 #define UHCI_CMD 0x00 65 #define UHCI_CMD_RS __BIT(0) 66 #define UHCI_CMD_HCRESET __BIT(1) 67 #define UHCI_CMD_GRESET __BIT(2) 68 #define UHCI_CMD_EGSM __BIT(3) 69 #define UHCI_CMD_FGR __BIT(4) 70 #define UHCI_CMD_SWDBG __BIT(5) 71 #define UHCI_CMD_CF __BIT(6) 72 #define UHCI_CMD_MAXP __BIT(7) 73 74 #define UHCI_STS 0x02 75 #define UHCI_STS_USBINT __BIT(0) 76 #define UHCI_STS_USBEI __BIT(1) 77 #define UHCI_STS_RD __BIT(2) 78 #define UHCI_STS_HSE __BIT(3) 79 #define UHCI_STS_HCPE __BIT(4) 80 #define UHCI_STS_HCH __BIT(5) 81 #define UHCI_STS_ALLINTRS __BITS(5,0) 82 83 #define UHCI_INTR 0x04 84 #define UHCI_INTR_TOCRCIE __BIT(0) 85 #define UHCI_INTR_RIE __BIT(1) 86 #define UHCI_INTR_IOCE __BIT(2) 87 #define UHCI_INTR_SPIE __BIT(3) 88 89 #define UHCI_FRNUM 0x06 90 #define UHCI_FRNUM_MASK __BITS(9,0) 91 92 93 #define UHCI_FLBASEADDR 0x08 94 95 #define UHCI_SOF 0x0c 96 #define UHCI_SOF_MASK __BITS(6,0) 97 98 #define UHCI_PORTSC1 0x010 99 #define UHCI_PORTSC2 0x012 100 #define UHCI_PORTSC_CCS __BIT(0) 101 #define UHCI_PORTSC_CSC __BIT(1) 102 #define UHCI_PORTSC_PE __BIT(2) 103 #define UHCI_PORTSC_POEDC __BIT(3) 104 #define UHCI_PORTSC_LS_MASK __BITS(5,4) 105 #define UHCI_PORTSC_GET_LS(p) __SHIFTOUT((p), UHCI_PORTSC_LS_MASK) 106 #define UHCI_PORTSC_RD __BIT(6) 107 #define UHCI_PORTSC_LSDA __BIT(8) 108 #define UHCI_PORTSC_PR __BIT(9) 109 #define UHCI_PORTSC_OCI __BIT(10) 110 #define UHCI_PORTSC_OCIC __BIT(11) 111 #define UHCI_PORTSC_SUSP __BIT(12) 112 113 #define URWMASK(x) \ 114 ((x) & (UHCI_PORTSC_SUSP | UHCI_PORTSC_PR | UHCI_PORTSC_RD | UHCI_PORTSC_PE)) 115 116 #define UHCI_FRAMELIST_COUNT 1024 117 #define UHCI_FRAMELIST_ALIGN 4096 118 119 #define UHCI_TD_ALIGN 16 120 #define UHCI_QH_ALIGN 16 121 122 typedef uint32_t uhci_physaddr_t; 123 #define UHCI_PTR_T __BIT(0) 124 #define UHCI_PTR_TD 0x00000000 125 #define UHCI_PTR_QH __BIT(1) 126 #define UHCI_PTR_VF __BIT(2) 127 128 /* 129 * Wait this long after a QH has been removed. This gives that HC a 130 * chance to stop looking at it before it's recycled. 131 */ 132 #define UHCI_QH_REMOVE_DELAY 5 133 134 /* 135 * The Queue Heads and Transfer Descriptors are accessed 136 * by both the CPU and the USB controller which run 137 * concurrently. This means that they have to be accessed 138 * with great care. As long as the data structures are 139 * not linked into the controller's frame list they cannot 140 * be accessed by it and anything goes. As soon as a 141 * TD is accessible by the controller it "owns" the td_status 142 * field; it will not be written by the CPU. Similarly 143 * the controller "owns" the qh_elink field. 144 */ 145 146 typedef struct { 147 volatile uhci_physaddr_t td_link; 148 volatile uint32_t td_status; 149 #define UHCI_TD_ACTLEN_MASK __BITS(10,0) 150 #define UHCI_TD_GET_ACTLEN(s) \ 151 ((__SHIFTOUT((s), UHCI_TD_ACTLEN_MASK) + 1) & __SHIFTOUT_MASK(UHCI_TD_ACTLEN_MASK)) 152 #define UHCI_TD_ZERO_ACTLEN(t) ((t) | 0x3ff) 153 #define UHCI_TD_BITSTUFF __BIT(17) 154 #define UHCI_TD_CRCTO __BIT(18) 155 #define UHCI_TD_NAK __BIT(19) 156 #define UHCI_TD_BABBLE __BIT(20) 157 #define UHCI_TD_DBUFFER __BIT(21) 158 #define UHCI_TD_STALLED __BIT(22) 159 #define UHCI_TD_ACTIVE __BIT(23) 160 #define UHCI_TD_STATUS_MASK __BITS(16,23) 161 #define UHCI_TD_IOC __BIT(24) 162 #define UHCI_TD_IOS __BIT(25) 163 #define UHCI_TD_LS __BIT(26) 164 #define UHCI_TD_ERRCNT_MASK __BITS(28,27) 165 #define UHCI_TD_GET_ERRCNT(s) __SHIFTOUT((s), UHCI_TD_ERRCNT_MASK) 166 #define UHCI_TD_SET_ERRCNT(n) __SHIFTIN((n), UHCI_TD_ERRCNT_MASK) 167 #define UHCI_TD_SPD __BIT(29) 168 volatile uint32_t td_token; 169 #define UHCI_TD_PID_IN 0x69 170 #define UHCI_TD_PID_OUT 0xe1 171 #define UHCI_TD_PID_SETUP 0x2d 172 #define UHCI_TD_PID_MASK __BITS(7,0) 173 #define UHCI_TD_SET_PID(p) __SHIFTIN((p), UHCI_TD_PID_MASK) 174 #define UHCI_TD_GET_PID(s) __SHIFTOUT((s), UHCI_TD_PID_MASK) 175 #define UHCI_TD_DEVADDR_MASK __BITS(14,8) 176 #define UHCI_TD_SET_DEVADDR(a) __SHIFTIN((a), UHCI_TD_DEVADDR_MASK) 177 #define UHCI_TD_GET_DEVADDR(s) __SHIFTOUT((s), UHCI_TD_DEVADDR_MASK) 178 #define UHCI_TD_ENDPT_MASK __BITS(18,15) 179 #define UHCI_TD_SET_ENDPT(e) __SHIFTIN((e), UHCI_TD_ENDPT_MASK) 180 #define UHCI_TD_GET_ENDPT(s) __SHIFTOUT((s), UHCI_TD_ENDPT_MASK) 181 #define UHCI_TD_DT_MASK __BIT(19) 182 #define UHCI_TD_SET_DT(t) __SHIFTIN((t), UHCI_TD_DT_MASK) 183 #define UHCI_TD_GET_DT(s) __SHIFTOUT((s), UHCI_TD_DT_MASK) 184 #define UHCI_TD_MAXLEN_MASK __BITS(31,21) 185 #define UHCI_TD_SET_MAXLEN(l) \ 186 __SHIFTIN((((l)-1) & __SHIFTOUT_MASK(UHCI_TD_MAXLEN_MASK)), UHCI_TD_MAXLEN_MASK) 187 #define UHCI_TD_GET_MAXLEN(s) \ 188 (__SHIFTOUT((s), UHCI_TD_MAXLEN_MASK) + 1) 189 volatile uint32_t td_buffer; 190 } uhci_td_t; 191 192 #define UHCI_TD_ERROR \ 193 (UHCI_TD_BITSTUFF|UHCI_TD_CRCTO|UHCI_TD_BABBLE|UHCI_TD_DBUFFER|UHCI_TD_STALLED) 194 195 #define UHCI_TD_SETUP(len, endp, dev) \ 196 (UHCI_TD_SET_MAXLEN(len) | UHCI_TD_SET_ENDPT(endp) | \ 197 UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_SETUP) 198 #define UHCI_TD_OUT(len, endp, dev, dt) \ 199 (UHCI_TD_SET_MAXLEN(len) | UHCI_TD_SET_ENDPT(endp) | \ 200 UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_OUT | UHCI_TD_SET_DT(dt)) 201 #define UHCI_TD_IN(len, endp, dev, dt) \ 202 (UHCI_TD_SET_MAXLEN(len) | UHCI_TD_SET_ENDPT(endp) | \ 203 UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_IN | UHCI_TD_SET_DT(dt)) 204 205 typedef struct { 206 volatile uhci_physaddr_t qh_hlink; 207 volatile uhci_physaddr_t qh_elink; 208 } uhci_qh_t; 209 210 #endif /* _DEV_USB_UHCIREG_H_ */ 211
Indexes created Sat Sep 20 22:09:52 GMT 2025