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      1 /*	$NetBSD: amdgpu_nbio.h,v 1.2 2021/12/18 23:44:58 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2019 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 #ifndef __AMDGPU_NBIO_H__
     26 #define __AMDGPU_NBIO_H__
     27 
     28 /*
     29  * amdgpu nbio functions
     30  */
     31 struct nbio_hdp_flush_reg {
     32 	u32 ref_and_mask_cp0;
     33 	u32 ref_and_mask_cp1;
     34 	u32 ref_and_mask_cp2;
     35 	u32 ref_and_mask_cp3;
     36 	u32 ref_and_mask_cp4;
     37 	u32 ref_and_mask_cp5;
     38 	u32 ref_and_mask_cp6;
     39 	u32 ref_and_mask_cp7;
     40 	u32 ref_and_mask_cp8;
     41 	u32 ref_and_mask_cp9;
     42 	u32 ref_and_mask_sdma0;
     43 	u32 ref_and_mask_sdma1;
     44 	u32 ref_and_mask_sdma2;
     45 	u32 ref_and_mask_sdma3;
     46 	u32 ref_and_mask_sdma4;
     47 	u32 ref_and_mask_sdma5;
     48 	u32 ref_and_mask_sdma6;
     49 	u32 ref_and_mask_sdma7;
     50 };
     51 
     52 struct amdgpu_nbio_funcs {
     53 	const struct nbio_hdp_flush_reg *hdp_flush_reg;
     54 	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
     55 	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
     56 	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
     57 	u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
     58 	u32 (*get_rev_id)(struct amdgpu_device *adev);
     59 	void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
     60 	void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
     61 	u32 (*get_memsize)(struct amdgpu_device *adev);
     62 	void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
     63 			bool use_doorbell, int doorbell_index, int doorbell_size);
     64 	void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
     65 				   int doorbell_index, int instance);
     66 	void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
     67 					 bool enable);
     68 	void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
     69 						  bool enable);
     70 	void (*ih_doorbell_range)(struct amdgpu_device *adev,
     71 				  bool use_doorbell, int doorbell_index);
     72 	void (*enable_doorbell_interrupt)(struct amdgpu_device *adev,
     73 					  bool enable);
     74 	void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
     75 						 bool enable);
     76 	void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
     77 						bool enable);
     78 	void (*get_clockgating_state)(struct amdgpu_device *adev,
     79 				      u32 *flags);
     80 	void (*ih_control)(struct amdgpu_device *adev);
     81 	void (*init_registers)(struct amdgpu_device *adev);
     82 	void (*detect_hw_virt)(struct amdgpu_device *adev);
     83 	void (*remap_hdp_registers)(struct amdgpu_device *adev);
     84 	void (*handle_ras_controller_intr_no_bifring)(struct amdgpu_device *adev);
     85 	void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
     86 	int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
     87 	int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
     88 	void (*query_ras_error_count)(struct amdgpu_device *adev,
     89 					void *ras_error_status);
     90 	int (*ras_late_init)(struct amdgpu_device *adev);
     91 };
     92 
     93 struct amdgpu_nbio {
     94 	const struct nbio_hdp_flush_reg *hdp_flush_reg;
     95 	struct amdgpu_irq_src ras_controller_irq;
     96 	struct amdgpu_irq_src ras_err_event_athub_irq;
     97 	struct ras_common_if *ras_if;
     98 	const struct amdgpu_nbio_funcs *funcs;
     99 };
    100 
    101 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev);
    102 void amdgpu_nbio_ras_fini(struct amdgpu_device *adev);
    103 #endif
    104