1 /* $NetBSD: navi10_sdma_pkt_open.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef __NAVI10_SDMA_PKT_OPEN_H_ 26 #define __NAVI10_SDMA_PKT_OPEN_H_ 27 28 #define SDMA_OP_NOP 0 29 #define SDMA_OP_COPY 1 30 #define SDMA_OP_WRITE 2 31 #define SDMA_OP_INDIRECT 4 32 #define SDMA_OP_FENCE 5 33 #define SDMA_OP_TRAP 6 34 #define SDMA_OP_SEM 7 35 #define SDMA_OP_POLL_REGMEM 8 36 #define SDMA_OP_COND_EXE 9 37 #define SDMA_OP_ATOMIC 10 38 #define SDMA_OP_CONST_FILL 11 39 #define SDMA_OP_PTEPDE 12 40 #define SDMA_OP_TIMESTAMP 13 41 #define SDMA_OP_SRBM_WRITE 14 42 #define SDMA_OP_PRE_EXE 15 43 #define SDMA_OP_GPUVM_INV 16 44 #define SDMA_OP_GCR_REQ 17 45 #define SDMA_OP_DUMMY_TRAP 32 46 #define SDMA_SUBOP_TIMESTAMP_SET 0 47 #define SDMA_SUBOP_TIMESTAMP_GET 1 48 #define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 49 #define SDMA_SUBOP_COPY_LINEAR 0 50 #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 51 #define SDMA_SUBOP_COPY_TILED 1 52 #define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 53 #define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 54 #define SDMA_SUBOP_COPY_SOA 3 55 #define SDMA_SUBOP_COPY_DIRTY_PAGE 7 56 #define SDMA_SUBOP_COPY_LINEAR_PHY 8 57 #define SDMA_SUBOP_COPY_LINEAR_BC 16 58 #define SDMA_SUBOP_COPY_TILED_BC 17 59 #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC 20 60 #define SDMA_SUBOP_COPY_TILED_SUB_WIND_BC 21 61 #define SDMA_SUBOP_COPY_T2T_SUB_WIND_BC 22 62 #define SDMA_SUBOP_WRITE_LINEAR 0 63 #define SDMA_SUBOP_WRITE_TILED 1 64 #define SDMA_SUBOP_WRITE_TILED_BC 17 65 #define SDMA_SUBOP_PTEPDE_GEN 0 66 #define SDMA_SUBOP_PTEPDE_COPY 1 67 #define SDMA_SUBOP_PTEPDE_RMW 2 68 #define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 3 69 #define SDMA_SUBOP_DATA_FILL_MULTI 1 70 #define SDMA_SUBOP_POLL_REG_WRITE_MEM 1 71 #define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2 72 #define SDMA_SUBOP_POLL_MEM_VERIFY 3 73 #define HEADER_AGENT_DISPATCH 4 74 #define HEADER_BARRIER 5 75 #define SDMA_OP_AQL_COPY 0 76 #define SDMA_OP_AQL_BARRIER_OR 0 77 78 /*define for op field*/ 79 #define SDMA_PKT_HEADER_op_offset 0 80 #define SDMA_PKT_HEADER_op_mask 0x000000FF 81 #define SDMA_PKT_HEADER_op_shift 0 82 #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) 83 84 /*define for sub_op field*/ 85 #define SDMA_PKT_HEADER_sub_op_offset 0 86 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF 87 #define SDMA_PKT_HEADER_sub_op_shift 8 88 #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) 89 90 /* 91 ** Definitions for SDMA_PKT_COPY_LINEAR packet 92 */ 93 94 /*define for HEADER word*/ 95 /*define for op field*/ 96 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 97 #define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF 98 #define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 99 #define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) 100 101 /*define for sub_op field*/ 102 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 103 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF 104 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 105 #define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) 106 107 /*define for encrypt field*/ 108 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0 109 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001 110 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16 111 #define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) 112 113 /*define for tmz field*/ 114 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0 115 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001 116 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18 117 #define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) 118 119 /*define for backwards field*/ 120 #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset 0 121 #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask 0x00000001 122 #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift 25 123 #define SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask) << SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift) 124 125 /*define for broadcast field*/ 126 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 127 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 128 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 129 #define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) 130 131 /*define for COUNT word*/ 132 /*define for count field*/ 133 #define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 134 #define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF 135 #define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 136 #define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) 137 138 /*define for PARAMETER word*/ 139 /*define for dst_sw field*/ 140 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 141 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 142 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 143 #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 144 145 /*define for src_sw field*/ 146 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 147 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 148 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 149 #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 150 151 /*define for SRC_ADDR_LO word*/ 152 /*define for src_addr_31_0 field*/ 153 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 154 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 155 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 156 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 157 158 /*define for SRC_ADDR_HI word*/ 159 /*define for src_addr_63_32 field*/ 160 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 161 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 162 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 163 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 164 165 /*define for DST_ADDR_LO word*/ 166 /*define for dst_addr_31_0 field*/ 167 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 168 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 169 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 170 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 171 172 /*define for DST_ADDR_HI word*/ 173 /*define for dst_addr_63_32 field*/ 174 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 175 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 176 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 177 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 178 179 180 /* 181 ** Definitions for SDMA_PKT_COPY_LINEAR_BC packet 182 */ 183 184 /*define for HEADER word*/ 185 /*define for op field*/ 186 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset 0 187 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask 0x000000FF 188 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift 0 189 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift) 190 191 /*define for sub_op field*/ 192 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset 0 193 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask 0x000000FF 194 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift 8 195 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift) 196 197 /*define for COUNT word*/ 198 /*define for count field*/ 199 #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset 1 200 #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask 0x003FFFFF 201 #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift 0 202 #define SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift) 203 204 /*define for PARAMETER word*/ 205 /*define for dst_sw field*/ 206 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset 2 207 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask 0x00000003 208 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift 16 209 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift) 210 211 /*define for dst_ha field*/ 212 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset 2 213 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask 0x00000001 214 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift 22 215 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift) 216 217 /*define for src_sw field*/ 218 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset 2 219 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask 0x00000003 220 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift 24 221 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift) 222 223 /*define for src_ha field*/ 224 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset 2 225 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask 0x00000001 226 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift 30 227 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift) 228 229 /*define for SRC_ADDR_LO word*/ 230 /*define for src_addr_31_0 field*/ 231 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset 3 232 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 233 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 234 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift) 235 236 /*define for SRC_ADDR_HI word*/ 237 /*define for src_addr_63_32 field*/ 238 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset 4 239 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 240 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 241 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift) 242 243 /*define for DST_ADDR_LO word*/ 244 /*define for dst_addr_31_0 field*/ 245 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset 5 246 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 247 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 248 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift) 249 250 /*define for DST_ADDR_HI word*/ 251 /*define for dst_addr_63_32 field*/ 252 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset 6 253 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 254 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 255 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift) 256 257 258 /* 259 ** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet 260 */ 261 262 /*define for HEADER word*/ 263 /*define for op field*/ 264 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0 265 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF 266 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0 267 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) 268 269 /*define for sub_op field*/ 270 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0 271 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF 272 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8 273 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) 274 275 /*define for tmz field*/ 276 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0 277 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001 278 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18 279 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) 280 281 /*define for all field*/ 282 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0 283 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001 284 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31 285 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) 286 287 /*define for COUNT word*/ 288 /*define for count field*/ 289 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1 290 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF 291 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0 292 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) 293 294 /*define for PARAMETER word*/ 295 /*define for dst_mtype field*/ 296 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset 2 297 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask 0x00000007 298 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift 3 299 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift) 300 301 /*define for dst_l2_policy field*/ 302 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset 2 303 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask 0x00000003 304 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift 6 305 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift) 306 307 /*define for src_mtype field*/ 308 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset 2 309 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask 0x00000007 310 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift 11 311 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift) 312 313 /*define for src_l2_policy field*/ 314 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset 2 315 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask 0x00000003 316 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift 14 317 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift) 318 319 /*define for dst_sw field*/ 320 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2 321 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003 322 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 16 323 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) 324 325 /*define for dst_gcc field*/ 326 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2 327 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001 328 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19 329 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) 330 331 /*define for dst_sys field*/ 332 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2 333 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001 334 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20 335 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) 336 337 /*define for dst_snoop field*/ 338 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2 339 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001 340 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22 341 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) 342 343 /*define for dst_gpa field*/ 344 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2 345 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001 346 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23 347 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) 348 349 /*define for src_sw field*/ 350 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2 351 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003 352 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24 353 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) 354 355 /*define for src_sys field*/ 356 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2 357 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001 358 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28 359 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) 360 361 /*define for src_snoop field*/ 362 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2 363 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001 364 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30 365 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) 366 367 /*define for src_gpa field*/ 368 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2 369 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001 370 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31 371 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) 372 373 /*define for SRC_ADDR_LO word*/ 374 /*define for src_addr_31_0 field*/ 375 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3 376 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 377 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0 378 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) 379 380 /*define for SRC_ADDR_HI word*/ 381 /*define for src_addr_63_32 field*/ 382 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4 383 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 384 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0 385 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) 386 387 /*define for DST_ADDR_LO word*/ 388 /*define for dst_addr_31_0 field*/ 389 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5 390 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 391 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0 392 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) 393 394 /*define for DST_ADDR_HI word*/ 395 /*define for dst_addr_63_32 field*/ 396 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6 397 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 398 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0 399 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) 400 401 402 /* 403 ** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet 404 */ 405 406 /*define for HEADER word*/ 407 /*define for op field*/ 408 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0 409 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF 410 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0 411 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) 412 413 /*define for sub_op field*/ 414 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0 415 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF 416 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8 417 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) 418 419 /*define for tmz field*/ 420 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0 421 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001 422 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18 423 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) 424 425 /*define for COUNT word*/ 426 /*define for count field*/ 427 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1 428 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF 429 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0 430 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) 431 432 /*define for PARAMETER word*/ 433 /*define for dst_mtype field*/ 434 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset 2 435 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask 0x00000007 436 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift 3 437 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift) 438 439 /*define for dst_l2_policy field*/ 440 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset 2 441 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask 0x00000003 442 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift 6 443 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift) 444 445 /*define for src_mtype field*/ 446 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset 2 447 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask 0x00000007 448 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift 11 449 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift) 450 451 /*define for src_l2_policy field*/ 452 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset 2 453 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask 0x00000003 454 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift 14 455 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift) 456 457 /*define for dst_sw field*/ 458 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2 459 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003 460 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 16 461 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) 462 463 /*define for dst_gcc field*/ 464 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2 465 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001 466 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19 467 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) 468 469 /*define for dst_sys field*/ 470 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2 471 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001 472 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20 473 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) 474 475 /*define for dst_log field*/ 476 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2 477 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001 478 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21 479 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) 480 481 /*define for dst_snoop field*/ 482 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2 483 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001 484 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22 485 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) 486 487 /*define for dst_gpa field*/ 488 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2 489 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001 490 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23 491 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) 492 493 /*define for src_sw field*/ 494 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2 495 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003 496 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24 497 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) 498 499 /*define for src_gcc field*/ 500 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2 501 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001 502 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27 503 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) 504 505 /*define for src_sys field*/ 506 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2 507 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001 508 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28 509 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) 510 511 /*define for src_snoop field*/ 512 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2 513 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001 514 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30 515 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) 516 517 /*define for src_gpa field*/ 518 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2 519 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001 520 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31 521 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) 522 523 /*define for SRC_ADDR_LO word*/ 524 /*define for src_addr_31_0 field*/ 525 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 526 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 527 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 528 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 529 530 /*define for SRC_ADDR_HI word*/ 531 /*define for src_addr_63_32 field*/ 532 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 533 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 534 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 535 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 536 537 /*define for DST_ADDR_LO word*/ 538 /*define for dst_addr_31_0 field*/ 539 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 540 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 541 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 542 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 543 544 /*define for DST_ADDR_HI word*/ 545 /*define for dst_addr_63_32 field*/ 546 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 547 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 548 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 549 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 550 551 552 /* 553 ** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet 554 */ 555 556 /*define for HEADER word*/ 557 /*define for op field*/ 558 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 559 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF 560 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 561 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) 562 563 /*define for sub_op field*/ 564 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 565 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF 566 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 567 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) 568 569 /*define for encrypt field*/ 570 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0 571 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001 572 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16 573 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) 574 575 /*define for tmz field*/ 576 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0 577 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001 578 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18 579 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) 580 581 /*define for broadcast field*/ 582 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 583 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 584 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 585 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) 586 587 /*define for COUNT word*/ 588 /*define for count field*/ 589 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 590 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF 591 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 592 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) 593 594 /*define for PARAMETER word*/ 595 /*define for dst2_sw field*/ 596 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 597 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 598 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 599 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) 600 601 /*define for dst1_sw field*/ 602 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 603 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 604 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 605 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) 606 607 /*define for src_sw field*/ 608 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 609 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 610 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 611 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) 612 613 /*define for SRC_ADDR_LO word*/ 614 /*define for src_addr_31_0 field*/ 615 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 616 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 617 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 618 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 619 620 /*define for SRC_ADDR_HI word*/ 621 /*define for src_addr_63_32 field*/ 622 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 623 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 624 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 625 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 626 627 /*define for DST1_ADDR_LO word*/ 628 /*define for dst1_addr_31_0 field*/ 629 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 630 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF 631 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 632 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) 633 634 /*define for DST1_ADDR_HI word*/ 635 /*define for dst1_addr_63_32 field*/ 636 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 637 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF 638 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 639 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) 640 641 /*define for DST2_ADDR_LO word*/ 642 /*define for dst2_addr_31_0 field*/ 643 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 644 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF 645 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 646 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) 647 648 /*define for DST2_ADDR_HI word*/ 649 /*define for dst2_addr_63_32 field*/ 650 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 651 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF 652 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 653 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) 654 655 656 /* 657 ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet 658 */ 659 660 /*define for HEADER word*/ 661 /*define for op field*/ 662 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 663 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF 664 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 665 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) 666 667 /*define for sub_op field*/ 668 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 669 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF 670 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 671 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) 672 673 /*define for tmz field*/ 674 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0 675 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001 676 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18 677 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) 678 679 /*define for elementsize field*/ 680 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 681 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 682 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 683 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) 684 685 /*define for SRC_ADDR_LO word*/ 686 /*define for src_addr_31_0 field*/ 687 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 688 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 689 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 690 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) 691 692 /*define for SRC_ADDR_HI word*/ 693 /*define for src_addr_63_32 field*/ 694 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 695 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 696 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 697 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) 698 699 /*define for DW_3 word*/ 700 /*define for src_x field*/ 701 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 702 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF 703 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 704 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) 705 706 /*define for src_y field*/ 707 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 708 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF 709 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 710 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) 711 712 /*define for DW_4 word*/ 713 /*define for src_z field*/ 714 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 715 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x00001FFF 716 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 717 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) 718 719 /*define for src_pitch field*/ 720 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 721 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF 722 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13 723 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) 724 725 /*define for DW_5 word*/ 726 /*define for src_slice_pitch field*/ 727 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 728 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF 729 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 730 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) 731 732 /*define for DST_ADDR_LO word*/ 733 /*define for dst_addr_31_0 field*/ 734 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 735 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 736 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 737 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) 738 739 /*define for DST_ADDR_HI word*/ 740 /*define for dst_addr_63_32 field*/ 741 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 742 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 743 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 744 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) 745 746 /*define for DW_8 word*/ 747 /*define for dst_x field*/ 748 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 749 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF 750 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 751 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) 752 753 /*define for dst_y field*/ 754 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 755 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF 756 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 757 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) 758 759 /*define for DW_9 word*/ 760 /*define for dst_z field*/ 761 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 762 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x00001FFF 763 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 764 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) 765 766 /*define for dst_pitch field*/ 767 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 768 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF 769 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13 770 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) 771 772 /*define for DW_10 word*/ 773 /*define for dst_slice_pitch field*/ 774 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 775 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF 776 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 777 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) 778 779 /*define for DW_11 word*/ 780 /*define for rect_x field*/ 781 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 782 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF 783 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 784 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) 785 786 /*define for rect_y field*/ 787 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 788 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF 789 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 790 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) 791 792 /*define for DW_12 word*/ 793 /*define for rect_z field*/ 794 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 795 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x00001FFF 796 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 797 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) 798 799 /*define for dst_sw field*/ 800 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 801 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 802 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 803 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) 804 805 /*define for src_sw field*/ 806 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 807 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 808 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 809 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) 810 811 812 /* 813 ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_BC packet 814 */ 815 816 /*define for HEADER word*/ 817 /*define for op field*/ 818 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset 0 819 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask 0x000000FF 820 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift 0 821 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift) 822 823 /*define for sub_op field*/ 824 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset 0 825 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF 826 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift 8 827 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift) 828 829 /*define for elementsize field*/ 830 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset 0 831 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask 0x00000007 832 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift 29 833 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift) 834 835 /*define for SRC_ADDR_LO word*/ 836 /*define for src_addr_31_0 field*/ 837 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 838 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 839 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 840 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift) 841 842 /*define for SRC_ADDR_HI word*/ 843 /*define for src_addr_63_32 field*/ 844 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 845 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 846 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 847 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift) 848 849 /*define for DW_3 word*/ 850 /*define for src_x field*/ 851 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset 3 852 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask 0x00003FFF 853 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift 0 854 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift) 855 856 /*define for src_y field*/ 857 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset 3 858 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask 0x00003FFF 859 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift 16 860 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift) 861 862 /*define for DW_4 word*/ 863 /*define for src_z field*/ 864 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset 4 865 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask 0x000007FF 866 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift 0 867 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift) 868 869 /*define for src_pitch field*/ 870 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset 4 871 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask 0x00003FFF 872 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift 13 873 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift) 874 875 /*define for DW_5 word*/ 876 /*define for src_slice_pitch field*/ 877 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset 5 878 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask 0x0FFFFFFF 879 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift 0 880 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift) 881 882 /*define for DST_ADDR_LO word*/ 883 /*define for dst_addr_31_0 field*/ 884 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset 6 885 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 886 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 887 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift) 888 889 /*define for DST_ADDR_HI word*/ 890 /*define for dst_addr_63_32 field*/ 891 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset 7 892 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 893 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 894 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift) 895 896 /*define for DW_8 word*/ 897 /*define for dst_x field*/ 898 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset 8 899 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask 0x00003FFF 900 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift 0 901 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift) 902 903 /*define for dst_y field*/ 904 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset 8 905 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask 0x00003FFF 906 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift 16 907 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift) 908 909 /*define for DW_9 word*/ 910 /*define for dst_z field*/ 911 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset 9 912 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask 0x000007FF 913 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift 0 914 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift) 915 916 /*define for dst_pitch field*/ 917 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset 9 918 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask 0x00003FFF 919 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift 13 920 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift) 921 922 /*define for DW_10 word*/ 923 /*define for dst_slice_pitch field*/ 924 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset 10 925 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask 0x0FFFFFFF 926 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift 0 927 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift) 928 929 /*define for DW_11 word*/ 930 /*define for rect_x field*/ 931 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset 11 932 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask 0x00003FFF 933 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift 0 934 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift) 935 936 /*define for rect_y field*/ 937 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset 11 938 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask 0x00003FFF 939 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift 16 940 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift) 941 942 /*define for DW_12 word*/ 943 /*define for rect_z field*/ 944 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset 12 945 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask 0x000007FF 946 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift 0 947 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift) 948 949 /*define for dst_sw field*/ 950 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset 12 951 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask 0x00000003 952 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift 16 953 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift) 954 955 /*define for dst_ha field*/ 956 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset 12 957 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask 0x00000001 958 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift 22 959 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift) 960 961 /*define for src_sw field*/ 962 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset 12 963 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask 0x00000003 964 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift 24 965 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift) 966 967 /*define for src_ha field*/ 968 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset 12 969 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask 0x00000001 970 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift 30 971 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift) 972 973 974 /* 975 ** Definitions for SDMA_PKT_COPY_TILED packet 976 */ 977 978 /*define for HEADER word*/ 979 /*define for op field*/ 980 #define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 981 #define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF 982 #define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 983 #define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) 984 985 /*define for sub_op field*/ 986 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 987 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF 988 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 989 #define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) 990 991 /*define for encrypt field*/ 992 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0 993 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001 994 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16 995 #define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) 996 997 /*define for tmz field*/ 998 #define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0 999 #define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001 1000 #define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18 1001 #define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) 1002 1003 /*define for detile field*/ 1004 #define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 1005 #define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 1006 #define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 1007 #define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) 1008 1009 /*define for TILED_ADDR_LO word*/ 1010 /*define for tiled_addr_31_0 field*/ 1011 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 1012 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 1013 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 1014 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) 1015 1016 /*define for TILED_ADDR_HI word*/ 1017 /*define for tiled_addr_63_32 field*/ 1018 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 1019 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 1020 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 1021 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) 1022 1023 /*define for DW_3 word*/ 1024 /*define for width field*/ 1025 #define SDMA_PKT_COPY_TILED_DW_3_width_offset 3 1026 #define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF 1027 #define SDMA_PKT_COPY_TILED_DW_3_width_shift 0 1028 #define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) 1029 1030 /*define for DW_4 word*/ 1031 /*define for height field*/ 1032 #define SDMA_PKT_COPY_TILED_DW_4_height_offset 4 1033 #define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF 1034 #define SDMA_PKT_COPY_TILED_DW_4_height_shift 0 1035 #define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) 1036 1037 /*define for depth field*/ 1038 #define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4 1039 #define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x00001FFF 1040 #define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16 1041 #define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) 1042 1043 /*define for DW_5 word*/ 1044 /*define for element_size field*/ 1045 #define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 1046 #define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 1047 #define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 1048 #define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) 1049 1050 /*define for swizzle_mode field*/ 1051 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5 1052 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F 1053 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3 1054 #define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) 1055 1056 /*define for dimension field*/ 1057 #define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5 1058 #define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003 1059 #define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9 1060 #define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) 1061 1062 /*define for mip_max field*/ 1063 #define SDMA_PKT_COPY_TILED_DW_5_mip_max_offset 5 1064 #define SDMA_PKT_COPY_TILED_DW_5_mip_max_mask 0x0000000F 1065 #define SDMA_PKT_COPY_TILED_DW_5_mip_max_shift 16 1066 #define SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mip_max_mask) << SDMA_PKT_COPY_TILED_DW_5_mip_max_shift) 1067 1068 /*define for DW_6 word*/ 1069 /*define for x field*/ 1070 #define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 1071 #define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF 1072 #define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 1073 #define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) 1074 1075 /*define for y field*/ 1076 #define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 1077 #define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF 1078 #define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 1079 #define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) 1080 1081 /*define for DW_7 word*/ 1082 /*define for z field*/ 1083 #define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 1084 #define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00001FFF 1085 #define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 1086 #define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) 1087 1088 /*define for linear_sw field*/ 1089 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 1090 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 1091 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 1092 #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) 1093 1094 /*define for linear_cc field*/ 1095 #define SDMA_PKT_COPY_TILED_DW_7_linear_cc_offset 7 1096 #define SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask 0x00000001 1097 #define SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift 20 1098 #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_CC(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift) 1099 1100 /*define for tile_sw field*/ 1101 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 1102 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 1103 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 1104 #define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) 1105 1106 /*define for LINEAR_ADDR_LO word*/ 1107 /*define for linear_addr_31_0 field*/ 1108 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 1109 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1110 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1111 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1112 1113 /*define for LINEAR_ADDR_HI word*/ 1114 /*define for linear_addr_63_32 field*/ 1115 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 1116 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1117 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1118 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1119 1120 /*define for LINEAR_PITCH word*/ 1121 /*define for linear_pitch field*/ 1122 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 1123 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 1124 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 1125 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) 1126 1127 /*define for LINEAR_SLICE_PITCH word*/ 1128 /*define for linear_slice_pitch field*/ 1129 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 1130 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 1131 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 1132 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 1133 1134 /*define for COUNT word*/ 1135 /*define for count field*/ 1136 #define SDMA_PKT_COPY_TILED_COUNT_count_offset 12 1137 #define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x003FFFFF 1138 #define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 1139 #define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) 1140 1141 1142 /* 1143 ** Definitions for SDMA_PKT_COPY_TILED_BC packet 1144 */ 1145 1146 /*define for HEADER word*/ 1147 /*define for op field*/ 1148 #define SDMA_PKT_COPY_TILED_BC_HEADER_op_offset 0 1149 #define SDMA_PKT_COPY_TILED_BC_HEADER_op_mask 0x000000FF 1150 #define SDMA_PKT_COPY_TILED_BC_HEADER_op_shift 0 1151 #define SDMA_PKT_COPY_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_op_shift) 1152 1153 /*define for sub_op field*/ 1154 #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset 0 1155 #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask 0x000000FF 1156 #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift 8 1157 #define SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift) 1158 1159 /*define for detile field*/ 1160 #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset 0 1161 #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask 0x00000001 1162 #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift 31 1163 #define SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift) 1164 1165 /*define for TILED_ADDR_LO word*/ 1166 /*define for tiled_addr_31_0 field*/ 1167 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 1168 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 1169 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 1170 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) 1171 1172 /*define for TILED_ADDR_HI word*/ 1173 /*define for tiled_addr_63_32 field*/ 1174 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 1175 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 1176 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 1177 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) 1178 1179 /*define for DW_3 word*/ 1180 /*define for width field*/ 1181 #define SDMA_PKT_COPY_TILED_BC_DW_3_width_offset 3 1182 #define SDMA_PKT_COPY_TILED_BC_DW_3_width_mask 0x00003FFF 1183 #define SDMA_PKT_COPY_TILED_BC_DW_3_width_shift 0 1184 #define SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_3_width_mask) << SDMA_PKT_COPY_TILED_BC_DW_3_width_shift) 1185 1186 /*define for DW_4 word*/ 1187 /*define for height field*/ 1188 #define SDMA_PKT_COPY_TILED_BC_DW_4_height_offset 4 1189 #define SDMA_PKT_COPY_TILED_BC_DW_4_height_mask 0x00003FFF 1190 #define SDMA_PKT_COPY_TILED_BC_DW_4_height_shift 0 1191 #define SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_height_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_height_shift) 1192 1193 /*define for depth field*/ 1194 #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset 4 1195 #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask 0x000007FF 1196 #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift 16 1197 #define SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift) 1198 1199 /*define for DW_5 word*/ 1200 /*define for element_size field*/ 1201 #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset 5 1202 #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask 0x00000007 1203 #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift 0 1204 #define SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift) 1205 1206 /*define for array_mode field*/ 1207 #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset 5 1208 #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask 0x0000000F 1209 #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift 3 1210 #define SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift) 1211 1212 /*define for mit_mode field*/ 1213 #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset 5 1214 #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask 0x00000007 1215 #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift 8 1216 #define SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift) 1217 1218 /*define for tilesplit_size field*/ 1219 #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset 5 1220 #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 1221 #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift 11 1222 #define SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift) 1223 1224 /*define for bank_w field*/ 1225 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset 5 1226 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask 0x00000003 1227 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift 15 1228 #define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift) 1229 1230 /*define for bank_h field*/ 1231 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset 5 1232 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask 0x00000003 1233 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift 18 1234 #define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift) 1235 1236 /*define for num_bank field*/ 1237 #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset 5 1238 #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask 0x00000003 1239 #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift 21 1240 #define SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift) 1241 1242 /*define for mat_aspt field*/ 1243 #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset 5 1244 #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask 0x00000003 1245 #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift 24 1246 #define SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift) 1247 1248 /*define for pipe_config field*/ 1249 #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset 5 1250 #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask 0x0000001F 1251 #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift 26 1252 #define SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift) 1253 1254 /*define for DW_6 word*/ 1255 /*define for x field*/ 1256 #define SDMA_PKT_COPY_TILED_BC_DW_6_x_offset 6 1257 #define SDMA_PKT_COPY_TILED_BC_DW_6_x_mask 0x00003FFF 1258 #define SDMA_PKT_COPY_TILED_BC_DW_6_x_shift 0 1259 #define SDMA_PKT_COPY_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_x_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_x_shift) 1260 1261 /*define for y field*/ 1262 #define SDMA_PKT_COPY_TILED_BC_DW_6_y_offset 6 1263 #define SDMA_PKT_COPY_TILED_BC_DW_6_y_mask 0x00003FFF 1264 #define SDMA_PKT_COPY_TILED_BC_DW_6_y_shift 16 1265 #define SDMA_PKT_COPY_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_y_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_y_shift) 1266 1267 /*define for DW_7 word*/ 1268 /*define for z field*/ 1269 #define SDMA_PKT_COPY_TILED_BC_DW_7_z_offset 7 1270 #define SDMA_PKT_COPY_TILED_BC_DW_7_z_mask 0x000007FF 1271 #define SDMA_PKT_COPY_TILED_BC_DW_7_z_shift 0 1272 #define SDMA_PKT_COPY_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_z_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_z_shift) 1273 1274 /*define for linear_sw field*/ 1275 #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset 7 1276 #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask 0x00000003 1277 #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift 16 1278 #define SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift) 1279 1280 /*define for tile_sw field*/ 1281 #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset 7 1282 #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask 0x00000003 1283 #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift 24 1284 #define SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift) 1285 1286 /*define for LINEAR_ADDR_LO word*/ 1287 /*define for linear_addr_31_0 field*/ 1288 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 1289 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1290 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1291 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1292 1293 /*define for LINEAR_ADDR_HI word*/ 1294 /*define for linear_addr_63_32 field*/ 1295 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 1296 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1297 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1298 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1299 1300 /*define for LINEAR_PITCH word*/ 1301 /*define for linear_pitch field*/ 1302 #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset 10 1303 #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 1304 #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift 0 1305 #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift) 1306 1307 /*define for COUNT word*/ 1308 /*define for count field*/ 1309 #define SDMA_PKT_COPY_TILED_BC_COUNT_count_offset 11 1310 #define SDMA_PKT_COPY_TILED_BC_COUNT_count_mask 0x000FFFFF 1311 #define SDMA_PKT_COPY_TILED_BC_COUNT_count_shift 2 1312 #define SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_BC_COUNT_count_mask) << SDMA_PKT_COPY_TILED_BC_COUNT_count_shift) 1313 1314 1315 /* 1316 ** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet 1317 */ 1318 1319 /*define for HEADER word*/ 1320 /*define for op field*/ 1321 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 1322 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF 1323 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 1324 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) 1325 1326 /*define for sub_op field*/ 1327 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 1328 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF 1329 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 1330 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) 1331 1332 /*define for encrypt field*/ 1333 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0 1334 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001 1335 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16 1336 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) 1337 1338 /*define for tmz field*/ 1339 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0 1340 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001 1341 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18 1342 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) 1343 1344 /*define for videocopy field*/ 1345 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 1346 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 1347 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 1348 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) 1349 1350 /*define for broadcast field*/ 1351 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 1352 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 1353 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 1354 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) 1355 1356 /*define for TILED_ADDR_LO_0 word*/ 1357 /*define for tiled_addr0_31_0 field*/ 1358 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 1359 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF 1360 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 1361 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) 1362 1363 /*define for TILED_ADDR_HI_0 word*/ 1364 /*define for tiled_addr0_63_32 field*/ 1365 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 1366 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF 1367 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 1368 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) 1369 1370 /*define for TILED_ADDR_LO_1 word*/ 1371 /*define for tiled_addr1_31_0 field*/ 1372 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 1373 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF 1374 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 1375 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) 1376 1377 /*define for TILED_ADDR_HI_1 word*/ 1378 /*define for tiled_addr1_63_32 field*/ 1379 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 1380 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF 1381 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 1382 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) 1383 1384 /*define for DW_5 word*/ 1385 /*define for width field*/ 1386 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5 1387 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF 1388 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0 1389 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) 1390 1391 /*define for DW_6 word*/ 1392 /*define for height field*/ 1393 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6 1394 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF 1395 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0 1396 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) 1397 1398 /*define for depth field*/ 1399 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6 1400 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x00001FFF 1401 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16 1402 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) 1403 1404 /*define for DW_7 word*/ 1405 /*define for element_size field*/ 1406 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 1407 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 1408 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 1409 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) 1410 1411 /*define for swizzle_mode field*/ 1412 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7 1413 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F 1414 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3 1415 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) 1416 1417 /*define for dimension field*/ 1418 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7 1419 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003 1420 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9 1421 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) 1422 1423 /*define for mip_max field*/ 1424 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset 7 1425 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask 0x0000000F 1426 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift 16 1427 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift) 1428 1429 /*define for DW_8 word*/ 1430 /*define for x field*/ 1431 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 1432 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF 1433 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 1434 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) 1435 1436 /*define for y field*/ 1437 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 1438 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF 1439 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 1440 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) 1441 1442 /*define for DW_9 word*/ 1443 /*define for z field*/ 1444 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 1445 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00001FFF 1446 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 1447 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) 1448 1449 /*define for DW_10 word*/ 1450 /*define for dst2_sw field*/ 1451 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 1452 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 1453 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 1454 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) 1455 1456 /*define for linear_sw field*/ 1457 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 1458 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 1459 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 1460 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) 1461 1462 /*define for tile_sw field*/ 1463 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 1464 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 1465 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 1466 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) 1467 1468 /*define for LINEAR_ADDR_LO word*/ 1469 /*define for linear_addr_31_0 field*/ 1470 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 1471 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1472 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1473 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1474 1475 /*define for LINEAR_ADDR_HI word*/ 1476 /*define for linear_addr_63_32 field*/ 1477 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 1478 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1479 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1480 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1481 1482 /*define for LINEAR_PITCH word*/ 1483 /*define for linear_pitch field*/ 1484 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 1485 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 1486 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 1487 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) 1488 1489 /*define for LINEAR_SLICE_PITCH word*/ 1490 /*define for linear_slice_pitch field*/ 1491 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14 1492 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 1493 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 1494 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 1495 1496 /*define for COUNT word*/ 1497 /*define for count field*/ 1498 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15 1499 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x003FFFFF 1500 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 1501 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) 1502 1503 1504 /* 1505 ** Definitions for SDMA_PKT_COPY_T2T packet 1506 */ 1507 1508 /*define for HEADER word*/ 1509 /*define for op field*/ 1510 #define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 1511 #define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF 1512 #define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 1513 #define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) 1514 1515 /*define for sub_op field*/ 1516 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 1517 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF 1518 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 1519 #define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) 1520 1521 /*define for tmz field*/ 1522 #define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0 1523 #define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001 1524 #define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 18 1525 #define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) 1526 1527 /*define for dcc field*/ 1528 #define SDMA_PKT_COPY_T2T_HEADER_dcc_offset 0 1529 #define SDMA_PKT_COPY_T2T_HEADER_dcc_mask 0x00000001 1530 #define SDMA_PKT_COPY_T2T_HEADER_dcc_shift 19 1531 #define SDMA_PKT_COPY_T2T_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_shift) 1532 1533 /*define for dcc_dir field*/ 1534 #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset 0 1535 #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask 0x00000001 1536 #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift 31 1537 #define SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift) 1538 1539 /*define for SRC_ADDR_LO word*/ 1540 /*define for src_addr_31_0 field*/ 1541 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 1542 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 1543 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 1544 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) 1545 1546 /*define for SRC_ADDR_HI word*/ 1547 /*define for src_addr_63_32 field*/ 1548 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 1549 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 1550 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 1551 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) 1552 1553 /*define for DW_3 word*/ 1554 /*define for src_x field*/ 1555 #define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 1556 #define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF 1557 #define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 1558 #define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) 1559 1560 /*define for src_y field*/ 1561 #define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 1562 #define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF 1563 #define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 1564 #define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) 1565 1566 /*define for DW_4 word*/ 1567 /*define for src_z field*/ 1568 #define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 1569 #define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x00001FFF 1570 #define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 1571 #define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) 1572 1573 /*define for src_width field*/ 1574 #define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4 1575 #define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF 1576 #define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 16 1577 #define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) 1578 1579 /*define for DW_5 word*/ 1580 /*define for src_height field*/ 1581 #define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5 1582 #define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF 1583 #define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0 1584 #define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) 1585 1586 /*define for src_depth field*/ 1587 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5 1588 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x00001FFF 1589 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 16 1590 #define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) 1591 1592 /*define for DW_6 word*/ 1593 /*define for src_element_size field*/ 1594 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 1595 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 1596 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 1597 #define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) 1598 1599 /*define for src_swizzle_mode field*/ 1600 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6 1601 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F 1602 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 3 1603 #define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) 1604 1605 /*define for src_dimension field*/ 1606 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6 1607 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003 1608 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 9 1609 #define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) 1610 1611 /*define for src_mip_max field*/ 1612 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset 6 1613 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask 0x0000000F 1614 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift 16 1615 #define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift) 1616 1617 /*define for src_mip_id field*/ 1618 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset 6 1619 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask 0x0000000F 1620 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift 20 1621 #define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift) 1622 1623 /*define for DST_ADDR_LO word*/ 1624 /*define for dst_addr_31_0 field*/ 1625 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 1626 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1627 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 1628 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) 1629 1630 /*define for DST_ADDR_HI word*/ 1631 /*define for dst_addr_63_32 field*/ 1632 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 1633 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1634 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 1635 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) 1636 1637 /*define for DW_9 word*/ 1638 /*define for dst_x field*/ 1639 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 1640 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF 1641 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 1642 #define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) 1643 1644 /*define for dst_y field*/ 1645 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 1646 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF 1647 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 1648 #define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) 1649 1650 /*define for DW_10 word*/ 1651 /*define for dst_z field*/ 1652 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 1653 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x00001FFF 1654 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 1655 #define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) 1656 1657 /*define for dst_width field*/ 1658 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10 1659 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF 1660 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 16 1661 #define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) 1662 1663 /*define for DW_11 word*/ 1664 /*define for dst_height field*/ 1665 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11 1666 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF 1667 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0 1668 #define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) 1669 1670 /*define for dst_depth field*/ 1671 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11 1672 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x00001FFF 1673 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 16 1674 #define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) 1675 1676 /*define for DW_12 word*/ 1677 /*define for dst_element_size field*/ 1678 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12 1679 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007 1680 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0 1681 #define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) 1682 1683 /*define for dst_swizzle_mode field*/ 1684 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12 1685 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F 1686 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 3 1687 #define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) 1688 1689 /*define for dst_dimension field*/ 1690 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12 1691 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003 1692 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 9 1693 #define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) 1694 1695 /*define for dst_mip_max field*/ 1696 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset 12 1697 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask 0x0000000F 1698 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift 16 1699 #define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift) 1700 1701 /*define for dst_mip_id field*/ 1702 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset 12 1703 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask 0x0000000F 1704 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift 20 1705 #define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift) 1706 1707 /*define for DW_13 word*/ 1708 /*define for rect_x field*/ 1709 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 1710 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF 1711 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 1712 #define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) 1713 1714 /*define for rect_y field*/ 1715 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 1716 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF 1717 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 1718 #define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) 1719 1720 /*define for DW_14 word*/ 1721 /*define for rect_z field*/ 1722 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 1723 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x00001FFF 1724 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 1725 #define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) 1726 1727 /*define for dst_sw field*/ 1728 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 1729 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 1730 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 1731 #define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) 1732 1733 /*define for src_sw field*/ 1734 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 1735 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 1736 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 1737 #define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) 1738 1739 /*define for META_ADDR_LO word*/ 1740 /*define for meta_addr_31_0 field*/ 1741 #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset 15 1742 #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF 1743 #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift 0 1744 #define SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift) 1745 1746 /*define for META_ADDR_HI word*/ 1747 /*define for meta_addr_63_32 field*/ 1748 #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset 16 1749 #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF 1750 #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift 0 1751 #define SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift) 1752 1753 /*define for META_CONFIG word*/ 1754 /*define for data_format field*/ 1755 #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset 17 1756 #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask 0x0000007F 1757 #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift 0 1758 #define SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift) 1759 1760 /*define for color_transform_disable field*/ 1761 #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset 17 1762 #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask 0x00000001 1763 #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift 7 1764 #define SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift) 1765 1766 /*define for alpha_is_on_msb field*/ 1767 #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset 17 1768 #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask 0x00000001 1769 #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift 8 1770 #define SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift) 1771 1772 /*define for number_type field*/ 1773 #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset 17 1774 #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask 0x00000007 1775 #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift 9 1776 #define SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift) 1777 1778 /*define for surface_type field*/ 1779 #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset 17 1780 #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask 0x00000003 1781 #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift 12 1782 #define SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift) 1783 1784 /*define for max_comp_block_size field*/ 1785 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset 17 1786 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask 0x00000003 1787 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift 24 1788 #define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift) 1789 1790 /*define for max_uncomp_block_size field*/ 1791 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset 17 1792 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask 0x00000003 1793 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift 26 1794 #define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift) 1795 1796 /*define for write_compress_enable field*/ 1797 #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset 17 1798 #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask 0x00000001 1799 #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift 28 1800 #define SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift) 1801 1802 /*define for meta_tmz field*/ 1803 #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset 17 1804 #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask 0x00000001 1805 #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift 29 1806 #define SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift) 1807 1808 1809 /* 1810 ** Definitions for SDMA_PKT_COPY_T2T_BC packet 1811 */ 1812 1813 /*define for HEADER word*/ 1814 /*define for op field*/ 1815 #define SDMA_PKT_COPY_T2T_BC_HEADER_op_offset 0 1816 #define SDMA_PKT_COPY_T2T_BC_HEADER_op_mask 0x000000FF 1817 #define SDMA_PKT_COPY_T2T_BC_HEADER_op_shift 0 1818 #define SDMA_PKT_COPY_T2T_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_op_shift) 1819 1820 /*define for sub_op field*/ 1821 #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset 0 1822 #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask 0x000000FF 1823 #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift 8 1824 #define SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift) 1825 1826 /*define for SRC_ADDR_LO word*/ 1827 /*define for src_addr_31_0 field*/ 1828 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 1829 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 1830 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 1831 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift) 1832 1833 /*define for SRC_ADDR_HI word*/ 1834 /*define for src_addr_63_32 field*/ 1835 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 1836 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 1837 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 1838 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift) 1839 1840 /*define for DW_3 word*/ 1841 /*define for src_x field*/ 1842 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset 3 1843 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask 0x00003FFF 1844 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift 0 1845 #define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift) 1846 1847 /*define for src_y field*/ 1848 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset 3 1849 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask 0x00003FFF 1850 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift 16 1851 #define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift) 1852 1853 /*define for DW_4 word*/ 1854 /*define for src_z field*/ 1855 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset 4 1856 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask 0x000007FF 1857 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift 0 1858 #define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift) 1859 1860 /*define for src_width field*/ 1861 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset 4 1862 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask 0x00003FFF 1863 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift 16 1864 #define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift) 1865 1866 /*define for DW_5 word*/ 1867 /*define for src_height field*/ 1868 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset 5 1869 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask 0x00003FFF 1870 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift 0 1871 #define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift) 1872 1873 /*define for src_depth field*/ 1874 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset 5 1875 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask 0x000007FF 1876 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift 16 1877 #define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift) 1878 1879 /*define for DW_6 word*/ 1880 /*define for src_element_size field*/ 1881 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset 6 1882 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask 0x00000007 1883 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift 0 1884 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift) 1885 1886 /*define for src_array_mode field*/ 1887 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset 6 1888 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask 0x0000000F 1889 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift 3 1890 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift) 1891 1892 /*define for src_mit_mode field*/ 1893 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset 6 1894 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask 0x00000007 1895 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift 8 1896 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift) 1897 1898 /*define for src_tilesplit_size field*/ 1899 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset 6 1900 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask 0x00000007 1901 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift 11 1902 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift) 1903 1904 /*define for src_bank_w field*/ 1905 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset 6 1906 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask 0x00000003 1907 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift 15 1908 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift) 1909 1910 /*define for src_bank_h field*/ 1911 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset 6 1912 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask 0x00000003 1913 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift 18 1914 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift) 1915 1916 /*define for src_num_bank field*/ 1917 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset 6 1918 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask 0x00000003 1919 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift 21 1920 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift) 1921 1922 /*define for src_mat_aspt field*/ 1923 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset 6 1924 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask 0x00000003 1925 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift 24 1926 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift) 1927 1928 /*define for src_pipe_config field*/ 1929 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset 6 1930 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask 0x0000001F 1931 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift 26 1932 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift) 1933 1934 /*define for DST_ADDR_LO word*/ 1935 /*define for dst_addr_31_0 field*/ 1936 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset 7 1937 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1938 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 1939 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift) 1940 1941 /*define for DST_ADDR_HI word*/ 1942 /*define for dst_addr_63_32 field*/ 1943 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset 8 1944 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1945 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 1946 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift) 1947 1948 /*define for DW_9 word*/ 1949 /*define for dst_x field*/ 1950 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset 9 1951 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask 0x00003FFF 1952 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift 0 1953 #define SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift) 1954 1955 /*define for dst_y field*/ 1956 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset 9 1957 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask 0x00003FFF 1958 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift 16 1959 #define SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift) 1960 1961 /*define for DW_10 word*/ 1962 /*define for dst_z field*/ 1963 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset 10 1964 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask 0x000007FF 1965 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift 0 1966 #define SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift) 1967 1968 /*define for dst_width field*/ 1969 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset 10 1970 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask 0x00003FFF 1971 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift 16 1972 #define SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift) 1973 1974 /*define for DW_11 word*/ 1975 /*define for dst_height field*/ 1976 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset 11 1977 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask 0x00003FFF 1978 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift 0 1979 #define SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift) 1980 1981 /*define for dst_depth field*/ 1982 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset 11 1983 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask 0x00000FFF 1984 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift 16 1985 #define SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift) 1986 1987 /*define for DW_12 word*/ 1988 /*define for dst_element_size field*/ 1989 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset 12 1990 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask 0x00000007 1991 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift 0 1992 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift) 1993 1994 /*define for dst_array_mode field*/ 1995 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset 12 1996 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask 0x0000000F 1997 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift 3 1998 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift) 1999 2000 /*define for dst_mit_mode field*/ 2001 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset 12 2002 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask 0x00000007 2003 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift 8 2004 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift) 2005 2006 /*define for dst_tilesplit_size field*/ 2007 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset 12 2008 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask 0x00000007 2009 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift 11 2010 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift) 2011 2012 /*define for dst_bank_w field*/ 2013 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset 12 2014 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask 0x00000003 2015 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift 15 2016 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift) 2017 2018 /*define for dst_bank_h field*/ 2019 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset 12 2020 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask 0x00000003 2021 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift 18 2022 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift) 2023 2024 /*define for dst_num_bank field*/ 2025 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset 12 2026 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask 0x00000003 2027 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift 21 2028 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift) 2029 2030 /*define for dst_mat_aspt field*/ 2031 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset 12 2032 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask 0x00000003 2033 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift 24 2034 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift) 2035 2036 /*define for dst_pipe_config field*/ 2037 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset 12 2038 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask 0x0000001F 2039 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift 26 2040 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift) 2041 2042 /*define for DW_13 word*/ 2043 /*define for rect_x field*/ 2044 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset 13 2045 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask 0x00003FFF 2046 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift 0 2047 #define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift) 2048 2049 /*define for rect_y field*/ 2050 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset 13 2051 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask 0x00003FFF 2052 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift 16 2053 #define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift) 2054 2055 /*define for DW_14 word*/ 2056 /*define for rect_z field*/ 2057 #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset 14 2058 #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask 0x000007FF 2059 #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift 0 2060 #define SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift) 2061 2062 /*define for dst_sw field*/ 2063 #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset 14 2064 #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask 0x00000003 2065 #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift 16 2066 #define SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift) 2067 2068 /*define for src_sw field*/ 2069 #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset 14 2070 #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask 0x00000003 2071 #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift 24 2072 #define SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift) 2073 2074 2075 /* 2076 ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet 2077 */ 2078 2079 /*define for HEADER word*/ 2080 /*define for op field*/ 2081 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 2082 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF 2083 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 2084 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) 2085 2086 /*define for sub_op field*/ 2087 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 2088 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF 2089 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 2090 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) 2091 2092 /*define for tmz field*/ 2093 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0 2094 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001 2095 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 18 2096 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) 2097 2098 /*define for dcc field*/ 2099 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset 0 2100 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask 0x00000001 2101 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift 19 2102 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift) 2103 2104 /*define for detile field*/ 2105 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 2106 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 2107 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 2108 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) 2109 2110 /*define for TILED_ADDR_LO word*/ 2111 /*define for tiled_addr_31_0 field*/ 2112 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 2113 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 2114 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 2115 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) 2116 2117 /*define for TILED_ADDR_HI word*/ 2118 /*define for tiled_addr_63_32 field*/ 2119 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 2120 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 2121 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 2122 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) 2123 2124 /*define for DW_3 word*/ 2125 /*define for tiled_x field*/ 2126 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 2127 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF 2128 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 2129 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) 2130 2131 /*define for tiled_y field*/ 2132 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 2133 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF 2134 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 2135 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) 2136 2137 /*define for DW_4 word*/ 2138 /*define for tiled_z field*/ 2139 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 2140 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x00001FFF 2141 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 2142 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) 2143 2144 /*define for width field*/ 2145 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4 2146 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF 2147 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 16 2148 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) 2149 2150 /*define for DW_5 word*/ 2151 /*define for height field*/ 2152 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5 2153 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF 2154 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0 2155 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) 2156 2157 /*define for depth field*/ 2158 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5 2159 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x00001FFF 2160 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 16 2161 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) 2162 2163 /*define for DW_6 word*/ 2164 /*define for element_size field*/ 2165 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 2166 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 2167 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 2168 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) 2169 2170 /*define for swizzle_mode field*/ 2171 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6 2172 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F 2173 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 3 2174 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) 2175 2176 /*define for dimension field*/ 2177 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6 2178 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003 2179 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 9 2180 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) 2181 2182 /*define for mip_max field*/ 2183 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset 6 2184 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask 0x0000000F 2185 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift 16 2186 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift) 2187 2188 /*define for mip_id field*/ 2189 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset 6 2190 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask 0x0000000F 2191 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift 20 2192 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift) 2193 2194 /*define for LINEAR_ADDR_LO word*/ 2195 /*define for linear_addr_31_0 field*/ 2196 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 2197 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 2198 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 2199 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) 2200 2201 /*define for LINEAR_ADDR_HI word*/ 2202 /*define for linear_addr_63_32 field*/ 2203 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 2204 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 2205 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 2206 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) 2207 2208 /*define for DW_9 word*/ 2209 /*define for linear_x field*/ 2210 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 2211 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF 2212 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 2213 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) 2214 2215 /*define for linear_y field*/ 2216 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 2217 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF 2218 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 2219 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) 2220 2221 /*define for DW_10 word*/ 2222 /*define for linear_z field*/ 2223 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 2224 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x00001FFF 2225 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 2226 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) 2227 2228 /*define for linear_pitch field*/ 2229 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 2230 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF 2231 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 2232 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) 2233 2234 /*define for DW_11 word*/ 2235 /*define for linear_slice_pitch field*/ 2236 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 2237 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF 2238 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 2239 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) 2240 2241 /*define for DW_12 word*/ 2242 /*define for rect_x field*/ 2243 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 2244 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF 2245 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 2246 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) 2247 2248 /*define for rect_y field*/ 2249 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 2250 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF 2251 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 2252 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) 2253 2254 /*define for DW_13 word*/ 2255 /*define for rect_z field*/ 2256 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 2257 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x00001FFF 2258 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 2259 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) 2260 2261 /*define for linear_sw field*/ 2262 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 2263 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 2264 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 2265 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) 2266 2267 /*define for tile_sw field*/ 2268 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 2269 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 2270 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 2271 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) 2272 2273 /*define for META_ADDR_LO word*/ 2274 /*define for meta_addr_31_0 field*/ 2275 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset 14 2276 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF 2277 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift 0 2278 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift) 2279 2280 /*define for META_ADDR_HI word*/ 2281 /*define for meta_addr_63_32 field*/ 2282 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset 15 2283 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF 2284 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift 0 2285 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift) 2286 2287 /*define for META_CONFIG word*/ 2288 /*define for data_format field*/ 2289 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset 16 2290 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask 0x0000007F 2291 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift 0 2292 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift) 2293 2294 /*define for color_transform_disable field*/ 2295 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset 16 2296 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask 0x00000001 2297 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift 7 2298 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift) 2299 2300 /*define for alpha_is_on_msb field*/ 2301 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset 16 2302 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask 0x00000001 2303 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift 8 2304 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift) 2305 2306 /*define for number_type field*/ 2307 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset 16 2308 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask 0x00000007 2309 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift 9 2310 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift) 2311 2312 /*define for surface_type field*/ 2313 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset 16 2314 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask 0x00000003 2315 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift 12 2316 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift) 2317 2318 /*define for max_comp_block_size field*/ 2319 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset 16 2320 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask 0x00000003 2321 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift 24 2322 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift) 2323 2324 /*define for max_uncomp_block_size field*/ 2325 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset 16 2326 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask 0x00000003 2327 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift 26 2328 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift) 2329 2330 /*define for write_compress_enable field*/ 2331 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset 16 2332 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask 0x00000001 2333 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift 28 2334 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift) 2335 2336 /*define for meta_tmz field*/ 2337 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset 16 2338 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask 0x00000001 2339 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift 29 2340 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift) 2341 2342 2343 /* 2344 ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN_BC packet 2345 */ 2346 2347 /*define for HEADER word*/ 2348 /*define for op field*/ 2349 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset 0 2350 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask 0x000000FF 2351 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift 0 2352 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift) 2353 2354 /*define for sub_op field*/ 2355 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset 0 2356 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF 2357 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift 8 2358 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift) 2359 2360 /*define for detile field*/ 2361 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset 0 2362 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask 0x00000001 2363 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift 31 2364 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift) 2365 2366 /*define for TILED_ADDR_LO word*/ 2367 /*define for tiled_addr_31_0 field*/ 2368 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 2369 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 2370 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 2371 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) 2372 2373 /*define for TILED_ADDR_HI word*/ 2374 /*define for tiled_addr_63_32 field*/ 2375 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 2376 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 2377 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 2378 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) 2379 2380 /*define for DW_3 word*/ 2381 /*define for tiled_x field*/ 2382 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset 3 2383 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask 0x00003FFF 2384 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift 0 2385 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift) 2386 2387 /*define for tiled_y field*/ 2388 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset 3 2389 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask 0x00003FFF 2390 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift 16 2391 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift) 2392 2393 /*define for DW_4 word*/ 2394 /*define for tiled_z field*/ 2395 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset 4 2396 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask 0x000007FF 2397 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift 0 2398 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift) 2399 2400 /*define for width field*/ 2401 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset 4 2402 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask 0x00003FFF 2403 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift 16 2404 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift) 2405 2406 /*define for DW_5 word*/ 2407 /*define for height field*/ 2408 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset 5 2409 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask 0x00003FFF 2410 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift 0 2411 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift) 2412 2413 /*define for depth field*/ 2414 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset 5 2415 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask 0x000007FF 2416 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift 16 2417 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift) 2418 2419 /*define for DW_6 word*/ 2420 /*define for element_size field*/ 2421 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset 6 2422 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask 0x00000007 2423 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift 0 2424 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift) 2425 2426 /*define for array_mode field*/ 2427 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset 6 2428 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask 0x0000000F 2429 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift 3 2430 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift) 2431 2432 /*define for mit_mode field*/ 2433 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset 6 2434 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask 0x00000007 2435 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift 8 2436 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift) 2437 2438 /*define for tilesplit_size field*/ 2439 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset 6 2440 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask 0x00000007 2441 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift 11 2442 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift) 2443 2444 /*define for bank_w field*/ 2445 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset 6 2446 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask 0x00000003 2447 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift 15 2448 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift) 2449 2450 /*define for bank_h field*/ 2451 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset 6 2452 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask 0x00000003 2453 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift 18 2454 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift) 2455 2456 /*define for num_bank field*/ 2457 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset 6 2458 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask 0x00000003 2459 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift 21 2460 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift) 2461 2462 /*define for mat_aspt field*/ 2463 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset 6 2464 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask 0x00000003 2465 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift 24 2466 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x) ((x & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift) 2467 2468 /*define for pipe_config field*/ 2469 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset 6 2470 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask 0x0000001F 2471 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift 26 2472 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift) 2473 2474 /*define for LINEAR_ADDR_LO word*/ 2475 /*define for linear_addr_31_0 field*/ 2476 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 2477 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 2478 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 2479 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) 2480 2481 /*define for LINEAR_ADDR_HI word*/ 2482 /*define for linear_addr_63_32 field*/ 2483 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 2484 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 2485 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 2486 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) 2487 2488 /*define for DW_9 word*/ 2489 /*define for linear_x field*/ 2490 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset 9 2491 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask 0x00003FFF 2492 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift 0 2493 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift) 2494 2495 /*define for linear_y field*/ 2496 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset 9 2497 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask 0x00003FFF 2498 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift 16 2499 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift) 2500 2501 /*define for DW_10 word*/ 2502 /*define for linear_z field*/ 2503 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset 10 2504 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask 0x000007FF 2505 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift 0 2506 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift) 2507 2508 /*define for linear_pitch field*/ 2509 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset 10 2510 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask 0x00003FFF 2511 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift 16 2512 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift) 2513 2514 /*define for DW_11 word*/ 2515 /*define for linear_slice_pitch field*/ 2516 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset 11 2517 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask 0x0FFFFFFF 2518 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift 0 2519 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift) 2520 2521 /*define for DW_12 word*/ 2522 /*define for rect_x field*/ 2523 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset 12 2524 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask 0x00003FFF 2525 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift 0 2526 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift) 2527 2528 /*define for rect_y field*/ 2529 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset 12 2530 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask 0x00003FFF 2531 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift 16 2532 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift) 2533 2534 /*define for DW_13 word*/ 2535 /*define for rect_z field*/ 2536 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset 13 2537 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask 0x000007FF 2538 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift 0 2539 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift) 2540 2541 /*define for linear_sw field*/ 2542 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset 13 2543 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask 0x00000003 2544 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift 16 2545 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift) 2546 2547 /*define for tile_sw field*/ 2548 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset 13 2549 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask 0x00000003 2550 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift 24 2551 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift) 2552 2553 2554 /* 2555 ** Definitions for SDMA_PKT_COPY_STRUCT packet 2556 */ 2557 2558 /*define for HEADER word*/ 2559 /*define for op field*/ 2560 #define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 2561 #define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF 2562 #define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 2563 #define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) 2564 2565 /*define for sub_op field*/ 2566 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 2567 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF 2568 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 2569 #define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) 2570 2571 /*define for tmz field*/ 2572 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0 2573 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001 2574 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 18 2575 #define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) 2576 2577 /*define for detile field*/ 2578 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 2579 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 2580 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 2581 #define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) 2582 2583 /*define for SB_ADDR_LO word*/ 2584 /*define for sb_addr_31_0 field*/ 2585 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 2586 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF 2587 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 2588 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) 2589 2590 /*define for SB_ADDR_HI word*/ 2591 /*define for sb_addr_63_32 field*/ 2592 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 2593 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF 2594 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 2595 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) 2596 2597 /*define for START_INDEX word*/ 2598 /*define for start_index field*/ 2599 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 2600 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF 2601 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 2602 #define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) 2603 2604 /*define for COUNT word*/ 2605 /*define for count field*/ 2606 #define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 2607 #define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF 2608 #define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 2609 #define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) 2610 2611 /*define for DW_5 word*/ 2612 /*define for stride field*/ 2613 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 2614 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF 2615 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 2616 #define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) 2617 2618 /*define for linear_sw field*/ 2619 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 2620 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 2621 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 16 2622 #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) 2623 2624 /*define for struct_sw field*/ 2625 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 2626 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 2627 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 24 2628 #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) 2629 2630 /*define for LINEAR_ADDR_LO word*/ 2631 /*define for linear_addr_31_0 field*/ 2632 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 2633 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 2634 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 2635 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) 2636 2637 /*define for LINEAR_ADDR_HI word*/ 2638 /*define for linear_addr_63_32 field*/ 2639 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 2640 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 2641 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 2642 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) 2643 2644 2645 /* 2646 ** Definitions for SDMA_PKT_WRITE_UNTILED packet 2647 */ 2648 2649 /*define for HEADER word*/ 2650 /*define for op field*/ 2651 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 2652 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF 2653 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 2654 #define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) 2655 2656 /*define for sub_op field*/ 2657 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 2658 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF 2659 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 2660 #define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) 2661 2662 /*define for encrypt field*/ 2663 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0 2664 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001 2665 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 16 2666 #define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) 2667 2668 /*define for tmz field*/ 2669 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0 2670 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001 2671 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 18 2672 #define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) 2673 2674 /*define for DST_ADDR_LO word*/ 2675 /*define for dst_addr_31_0 field*/ 2676 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 2677 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 2678 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 2679 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) 2680 2681 /*define for DST_ADDR_HI word*/ 2682 /*define for dst_addr_63_32 field*/ 2683 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 2684 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 2685 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 2686 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) 2687 2688 /*define for DW_3 word*/ 2689 /*define for count field*/ 2690 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 2691 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF 2692 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 2693 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) 2694 2695 /*define for sw field*/ 2696 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 2697 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 2698 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 2699 #define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) 2700 2701 /*define for DATA0 word*/ 2702 /*define for data0 field*/ 2703 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 2704 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF 2705 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 2706 #define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) 2707 2708 2709 /* 2710 ** Definitions for SDMA_PKT_WRITE_TILED packet 2711 */ 2712 2713 /*define for HEADER word*/ 2714 /*define for op field*/ 2715 #define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 2716 #define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF 2717 #define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 2718 #define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) 2719 2720 /*define for sub_op field*/ 2721 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 2722 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF 2723 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 2724 #define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) 2725 2726 /*define for encrypt field*/ 2727 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0 2728 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001 2729 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 16 2730 #define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) 2731 2732 /*define for tmz field*/ 2733 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0 2734 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001 2735 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 18 2736 #define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) 2737 2738 /*define for DST_ADDR_LO word*/ 2739 /*define for dst_addr_31_0 field*/ 2740 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 2741 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 2742 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 2743 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) 2744 2745 /*define for DST_ADDR_HI word*/ 2746 /*define for dst_addr_63_32 field*/ 2747 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 2748 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 2749 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 2750 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) 2751 2752 /*define for DW_3 word*/ 2753 /*define for width field*/ 2754 #define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3 2755 #define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF 2756 #define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0 2757 #define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) 2758 2759 /*define for DW_4 word*/ 2760 /*define for height field*/ 2761 #define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4 2762 #define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF 2763 #define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0 2764 #define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) 2765 2766 /*define for depth field*/ 2767 #define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4 2768 #define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x00001FFF 2769 #define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 16 2770 #define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) 2771 2772 /*define for DW_5 word*/ 2773 /*define for element_size field*/ 2774 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 2775 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 2776 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 2777 #define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) 2778 2779 /*define for swizzle_mode field*/ 2780 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5 2781 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F 2782 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 3 2783 #define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) 2784 2785 /*define for dimension field*/ 2786 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5 2787 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003 2788 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 9 2789 #define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) 2790 2791 /*define for mip_max field*/ 2792 #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset 5 2793 #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask 0x0000000F 2794 #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift 16 2795 #define SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask) << SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift) 2796 2797 /*define for DW_6 word*/ 2798 /*define for x field*/ 2799 #define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 2800 #define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF 2801 #define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 2802 #define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) 2803 2804 /*define for y field*/ 2805 #define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 2806 #define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF 2807 #define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 2808 #define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) 2809 2810 /*define for DW_7 word*/ 2811 /*define for z field*/ 2812 #define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 2813 #define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00001FFF 2814 #define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 2815 #define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) 2816 2817 /*define for sw field*/ 2818 #define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 2819 #define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 2820 #define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 2821 #define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) 2822 2823 /*define for COUNT word*/ 2824 /*define for count field*/ 2825 #define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 2826 #define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF 2827 #define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 2828 #define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) 2829 2830 /*define for DATA0 word*/ 2831 /*define for data0 field*/ 2832 #define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 2833 #define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF 2834 #define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 2835 #define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) 2836 2837 2838 /* 2839 ** Definitions for SDMA_PKT_WRITE_TILED_BC packet 2840 */ 2841 2842 /*define for HEADER word*/ 2843 /*define for op field*/ 2844 #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset 0 2845 #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask 0x000000FF 2846 #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift 0 2847 #define SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift) 2848 2849 /*define for sub_op field*/ 2850 #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset 0 2851 #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask 0x000000FF 2852 #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift 8 2853 #define SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift) 2854 2855 /*define for DST_ADDR_LO word*/ 2856 /*define for dst_addr_31_0 field*/ 2857 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset 1 2858 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 2859 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 2860 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift) 2861 2862 /*define for DST_ADDR_HI word*/ 2863 /*define for dst_addr_63_32 field*/ 2864 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset 2 2865 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 2866 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 2867 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift) 2868 2869 /*define for DW_3 word*/ 2870 /*define for width field*/ 2871 #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset 3 2872 #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask 0x00003FFF 2873 #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift 0 2874 #define SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift) 2875 2876 /*define for DW_4 word*/ 2877 /*define for height field*/ 2878 #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset 4 2879 #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask 0x00003FFF 2880 #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift 0 2881 #define SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift) 2882 2883 /*define for depth field*/ 2884 #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset 4 2885 #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask 0x000007FF 2886 #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift 16 2887 #define SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift) 2888 2889 /*define for DW_5 word*/ 2890 /*define for element_size field*/ 2891 #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset 5 2892 #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask 0x00000007 2893 #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift 0 2894 #define SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift) 2895 2896 /*define for array_mode field*/ 2897 #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset 5 2898 #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask 0x0000000F 2899 #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift 3 2900 #define SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift) 2901 2902 /*define for mit_mode field*/ 2903 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset 5 2904 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask 0x00000007 2905 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift 8 2906 #define SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift) 2907 2908 /*define for tilesplit_size field*/ 2909 #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset 5 2910 #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 2911 #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift 11 2912 #define SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift) 2913 2914 /*define for bank_w field*/ 2915 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset 5 2916 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask 0x00000003 2917 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift 15 2918 #define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift) 2919 2920 /*define for bank_h field*/ 2921 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset 5 2922 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask 0x00000003 2923 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift 18 2924 #define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift) 2925 2926 /*define for num_bank field*/ 2927 #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset 5 2928 #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask 0x00000003 2929 #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift 21 2930 #define SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift) 2931 2932 /*define for mat_aspt field*/ 2933 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset 5 2934 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask 0x00000003 2935 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift 24 2936 #define SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift) 2937 2938 /*define for pipe_config field*/ 2939 #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset 5 2940 #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask 0x0000001F 2941 #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift 26 2942 #define SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift) 2943 2944 /*define for DW_6 word*/ 2945 /*define for x field*/ 2946 #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset 6 2947 #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask 0x00003FFF 2948 #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift 0 2949 #define SDMA_PKT_WRITE_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift) 2950 2951 /*define for y field*/ 2952 #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset 6 2953 #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask 0x00003FFF 2954 #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift 16 2955 #define SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift) 2956 2957 /*define for DW_7 word*/ 2958 /*define for z field*/ 2959 #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset 7 2960 #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask 0x000007FF 2961 #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift 0 2962 #define SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift) 2963 2964 /*define for sw field*/ 2965 #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset 7 2966 #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask 0x00000003 2967 #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift 24 2968 #define SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift) 2969 2970 /*define for COUNT word*/ 2971 /*define for count field*/ 2972 #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset 8 2973 #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask 0x000FFFFF 2974 #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift 2 2975 #define SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift) 2976 2977 /*define for DATA0 word*/ 2978 /*define for data0 field*/ 2979 #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset 9 2980 #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask 0xFFFFFFFF 2981 #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift 0 2982 #define SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift) 2983 2984 2985 /* 2986 ** Definitions for SDMA_PKT_PTEPDE_COPY packet 2987 */ 2988 2989 /*define for HEADER word*/ 2990 /*define for op field*/ 2991 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0 2992 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF 2993 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0 2994 #define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) 2995 2996 /*define for sub_op field*/ 2997 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0 2998 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF 2999 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 8 3000 #define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) 3001 3002 /*define for tmz field*/ 3003 #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset 0 3004 #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask 0x00000001 3005 #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift 18 3006 #define SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift) 3007 3008 /*define for ptepde_op field*/ 3009 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0 3010 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x00000001 3011 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 31 3012 #define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) 3013 3014 /*define for SRC_ADDR_LO word*/ 3015 /*define for src_addr_31_0 field*/ 3016 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1 3017 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 3018 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0 3019 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) 3020 3021 /*define for SRC_ADDR_HI word*/ 3022 /*define for src_addr_63_32 field*/ 3023 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2 3024 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 3025 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0 3026 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) 3027 3028 /*define for DST_ADDR_LO word*/ 3029 /*define for dst_addr_31_0 field*/ 3030 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3 3031 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3032 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0 3033 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) 3034 3035 /*define for DST_ADDR_HI word*/ 3036 /*define for dst_addr_63_32 field*/ 3037 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4 3038 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3039 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0 3040 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) 3041 3042 /*define for MASK_DW0 word*/ 3043 /*define for mask_dw0 field*/ 3044 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5 3045 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 3046 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0 3047 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) 3048 3049 /*define for MASK_DW1 word*/ 3050 /*define for mask_dw1 field*/ 3051 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6 3052 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 3053 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0 3054 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) 3055 3056 /*define for COUNT word*/ 3057 /*define for count field*/ 3058 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7 3059 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF 3060 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0 3061 #define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) 3062 3063 3064 /* 3065 ** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet 3066 */ 3067 3068 /*define for HEADER word*/ 3069 /*define for op field*/ 3070 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0 3071 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF 3072 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0 3073 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) 3074 3075 /*define for sub_op field*/ 3076 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0 3077 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF 3078 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 8 3079 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) 3080 3081 /*define for pte_size field*/ 3082 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0 3083 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003 3084 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 28 3085 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) 3086 3087 /*define for direction field*/ 3088 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0 3089 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001 3090 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 30 3091 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) 3092 3093 /*define for ptepde_op field*/ 3094 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0 3095 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001 3096 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 31 3097 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) 3098 3099 /*define for SRC_ADDR_LO word*/ 3100 /*define for src_addr_31_0 field*/ 3101 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1 3102 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 3103 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0 3104 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) 3105 3106 /*define for SRC_ADDR_HI word*/ 3107 /*define for src_addr_63_32 field*/ 3108 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2 3109 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 3110 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0 3111 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) 3112 3113 /*define for DST_ADDR_LO word*/ 3114 /*define for dst_addr_31_0 field*/ 3115 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3 3116 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3117 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0 3118 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) 3119 3120 /*define for DST_ADDR_HI word*/ 3121 /*define for dst_addr_63_32 field*/ 3122 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4 3123 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3124 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0 3125 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) 3126 3127 /*define for MASK_BIT_FOR_DW word*/ 3128 /*define for mask_first_xfer field*/ 3129 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5 3130 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF 3131 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0 3132 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) 3133 3134 /*define for mask_last_xfer field*/ 3135 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5 3136 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF 3137 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 8 3138 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) 3139 3140 /*define for COUNT_IN_32B_XFER word*/ 3141 /*define for count field*/ 3142 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6 3143 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF 3144 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0 3145 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) 3146 3147 3148 /* 3149 ** Definitions for SDMA_PKT_PTEPDE_RMW packet 3150 */ 3151 3152 /*define for HEADER word*/ 3153 /*define for op field*/ 3154 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0 3155 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF 3156 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0 3157 #define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) 3158 3159 /*define for sub_op field*/ 3160 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0 3161 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF 3162 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 8 3163 #define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) 3164 3165 /*define for mtype field*/ 3166 #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset 0 3167 #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask 0x00000007 3168 #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift 16 3169 #define SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift) 3170 3171 /*define for gcc field*/ 3172 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0 3173 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001 3174 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 19 3175 #define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) 3176 3177 /*define for sys field*/ 3178 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0 3179 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001 3180 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 20 3181 #define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) 3182 3183 /*define for snp field*/ 3184 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0 3185 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001 3186 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 22 3187 #define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) 3188 3189 /*define for gpa field*/ 3190 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0 3191 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001 3192 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 23 3193 #define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) 3194 3195 /*define for l2_policy field*/ 3196 #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset 0 3197 #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask 0x00000003 3198 #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift 24 3199 #define SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift) 3200 3201 /*define for ADDR_LO word*/ 3202 /*define for addr_31_0 field*/ 3203 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1 3204 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3205 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0 3206 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) 3207 3208 /*define for ADDR_HI word*/ 3209 /*define for addr_63_32 field*/ 3210 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2 3211 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3212 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0 3213 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) 3214 3215 /*define for MASK_LO word*/ 3216 /*define for mask_31_0 field*/ 3217 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3 3218 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF 3219 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0 3220 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) 3221 3222 /*define for MASK_HI word*/ 3223 /*define for mask_63_32 field*/ 3224 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4 3225 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF 3226 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0 3227 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) 3228 3229 /*define for VALUE_LO word*/ 3230 /*define for value_31_0 field*/ 3231 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5 3232 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF 3233 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0 3234 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) 3235 3236 /*define for VALUE_HI word*/ 3237 /*define for value_63_32 field*/ 3238 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6 3239 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF 3240 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0 3241 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) 3242 3243 3244 /* 3245 ** Definitions for SDMA_PKT_WRITE_INCR packet 3246 */ 3247 3248 /*define for HEADER word*/ 3249 /*define for op field*/ 3250 #define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 3251 #define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF 3252 #define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 3253 #define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) 3254 3255 /*define for sub_op field*/ 3256 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 3257 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF 3258 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 3259 #define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) 3260 3261 /*define for DST_ADDR_LO word*/ 3262 /*define for dst_addr_31_0 field*/ 3263 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 3264 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3265 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 3266 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) 3267 3268 /*define for DST_ADDR_HI word*/ 3269 /*define for dst_addr_63_32 field*/ 3270 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 3271 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3272 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 3273 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) 3274 3275 /*define for MASK_DW0 word*/ 3276 /*define for mask_dw0 field*/ 3277 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 3278 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 3279 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 3280 #define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) 3281 3282 /*define for MASK_DW1 word*/ 3283 /*define for mask_dw1 field*/ 3284 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 3285 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 3286 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 3287 #define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) 3288 3289 /*define for INIT_DW0 word*/ 3290 /*define for init_dw0 field*/ 3291 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 3292 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF 3293 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 3294 #define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) 3295 3296 /*define for INIT_DW1 word*/ 3297 /*define for init_dw1 field*/ 3298 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 3299 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF 3300 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 3301 #define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) 3302 3303 /*define for INCR_DW0 word*/ 3304 /*define for incr_dw0 field*/ 3305 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 3306 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF 3307 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 3308 #define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) 3309 3310 /*define for INCR_DW1 word*/ 3311 /*define for incr_dw1 field*/ 3312 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 3313 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF 3314 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 3315 #define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) 3316 3317 /*define for COUNT word*/ 3318 /*define for count field*/ 3319 #define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 3320 #define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF 3321 #define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 3322 #define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) 3323 3324 3325 /* 3326 ** Definitions for SDMA_PKT_INDIRECT packet 3327 */ 3328 3329 /*define for HEADER word*/ 3330 /*define for op field*/ 3331 #define SDMA_PKT_INDIRECT_HEADER_op_offset 0 3332 #define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF 3333 #define SDMA_PKT_INDIRECT_HEADER_op_shift 0 3334 #define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) 3335 3336 /*define for sub_op field*/ 3337 #define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 3338 #define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF 3339 #define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 3340 #define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) 3341 3342 /*define for vmid field*/ 3343 #define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 3344 #define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F 3345 #define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 3346 #define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) 3347 3348 /*define for priv field*/ 3349 #define SDMA_PKT_INDIRECT_HEADER_priv_offset 0 3350 #define SDMA_PKT_INDIRECT_HEADER_priv_mask 0x00000001 3351 #define SDMA_PKT_INDIRECT_HEADER_priv_shift 31 3352 #define SDMA_PKT_INDIRECT_HEADER_PRIV(x) (((x) & SDMA_PKT_INDIRECT_HEADER_priv_mask) << SDMA_PKT_INDIRECT_HEADER_priv_shift) 3353 3354 /*define for BASE_LO word*/ 3355 /*define for ib_base_31_0 field*/ 3356 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 3357 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF 3358 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 3359 #define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) 3360 3361 /*define for BASE_HI word*/ 3362 /*define for ib_base_63_32 field*/ 3363 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 3364 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF 3365 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 3366 #define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) 3367 3368 /*define for IB_SIZE word*/ 3369 /*define for ib_size field*/ 3370 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 3371 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF 3372 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 3373 #define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) 3374 3375 /*define for CSA_ADDR_LO word*/ 3376 /*define for csa_addr_31_0 field*/ 3377 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 3378 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF 3379 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 3380 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) 3381 3382 /*define for CSA_ADDR_HI word*/ 3383 /*define for csa_addr_63_32 field*/ 3384 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 3385 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF 3386 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 3387 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) 3388 3389 3390 /* 3391 ** Definitions for SDMA_PKT_SEMAPHORE packet 3392 */ 3393 3394 /*define for HEADER word*/ 3395 /*define for op field*/ 3396 #define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 3397 #define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF 3398 #define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 3399 #define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) 3400 3401 /*define for sub_op field*/ 3402 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 3403 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF 3404 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 3405 #define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) 3406 3407 /*define for write_one field*/ 3408 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 3409 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 3410 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 3411 #define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) 3412 3413 /*define for signal field*/ 3414 #define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 3415 #define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 3416 #define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 3417 #define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) 3418 3419 /*define for mailbox field*/ 3420 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 3421 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 3422 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 3423 #define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) 3424 3425 /*define for ADDR_LO word*/ 3426 /*define for addr_31_0 field*/ 3427 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 3428 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3429 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 3430 #define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) 3431 3432 /*define for ADDR_HI word*/ 3433 /*define for addr_63_32 field*/ 3434 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 3435 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3436 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 3437 #define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) 3438 3439 3440 /* 3441 ** Definitions for SDMA_PKT_FENCE packet 3442 */ 3443 3444 /*define for HEADER word*/ 3445 /*define for op field*/ 3446 #define SDMA_PKT_FENCE_HEADER_op_offset 0 3447 #define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF 3448 #define SDMA_PKT_FENCE_HEADER_op_shift 0 3449 #define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) 3450 3451 /*define for sub_op field*/ 3452 #define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 3453 #define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF 3454 #define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 3455 #define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) 3456 3457 /*define for mtype field*/ 3458 #define SDMA_PKT_FENCE_HEADER_mtype_offset 0 3459 #define SDMA_PKT_FENCE_HEADER_mtype_mask 0x00000007 3460 #define SDMA_PKT_FENCE_HEADER_mtype_shift 16 3461 #define SDMA_PKT_FENCE_HEADER_MTYPE(x) (((x) & SDMA_PKT_FENCE_HEADER_mtype_mask) << SDMA_PKT_FENCE_HEADER_mtype_shift) 3462 3463 /*define for gcc field*/ 3464 #define SDMA_PKT_FENCE_HEADER_gcc_offset 0 3465 #define SDMA_PKT_FENCE_HEADER_gcc_mask 0x00000001 3466 #define SDMA_PKT_FENCE_HEADER_gcc_shift 19 3467 #define SDMA_PKT_FENCE_HEADER_GCC(x) (((x) & SDMA_PKT_FENCE_HEADER_gcc_mask) << SDMA_PKT_FENCE_HEADER_gcc_shift) 3468 3469 /*define for sys field*/ 3470 #define SDMA_PKT_FENCE_HEADER_sys_offset 0 3471 #define SDMA_PKT_FENCE_HEADER_sys_mask 0x00000001 3472 #define SDMA_PKT_FENCE_HEADER_sys_shift 20 3473 #define SDMA_PKT_FENCE_HEADER_SYS(x) (((x) & SDMA_PKT_FENCE_HEADER_sys_mask) << SDMA_PKT_FENCE_HEADER_sys_shift) 3474 3475 /*define for snp field*/ 3476 #define SDMA_PKT_FENCE_HEADER_snp_offset 0 3477 #define SDMA_PKT_FENCE_HEADER_snp_mask 0x00000001 3478 #define SDMA_PKT_FENCE_HEADER_snp_shift 22 3479 #define SDMA_PKT_FENCE_HEADER_SNP(x) (((x) & SDMA_PKT_FENCE_HEADER_snp_mask) << SDMA_PKT_FENCE_HEADER_snp_shift) 3480 3481 /*define for gpa field*/ 3482 #define SDMA_PKT_FENCE_HEADER_gpa_offset 0 3483 #define SDMA_PKT_FENCE_HEADER_gpa_mask 0x00000001 3484 #define SDMA_PKT_FENCE_HEADER_gpa_shift 23 3485 #define SDMA_PKT_FENCE_HEADER_GPA(x) (((x) & SDMA_PKT_FENCE_HEADER_gpa_mask) << SDMA_PKT_FENCE_HEADER_gpa_shift) 3486 3487 /*define for l2_policy field*/ 3488 #define SDMA_PKT_FENCE_HEADER_l2_policy_offset 0 3489 #define SDMA_PKT_FENCE_HEADER_l2_policy_mask 0x00000003 3490 #define SDMA_PKT_FENCE_HEADER_l2_policy_shift 24 3491 #define SDMA_PKT_FENCE_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_l2_policy_mask) << SDMA_PKT_FENCE_HEADER_l2_policy_shift) 3492 3493 /*define for ADDR_LO word*/ 3494 /*define for addr_31_0 field*/ 3495 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 3496 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3497 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 3498 #define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) 3499 3500 /*define for ADDR_HI word*/ 3501 /*define for addr_63_32 field*/ 3502 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 3503 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3504 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 3505 #define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) 3506 3507 /*define for DATA word*/ 3508 /*define for data field*/ 3509 #define SDMA_PKT_FENCE_DATA_data_offset 3 3510 #define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF 3511 #define SDMA_PKT_FENCE_DATA_data_shift 0 3512 #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) 3513 3514 3515 /* 3516 ** Definitions for SDMA_PKT_SRBM_WRITE packet 3517 */ 3518 3519 /*define for HEADER word*/ 3520 /*define for op field*/ 3521 #define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 3522 #define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF 3523 #define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 3524 #define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) 3525 3526 /*define for sub_op field*/ 3527 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 3528 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF 3529 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 3530 #define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) 3531 3532 /*define for byte_en field*/ 3533 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 3534 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F 3535 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 3536 #define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) 3537 3538 /*define for ADDR word*/ 3539 /*define for addr field*/ 3540 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 3541 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF 3542 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 3543 #define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) 3544 3545 /*define for apertureid field*/ 3546 #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset 1 3547 #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask 0x00000FFF 3548 #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift 20 3549 #define SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask) << SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift) 3550 3551 /*define for DATA word*/ 3552 /*define for data field*/ 3553 #define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 3554 #define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF 3555 #define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 3556 #define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) 3557 3558 3559 /* 3560 ** Definitions for SDMA_PKT_PRE_EXE packet 3561 */ 3562 3563 /*define for HEADER word*/ 3564 /*define for op field*/ 3565 #define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 3566 #define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF 3567 #define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 3568 #define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) 3569 3570 /*define for sub_op field*/ 3571 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 3572 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF 3573 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 3574 #define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) 3575 3576 /*define for dev_sel field*/ 3577 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 3578 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF 3579 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 3580 #define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) 3581 3582 /*define for EXEC_COUNT word*/ 3583 /*define for exec_count field*/ 3584 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 3585 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 3586 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 3587 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) 3588 3589 3590 /* 3591 ** Definitions for SDMA_PKT_COND_EXE packet 3592 */ 3593 3594 /*define for HEADER word*/ 3595 /*define for op field*/ 3596 #define SDMA_PKT_COND_EXE_HEADER_op_offset 0 3597 #define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF 3598 #define SDMA_PKT_COND_EXE_HEADER_op_shift 0 3599 #define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) 3600 3601 /*define for sub_op field*/ 3602 #define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 3603 #define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF 3604 #define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 3605 #define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) 3606 3607 /*define for ADDR_LO word*/ 3608 /*define for addr_31_0 field*/ 3609 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 3610 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3611 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 3612 #define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) 3613 3614 /*define for ADDR_HI word*/ 3615 /*define for addr_63_32 field*/ 3616 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 3617 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3618 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 3619 #define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) 3620 3621 /*define for REFERENCE word*/ 3622 /*define for reference field*/ 3623 #define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 3624 #define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF 3625 #define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 3626 #define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) 3627 3628 /*define for EXEC_COUNT word*/ 3629 /*define for exec_count field*/ 3630 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 3631 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 3632 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 3633 #define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) 3634 3635 3636 /* 3637 ** Definitions for SDMA_PKT_CONSTANT_FILL packet 3638 */ 3639 3640 /*define for HEADER word*/ 3641 /*define for op field*/ 3642 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 3643 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF 3644 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 3645 #define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) 3646 3647 /*define for sub_op field*/ 3648 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 3649 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF 3650 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 3651 #define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) 3652 3653 /*define for sw field*/ 3654 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 3655 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 3656 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 3657 #define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) 3658 3659 /*define for fillsize field*/ 3660 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 3661 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 3662 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 3663 #define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) 3664 3665 /*define for DST_ADDR_LO word*/ 3666 /*define for dst_addr_31_0 field*/ 3667 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 3668 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3669 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 3670 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) 3671 3672 /*define for DST_ADDR_HI word*/ 3673 /*define for dst_addr_63_32 field*/ 3674 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 3675 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3676 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 3677 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) 3678 3679 /*define for DATA word*/ 3680 /*define for src_data_31_0 field*/ 3681 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 3682 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF 3683 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 3684 #define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) 3685 3686 /*define for COUNT word*/ 3687 /*define for count field*/ 3688 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 3689 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF 3690 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 3691 #define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) 3692 3693 3694 /* 3695 ** Definitions for SDMA_PKT_DATA_FILL_MULTI packet 3696 */ 3697 3698 /*define for HEADER word*/ 3699 /*define for op field*/ 3700 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0 3701 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF 3702 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0 3703 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) 3704 3705 /*define for sub_op field*/ 3706 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0 3707 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF 3708 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 8 3709 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) 3710 3711 /*define for memlog_clr field*/ 3712 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0 3713 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001 3714 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 31 3715 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) 3716 3717 /*define for BYTE_STRIDE word*/ 3718 /*define for byte_stride field*/ 3719 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1 3720 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF 3721 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0 3722 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) 3723 3724 /*define for DMA_COUNT word*/ 3725 /*define for dma_count field*/ 3726 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2 3727 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF 3728 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0 3729 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) 3730 3731 /*define for DST_ADDR_LO word*/ 3732 /*define for dst_addr_31_0 field*/ 3733 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3 3734 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3735 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0 3736 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) 3737 3738 /*define for DST_ADDR_HI word*/ 3739 /*define for dst_addr_63_32 field*/ 3740 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4 3741 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3742 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0 3743 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) 3744 3745 /*define for BYTE_COUNT word*/ 3746 /*define for count field*/ 3747 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5 3748 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF 3749 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0 3750 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) 3751 3752 3753 /* 3754 ** Definitions for SDMA_PKT_POLL_REGMEM packet 3755 */ 3756 3757 /*define for HEADER word*/ 3758 /*define for op field*/ 3759 #define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 3760 #define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF 3761 #define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 3762 #define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) 3763 3764 /*define for sub_op field*/ 3765 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 3766 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF 3767 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 3768 #define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) 3769 3770 /*define for hdp_flush field*/ 3771 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 3772 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 3773 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 3774 #define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) 3775 3776 /*define for func field*/ 3777 #define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 3778 #define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 3779 #define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 3780 #define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) 3781 3782 /*define for mem_poll field*/ 3783 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 3784 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 3785 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 3786 #define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) 3787 3788 /*define for ADDR_LO word*/ 3789 /*define for addr_31_0 field*/ 3790 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 3791 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3792 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 3793 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) 3794 3795 /*define for ADDR_HI word*/ 3796 /*define for addr_63_32 field*/ 3797 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 3798 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3799 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 3800 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) 3801 3802 /*define for VALUE word*/ 3803 /*define for value field*/ 3804 #define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 3805 #define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF 3806 #define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 3807 #define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) 3808 3809 /*define for MASK word*/ 3810 /*define for mask field*/ 3811 #define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 3812 #define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF 3813 #define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 3814 #define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) 3815 3816 /*define for DW5 word*/ 3817 /*define for interval field*/ 3818 #define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 3819 #define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF 3820 #define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 3821 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) 3822 3823 /*define for retry_count field*/ 3824 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 3825 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF 3826 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 3827 #define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) 3828 3829 3830 /* 3831 ** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet 3832 */ 3833 3834 /*define for HEADER word*/ 3835 /*define for op field*/ 3836 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0 3837 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF 3838 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0 3839 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) 3840 3841 /*define for sub_op field*/ 3842 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0 3843 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF 3844 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 8 3845 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) 3846 3847 /*define for SRC_ADDR word*/ 3848 /*define for addr_31_2 field*/ 3849 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1 3850 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF 3851 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 2 3852 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) 3853 3854 /*define for DST_ADDR_LO word*/ 3855 /*define for addr_31_0 field*/ 3856 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2 3857 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3858 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 3859 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) 3860 3861 /*define for DST_ADDR_HI word*/ 3862 /*define for addr_63_32 field*/ 3863 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3 3864 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3865 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 3866 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) 3867 3868 3869 /* 3870 ** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet 3871 */ 3872 3873 /*define for HEADER word*/ 3874 /*define for op field*/ 3875 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0 3876 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF 3877 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0 3878 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) 3879 3880 /*define for sub_op field*/ 3881 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0 3882 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF 3883 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 8 3884 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) 3885 3886 /*define for ea field*/ 3887 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0 3888 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003 3889 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 16 3890 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) 3891 3892 /*define for DST_ADDR_LO word*/ 3893 /*define for addr_31_0 field*/ 3894 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1 3895 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3896 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 3897 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) 3898 3899 /*define for DST_ADDR_HI word*/ 3900 /*define for addr_63_32 field*/ 3901 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2 3902 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3903 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 3904 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) 3905 3906 /*define for START_PAGE word*/ 3907 /*define for addr_31_4 field*/ 3908 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3 3909 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF 3910 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 4 3911 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) 3912 3913 /*define for PAGE_NUM word*/ 3914 /*define for page_num_31_0 field*/ 3915 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4 3916 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF 3917 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0 3918 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) 3919 3920 3921 /* 3922 ** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet 3923 */ 3924 3925 /*define for HEADER word*/ 3926 /*define for op field*/ 3927 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0 3928 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF 3929 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0 3930 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) 3931 3932 /*define for sub_op field*/ 3933 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0 3934 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF 3935 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 8 3936 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) 3937 3938 /*define for mode field*/ 3939 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0 3940 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001 3941 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 31 3942 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) 3943 3944 /*define for PATTERN word*/ 3945 /*define for pattern field*/ 3946 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1 3947 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF 3948 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0 3949 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) 3950 3951 /*define for CMP0_ADDR_START_LO word*/ 3952 /*define for cmp0_start_31_0 field*/ 3953 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2 3954 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF 3955 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0 3956 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) 3957 3958 /*define for CMP0_ADDR_START_HI word*/ 3959 /*define for cmp0_start_63_32 field*/ 3960 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3 3961 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF 3962 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0 3963 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) 3964 3965 /*define for CMP0_ADDR_END_LO word*/ 3966 /*define for cmp1_end_31_0 field*/ 3967 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset 4 3968 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF 3969 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift 0 3970 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift) 3971 3972 /*define for CMP0_ADDR_END_HI word*/ 3973 /*define for cmp1_end_63_32 field*/ 3974 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset 5 3975 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF 3976 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift 0 3977 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift) 3978 3979 /*define for CMP1_ADDR_START_LO word*/ 3980 /*define for cmp1_start_31_0 field*/ 3981 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6 3982 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF 3983 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0 3984 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) 3985 3986 /*define for CMP1_ADDR_START_HI word*/ 3987 /*define for cmp1_start_63_32 field*/ 3988 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7 3989 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF 3990 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0 3991 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) 3992 3993 /*define for CMP1_ADDR_END_LO word*/ 3994 /*define for cmp1_end_31_0 field*/ 3995 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8 3996 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF 3997 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0 3998 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) 3999 4000 /*define for CMP1_ADDR_END_HI word*/ 4001 /*define for cmp1_end_63_32 field*/ 4002 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9 4003 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF 4004 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0 4005 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) 4006 4007 /*define for REC_ADDR_LO word*/ 4008 /*define for rec_31_0 field*/ 4009 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10 4010 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF 4011 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0 4012 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) 4013 4014 /*define for REC_ADDR_HI word*/ 4015 /*define for rec_63_32 field*/ 4016 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11 4017 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF 4018 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0 4019 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) 4020 4021 /*define for RESERVED word*/ 4022 /*define for reserved field*/ 4023 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12 4024 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF 4025 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0 4026 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) 4027 4028 4029 /* 4030 ** Definitions for SDMA_PKT_ATOMIC packet 4031 */ 4032 4033 /*define for HEADER word*/ 4034 /*define for op field*/ 4035 #define SDMA_PKT_ATOMIC_HEADER_op_offset 0 4036 #define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF 4037 #define SDMA_PKT_ATOMIC_HEADER_op_shift 0 4038 #define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) 4039 4040 /*define for loop field*/ 4041 #define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 4042 #define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 4043 #define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 4044 #define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) 4045 4046 /*define for tmz field*/ 4047 #define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0 4048 #define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001 4049 #define SDMA_PKT_ATOMIC_HEADER_tmz_shift 18 4050 #define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) 4051 4052 /*define for atomic_op field*/ 4053 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 4054 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F 4055 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 4056 #define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) 4057 4058 /*define for ADDR_LO word*/ 4059 /*define for addr_31_0 field*/ 4060 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 4061 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4062 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 4063 #define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) 4064 4065 /*define for ADDR_HI word*/ 4066 /*define for addr_63_32 field*/ 4067 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 4068 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4069 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 4070 #define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) 4071 4072 /*define for SRC_DATA_LO word*/ 4073 /*define for src_data_31_0 field*/ 4074 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 4075 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF 4076 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 4077 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) 4078 4079 /*define for SRC_DATA_HI word*/ 4080 /*define for src_data_63_32 field*/ 4081 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 4082 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF 4083 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 4084 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) 4085 4086 /*define for CMP_DATA_LO word*/ 4087 /*define for cmp_data_31_0 field*/ 4088 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 4089 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF 4090 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 4091 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) 4092 4093 /*define for CMP_DATA_HI word*/ 4094 /*define for cmp_data_63_32 field*/ 4095 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 4096 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF 4097 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 4098 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) 4099 4100 /*define for LOOP_INTERVAL word*/ 4101 /*define for loop_interval field*/ 4102 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 4103 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF 4104 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 4105 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) 4106 4107 4108 /* 4109 ** Definitions for SDMA_PKT_TIMESTAMP_SET packet 4110 */ 4111 4112 /*define for HEADER word*/ 4113 /*define for op field*/ 4114 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 4115 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF 4116 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 4117 #define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) 4118 4119 /*define for sub_op field*/ 4120 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 4121 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF 4122 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 4123 #define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) 4124 4125 /*define for INIT_DATA_LO word*/ 4126 /*define for init_data_31_0 field*/ 4127 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 4128 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF 4129 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 4130 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) 4131 4132 /*define for INIT_DATA_HI word*/ 4133 /*define for init_data_63_32 field*/ 4134 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 4135 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF 4136 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 4137 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) 4138 4139 4140 /* 4141 ** Definitions for SDMA_PKT_TIMESTAMP_GET packet 4142 */ 4143 4144 /*define for HEADER word*/ 4145 /*define for op field*/ 4146 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 4147 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF 4148 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 4149 #define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) 4150 4151 /*define for sub_op field*/ 4152 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 4153 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF 4154 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 4155 #define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) 4156 4157 /*define for WRITE_ADDR_LO word*/ 4158 /*define for write_addr_31_3 field*/ 4159 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 4160 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 4161 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 4162 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) 4163 4164 /*define for WRITE_ADDR_HI word*/ 4165 /*define for write_addr_63_32 field*/ 4166 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 4167 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 4168 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 4169 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) 4170 4171 4172 /* 4173 ** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet 4174 */ 4175 4176 /*define for HEADER word*/ 4177 /*define for op field*/ 4178 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 4179 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF 4180 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 4181 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) 4182 4183 /*define for sub_op field*/ 4184 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 4185 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF 4186 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 4187 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) 4188 4189 /*define for WRITE_ADDR_LO word*/ 4190 /*define for write_addr_31_3 field*/ 4191 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 4192 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 4193 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 4194 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) 4195 4196 /*define for WRITE_ADDR_HI word*/ 4197 /*define for write_addr_63_32 field*/ 4198 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 4199 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 4200 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 4201 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) 4202 4203 4204 /* 4205 ** Definitions for SDMA_PKT_TRAP packet 4206 */ 4207 4208 /*define for HEADER word*/ 4209 /*define for op field*/ 4210 #define SDMA_PKT_TRAP_HEADER_op_offset 0 4211 #define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF 4212 #define SDMA_PKT_TRAP_HEADER_op_shift 0 4213 #define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) 4214 4215 /*define for sub_op field*/ 4216 #define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 4217 #define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF 4218 #define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 4219 #define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) 4220 4221 /*define for INT_CONTEXT word*/ 4222 /*define for int_context field*/ 4223 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 4224 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 4225 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 4226 #define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) 4227 4228 4229 /* 4230 ** Definitions for SDMA_PKT_DUMMY_TRAP packet 4231 */ 4232 4233 /*define for HEADER word*/ 4234 /*define for op field*/ 4235 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0 4236 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF 4237 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0 4238 #define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) 4239 4240 /*define for sub_op field*/ 4241 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0 4242 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF 4243 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 8 4244 #define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) 4245 4246 /*define for INT_CONTEXT word*/ 4247 /*define for int_context field*/ 4248 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1 4249 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 4250 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0 4251 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) 4252 4253 4254 /* 4255 ** Definitions for SDMA_PKT_GPUVM_INV packet 4256 */ 4257 4258 /*define for HEADER word*/ 4259 /*define for op field*/ 4260 #define SDMA_PKT_GPUVM_INV_HEADER_op_offset 0 4261 #define SDMA_PKT_GPUVM_INV_HEADER_op_mask 0x000000FF 4262 #define SDMA_PKT_GPUVM_INV_HEADER_op_shift 0 4263 #define SDMA_PKT_GPUVM_INV_HEADER_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_op_shift) 4264 4265 /*define for sub_op field*/ 4266 #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset 0 4267 #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask 0x000000FF 4268 #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift 8 4269 #define SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift) 4270 4271 /*define for PAYLOAD1 word*/ 4272 /*define for per_vmid_inv_req field*/ 4273 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset 1 4274 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask 0x0000FFFF 4275 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift 0 4276 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift) 4277 4278 /*define for flush_type field*/ 4279 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset 1 4280 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask 0x00000007 4281 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift 16 4282 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift) 4283 4284 /*define for l2_ptes field*/ 4285 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset 1 4286 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask 0x00000001 4287 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift 19 4288 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift) 4289 4290 /*define for l2_pde0 field*/ 4291 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset 1 4292 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask 0x00000001 4293 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift 20 4294 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift) 4295 4296 /*define for l2_pde1 field*/ 4297 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset 1 4298 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask 0x00000001 4299 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift 21 4300 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift) 4301 4302 /*define for l2_pde2 field*/ 4303 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset 1 4304 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask 0x00000001 4305 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift 22 4306 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift) 4307 4308 /*define for l1_ptes field*/ 4309 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset 1 4310 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask 0x00000001 4311 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift 23 4312 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift) 4313 4314 /*define for clr_protection_fault_status_addr field*/ 4315 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset 1 4316 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask 0x00000001 4317 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift 24 4318 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift) 4319 4320 /*define for log_request field*/ 4321 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset 1 4322 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask 0x00000001 4323 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift 25 4324 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift) 4325 4326 /*define for four_kilobytes field*/ 4327 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset 1 4328 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask 0x00000001 4329 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift 26 4330 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift) 4331 4332 /*define for PAYLOAD2 word*/ 4333 /*define for s field*/ 4334 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset 2 4335 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask 0x00000001 4336 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift 0 4337 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift) 4338 4339 /*define for page_va_42_12 field*/ 4340 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset 2 4341 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask 0x7FFFFFFF 4342 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift 1 4343 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift) 4344 4345 /*define for PAYLOAD3 word*/ 4346 /*define for page_va_47_43 field*/ 4347 #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset 3 4348 #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask 0x0000003F 4349 #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift 0 4350 #define SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift) 4351 4352 4353 /* 4354 ** Definitions for SDMA_PKT_GCR_REQ packet 4355 */ 4356 4357 /*define for HEADER word*/ 4358 /*define for op field*/ 4359 #define SDMA_PKT_GCR_REQ_HEADER_op_offset 0 4360 #define SDMA_PKT_GCR_REQ_HEADER_op_mask 0x000000FF 4361 #define SDMA_PKT_GCR_REQ_HEADER_op_shift 0 4362 #define SDMA_PKT_GCR_REQ_HEADER_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_op_mask) << SDMA_PKT_GCR_REQ_HEADER_op_shift) 4363 4364 /*define for sub_op field*/ 4365 #define SDMA_PKT_GCR_REQ_HEADER_sub_op_offset 0 4366 #define SDMA_PKT_GCR_REQ_HEADER_sub_op_mask 0x000000FF 4367 #define SDMA_PKT_GCR_REQ_HEADER_sub_op_shift 8 4368 #define SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_sub_op_mask) << SDMA_PKT_GCR_REQ_HEADER_sub_op_shift) 4369 4370 /*define for PAYLOAD1 word*/ 4371 /*define for base_va_31_7 field*/ 4372 #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset 1 4373 #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask 0x01FFFFFF 4374 #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift 7 4375 #define SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift) 4376 4377 /*define for PAYLOAD2 word*/ 4378 /*define for base_va_47_32 field*/ 4379 #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset 2 4380 #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask 0x0000FFFF 4381 #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift 0 4382 #define SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift) 4383 4384 /*define for gcr_control_15_0 field*/ 4385 #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset 2 4386 #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask 0x0000FFFF 4387 #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift 16 4388 #define SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift) 4389 4390 /*define for PAYLOAD3 word*/ 4391 /*define for gcr_control_18_16 field*/ 4392 #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset 3 4393 #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask 0x00000007 4394 #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift 0 4395 #define SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift) 4396 4397 /*define for limit_va_31_7 field*/ 4398 #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset 3 4399 #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask 0x01FFFFFF 4400 #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift 7 4401 #define SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift) 4402 4403 /*define for PAYLOAD4 word*/ 4404 /*define for limit_va_47_32 field*/ 4405 #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset 4 4406 #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask 0x0000FFFF 4407 #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift 0 4408 #define SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift) 4409 4410 /*define for vmid field*/ 4411 #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset 4 4412 #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask 0x0000000F 4413 #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift 24 4414 #define SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift) 4415 4416 4417 /* 4418 ** Definitions for SDMA_PKT_NOP packet 4419 */ 4420 4421 /*define for HEADER word*/ 4422 /*define for op field*/ 4423 #define SDMA_PKT_NOP_HEADER_op_offset 0 4424 #define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF 4425 #define SDMA_PKT_NOP_HEADER_op_shift 0 4426 #define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) 4427 4428 /*define for sub_op field*/ 4429 #define SDMA_PKT_NOP_HEADER_sub_op_offset 0 4430 #define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF 4431 #define SDMA_PKT_NOP_HEADER_sub_op_shift 8 4432 #define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) 4433 4434 /*define for count field*/ 4435 #define SDMA_PKT_NOP_HEADER_count_offset 0 4436 #define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF 4437 #define SDMA_PKT_NOP_HEADER_count_shift 16 4438 #define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) 4439 4440 /*define for DATA0 word*/ 4441 /*define for data0 field*/ 4442 #define SDMA_PKT_NOP_DATA0_data0_offset 1 4443 #define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF 4444 #define SDMA_PKT_NOP_DATA0_data0_shift 0 4445 #define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) 4446 4447 4448 /* 4449 ** Definitions for SDMA_AQL_PKT_HEADER packet 4450 */ 4451 4452 /*define for HEADER word*/ 4453 /*define for format field*/ 4454 #define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0 4455 #define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF 4456 #define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0 4457 #define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) 4458 4459 /*define for barrier field*/ 4460 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0 4461 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001 4462 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 8 4463 #define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) 4464 4465 /*define for acquire_fence_scope field*/ 4466 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0 4467 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003 4468 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 9 4469 #define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) 4470 4471 /*define for release_fence_scope field*/ 4472 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0 4473 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003 4474 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 11 4475 #define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) 4476 4477 /*define for reserved field*/ 4478 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0 4479 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007 4480 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 13 4481 #define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) 4482 4483 /*define for op field*/ 4484 #define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0 4485 #define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F 4486 #define SDMA_AQL_PKT_HEADER_HEADER_op_shift 16 4487 #define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) 4488 4489 /*define for subop field*/ 4490 #define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0 4491 #define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007 4492 #define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 20 4493 #define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) 4494 4495 4496 /* 4497 ** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet 4498 */ 4499 4500 /*define for HEADER word*/ 4501 /*define for format field*/ 4502 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0 4503 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF 4504 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0 4505 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) 4506 4507 /*define for barrier field*/ 4508 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0 4509 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001 4510 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 8 4511 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) 4512 4513 /*define for acquire_fence_scope field*/ 4514 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0 4515 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003 4516 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 9 4517 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) 4518 4519 /*define for release_fence_scope field*/ 4520 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0 4521 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003 4522 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 11 4523 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) 4524 4525 /*define for reserved field*/ 4526 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0 4527 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007 4528 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 13 4529 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) 4530 4531 /*define for op field*/ 4532 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0 4533 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F 4534 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 16 4535 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) 4536 4537 /*define for subop field*/ 4538 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0 4539 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007 4540 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 20 4541 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) 4542 4543 /*define for RESERVED_DW1 word*/ 4544 /*define for reserved_dw1 field*/ 4545 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1 4546 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF 4547 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0 4548 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) 4549 4550 /*define for RETURN_ADDR_LO word*/ 4551 /*define for return_addr_31_0 field*/ 4552 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2 4553 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF 4554 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0 4555 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) 4556 4557 /*define for RETURN_ADDR_HI word*/ 4558 /*define for return_addr_63_32 field*/ 4559 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3 4560 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF 4561 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0 4562 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) 4563 4564 /*define for COUNT word*/ 4565 /*define for count field*/ 4566 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4 4567 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF 4568 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0 4569 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) 4570 4571 /*define for PARAMETER word*/ 4572 /*define for dst_sw field*/ 4573 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5 4574 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 4575 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 4576 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 4577 4578 /*define for src_sw field*/ 4579 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5 4580 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 4581 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 4582 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 4583 4584 /*define for SRC_ADDR_LO word*/ 4585 /*define for src_addr_31_0 field*/ 4586 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6 4587 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 4588 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 4589 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 4590 4591 /*define for SRC_ADDR_HI word*/ 4592 /*define for src_addr_63_32 field*/ 4593 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7 4594 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 4595 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 4596 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 4597 4598 /*define for DST_ADDR_LO word*/ 4599 /*define for dst_addr_31_0 field*/ 4600 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8 4601 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 4602 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 4603 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 4604 4605 /*define for DST_ADDR_HI word*/ 4606 /*define for dst_addr_63_32 field*/ 4607 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9 4608 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 4609 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 4610 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 4611 4612 /*define for RESERVED_DW10 word*/ 4613 /*define for reserved_dw10 field*/ 4614 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10 4615 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF 4616 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0 4617 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) 4618 4619 /*define for RESERVED_DW11 word*/ 4620 /*define for reserved_dw11 field*/ 4621 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11 4622 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF 4623 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0 4624 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) 4625 4626 /*define for RESERVED_DW12 word*/ 4627 /*define for reserved_dw12 field*/ 4628 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12 4629 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF 4630 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0 4631 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) 4632 4633 /*define for RESERVED_DW13 word*/ 4634 /*define for reserved_dw13 field*/ 4635 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13 4636 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF 4637 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0 4638 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) 4639 4640 /*define for COMPLETION_SIGNAL_LO word*/ 4641 /*define for completion_signal_31_0 field*/ 4642 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 4643 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF 4644 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 4645 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) 4646 4647 /*define for COMPLETION_SIGNAL_HI word*/ 4648 /*define for completion_signal_63_32 field*/ 4649 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 4650 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF 4651 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 4652 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) 4653 4654 4655 /* 4656 ** Definitions for SDMA_AQL_PKT_BARRIER_OR packet 4657 */ 4658 4659 /*define for HEADER word*/ 4660 /*define for format field*/ 4661 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0 4662 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF 4663 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0 4664 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) 4665 4666 /*define for barrier field*/ 4667 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0 4668 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001 4669 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 8 4670 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) 4671 4672 /*define for acquire_fence_scope field*/ 4673 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0 4674 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003 4675 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 9 4676 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) 4677 4678 /*define for release_fence_scope field*/ 4679 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0 4680 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003 4681 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 11 4682 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) 4683 4684 /*define for reserved field*/ 4685 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0 4686 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007 4687 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 13 4688 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) 4689 4690 /*define for op field*/ 4691 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0 4692 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F 4693 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 16 4694 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) 4695 4696 /*define for subop field*/ 4697 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0 4698 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007 4699 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 20 4700 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) 4701 4702 /*define for RESERVED_DW1 word*/ 4703 /*define for reserved_dw1 field*/ 4704 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1 4705 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF 4706 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0 4707 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) 4708 4709 /*define for DEPENDENT_ADDR_0_LO word*/ 4710 /*define for dependent_addr_0_31_0 field*/ 4711 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2 4712 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF 4713 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0 4714 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) 4715 4716 /*define for DEPENDENT_ADDR_0_HI word*/ 4717 /*define for dependent_addr_0_63_32 field*/ 4718 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3 4719 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF 4720 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0 4721 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) 4722 4723 /*define for DEPENDENT_ADDR_1_LO word*/ 4724 /*define for dependent_addr_1_31_0 field*/ 4725 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4 4726 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF 4727 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0 4728 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) 4729 4730 /*define for DEPENDENT_ADDR_1_HI word*/ 4731 /*define for dependent_addr_1_63_32 field*/ 4732 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5 4733 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF 4734 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0 4735 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) 4736 4737 /*define for DEPENDENT_ADDR_2_LO word*/ 4738 /*define for dependent_addr_2_31_0 field*/ 4739 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6 4740 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF 4741 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0 4742 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) 4743 4744 /*define for DEPENDENT_ADDR_2_HI word*/ 4745 /*define for dependent_addr_2_63_32 field*/ 4746 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7 4747 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF 4748 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0 4749 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) 4750 4751 /*define for DEPENDENT_ADDR_3_LO word*/ 4752 /*define for dependent_addr_3_31_0 field*/ 4753 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8 4754 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF 4755 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0 4756 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) 4757 4758 /*define for DEPENDENT_ADDR_3_HI word*/ 4759 /*define for dependent_addr_3_63_32 field*/ 4760 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9 4761 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF 4762 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0 4763 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) 4764 4765 /*define for DEPENDENT_ADDR_4_LO word*/ 4766 /*define for dependent_addr_4_31_0 field*/ 4767 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10 4768 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF 4769 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0 4770 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) 4771 4772 /*define for DEPENDENT_ADDR_4_HI word*/ 4773 /*define for dependent_addr_4_63_32 field*/ 4774 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11 4775 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF 4776 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0 4777 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) 4778 4779 /*define for RESERVED_DW12 word*/ 4780 /*define for reserved_dw12 field*/ 4781 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset 12 4782 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF 4783 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift 0 4784 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift) 4785 4786 /*define for RESERVED_DW13 word*/ 4787 /*define for reserved_dw13 field*/ 4788 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13 4789 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF 4790 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0 4791 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) 4792 4793 /*define for COMPLETION_SIGNAL_LO word*/ 4794 /*define for completion_signal_31_0 field*/ 4795 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 4796 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF 4797 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 4798 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) 4799 4800 /*define for COMPLETION_SIGNAL_HI word*/ 4801 /*define for completion_signal_63_32 field*/ 4802 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 4803 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF 4804 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 4805 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) 4806 4807 4808 #endif /* __NAVI10_SDMA_PKT_OPEN_H_ */ 4809
Indexes created Sat Sep 20 22:09:52 GMT 2025