1 /* $NetBSD: nvd.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef NVD_H 27 #define NVD_H 28 29 /** 30 * Navi's PM4 definitions 31 */ 32 #define PACKET_TYPE0 0 33 #define PACKET_TYPE1 1 34 #define PACKET_TYPE2 2 35 #define PACKET_TYPE3 3 36 37 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 38 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 39 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 40 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 41 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 42 ((reg) & 0xFFFF) | \ 43 ((n) & 0x3FFF) << 16) 44 #define CP_PACKET2 0x80000000 45 #define PACKET2_PAD_SHIFT 0 46 #define PACKET2_PAD_MASK (0x3fffffff << 0) 47 48 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 49 50 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 51 (((op) & 0xFF) << 8) | \ 52 ((n) & 0x3FFF) << 16) 53 54 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 55 56 /* Packet 3 types */ 57 #define PACKET3_NOP 0x10 58 #define PACKET3_SET_BASE 0x11 59 #define PACKET3_BASE_INDEX(x) ((x) << 0) 60 #define CE_PARTITION_BASE 3 61 #define PACKET3_CLEAR_STATE 0x12 62 #define PACKET3_INDEX_BUFFER_SIZE 0x13 63 #define PACKET3_DISPATCH_DIRECT 0x15 64 #define PACKET3_DISPATCH_INDIRECT 0x16 65 #define PACKET3_INDIRECT_BUFFER_END 0x17 66 #define PACKET3_INDIRECT_BUFFER_CNST_END 0x19 67 #define PACKET3_ATOMIC_GDS 0x1D 68 #define PACKET3_ATOMIC_MEM 0x1E 69 #define PACKET3_OCCLUSION_QUERY 0x1F 70 #define PACKET3_SET_PREDICATION 0x20 71 #define PACKET3_REG_RMW 0x21 72 #define PACKET3_COND_EXEC 0x22 73 #define PACKET3_PRED_EXEC 0x23 74 #define PACKET3_DRAW_INDIRECT 0x24 75 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 76 #define PACKET3_INDEX_BASE 0x26 77 #define PACKET3_DRAW_INDEX_2 0x27 78 #define PACKET3_CONTEXT_CONTROL 0x28 79 #define PACKET3_INDEX_TYPE 0x2A 80 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 81 #define PACKET3_DRAW_INDEX_AUTO 0x2D 82 #define PACKET3_NUM_INSTANCES 0x2F 83 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 84 #define PACKET3_INDIRECT_BUFFER_PRIV 0x32 85 #define PACKET3_INDIRECT_BUFFER_CNST 0x33 86 #define PACKET3_COND_INDIRECT_BUFFER_CNST 0x33 87 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 88 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 89 #define PACKET3_DRAW_PREAMBLE 0x36 90 #define PACKET3_WRITE_DATA 0x37 91 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 92 /* 0 - register 93 * 1 - memory (sync - via GRBM) 94 * 2 - gl2 95 * 3 - gds 96 * 4 - reserved 97 * 5 - memory (async - direct) 98 */ 99 #define WR_ONE_ADDR (1 << 16) 100 #define WR_CONFIRM (1 << 20) 101 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 102 /* 0 - LRU 103 * 1 - Stream 104 */ 105 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 106 /* 0 - me 107 * 1 - pfp 108 * 2 - ce 109 */ 110 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 111 #define PACKET3_MEM_SEMAPHORE 0x39 112 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 113 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 114 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 115 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 116 #define PACKET3_DRAW_INDEX_MULTI_INST 0x3A 117 #define PACKET3_COPY_DW 0x3B 118 #define PACKET3_WAIT_REG_MEM 0x3C 119 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 120 /* 0 - always 121 * 1 - < 122 * 2 - <= 123 * 3 - == 124 * 4 - != 125 * 5 - >= 126 * 6 - > 127 */ 128 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 129 /* 0 - reg 130 * 1 - mem 131 */ 132 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 133 /* 0 - wait_reg_mem 134 * 1 - wr_wait_wr_reg 135 */ 136 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 137 /* 0 - me 138 * 1 - pfp 139 */ 140 #define PACKET3_INDIRECT_BUFFER 0x3F 141 #define INDIRECT_BUFFER_VALID (1 << 23) 142 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 143 /* 0 - LRU 144 * 1 - Stream 145 * 2 - Bypass 146 */ 147 #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) 148 #define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30) 149 #define PACKET3_COND_INDIRECT_BUFFER 0x3F 150 #define PACKET3_COPY_DATA 0x40 151 #define PACKET3_CP_DMA 0x41 152 #define PACKET3_PFP_SYNC_ME 0x42 153 #define PACKET3_SURFACE_SYNC 0x43 154 #define PACKET3_ME_INITIALIZE 0x44 155 #define PACKET3_COND_WRITE 0x45 156 #define PACKET3_EVENT_WRITE 0x46 157 #define EVENT_TYPE(x) ((x) << 0) 158 #define EVENT_INDEX(x) ((x) << 8) 159 /* 0 - any non-TS event 160 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 161 * 2 - SAMPLE_PIPELINESTAT 162 * 3 - SAMPLE_STREAMOUTSTAT* 163 * 4 - *S_PARTIAL_FLUSH 164 */ 165 #define PACKET3_EVENT_WRITE_EOP 0x47 166 #define PACKET3_EVENT_WRITE_EOS 0x48 167 #define PACKET3_RELEASE_MEM 0x49 168 #define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) 169 #define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) 170 #define PACKET3_RELEASE_MEM_GCR_GLM_WB (1 << 12) 171 #define PACKET3_RELEASE_MEM_GCR_GLM_INV (1 << 13) 172 #define PACKET3_RELEASE_MEM_GCR_GLV_INV (1 << 14) 173 #define PACKET3_RELEASE_MEM_GCR_GL1_INV (1 << 15) 174 #define PACKET3_RELEASE_MEM_GCR_GL2_US (1 << 16) 175 #define PACKET3_RELEASE_MEM_GCR_GL2_RANGE (1 << 17) 176 #define PACKET3_RELEASE_MEM_GCR_GL2_DISCARD (1 << 19) 177 #define PACKET3_RELEASE_MEM_GCR_GL2_INV (1 << 20) 178 #define PACKET3_RELEASE_MEM_GCR_GL2_WB (1 << 21) 179 #define PACKET3_RELEASE_MEM_GCR_SEQ (1 << 22) 180 #define PACKET3_RELEASE_MEM_CACHE_POLICY(x) ((x) << 25) 181 /* 0 - cache_policy__me_release_mem__lru 182 * 1 - cache_policy__me_release_mem__stream 183 * 2 - cache_policy__me_release_mem__noa 184 * 3 - cache_policy__me_release_mem__bypass 185 */ 186 #define PACKET3_RELEASE_MEM_EXECUTE (1 << 28) 187 188 #define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) 189 /* 0 - discard 190 * 1 - send low 32bit data 191 * 2 - send 64bit data 192 * 3 - send 64bit GPU counter value 193 * 4 - send 64bit sys counter value 194 */ 195 #define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) 196 /* 0 - none 197 * 1 - interrupt only (DATA_SEL = 0) 198 * 2 - interrupt when data write is confirmed 199 */ 200 #define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) 201 /* 0 - MC 202 * 1 - TC/L2 203 */ 204 205 206 207 #define PACKET3_PREAMBLE_CNTL 0x4A 208 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 209 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 210 #define PACKET3_DMA_DATA 0x50 211 /* 1. header 212 * 2. CONTROL 213 * 3. SRC_ADDR_LO or DATA [31:0] 214 * 4. SRC_ADDR_HI [31:0] 215 * 5. DST_ADDR_LO [31:0] 216 * 6. DST_ADDR_HI [7:0] 217 * 7. COMMAND [31:26] | BYTE_COUNT [25:0] 218 */ 219 /* CONTROL */ 220 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 221 /* 0 - ME 222 * 1 - PFP 223 */ 224 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 225 /* 0 - LRU 226 * 1 - Stream 227 */ 228 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 229 /* 0 - DST_ADDR using DAS 230 * 1 - GDS 231 * 3 - DST_ADDR using L2 232 */ 233 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 234 /* 0 - LRU 235 * 1 - Stream 236 */ 237 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 238 /* 0 - SRC_ADDR using SAS 239 * 1 - GDS 240 * 2 - DATA 241 * 3 - SRC_ADDR using L2 242 */ 243 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 244 /* COMMAND */ 245 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 246 /* 0 - memory 247 * 1 - register 248 */ 249 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 250 /* 0 - memory 251 * 1 - register 252 */ 253 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 254 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 255 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 256 #define PACKET3_CONTEXT_REG_RMW 0x51 257 #define PACKET3_GFX_CNTX_UPDATE 0x52 258 #define PACKET3_BLK_CNTX_UPDATE 0x53 259 #define PACKET3_INCR_UPDT_STATE 0x55 260 #define PACKET3_ACQUIRE_MEM 0x58 261 #define PACKET3_REWIND 0x59 262 #define PACKET3_INTERRUPT 0x5A 263 #define PACKET3_GEN_PDEPTE 0x5B 264 #define PACKET3_INDIRECT_BUFFER_PASID 0x5C 265 #define PACKET3_PRIME_UTCL2 0x5D 266 #define PACKET3_LOAD_UCONFIG_REG 0x5E 267 #define PACKET3_LOAD_SH_REG 0x5F 268 #define PACKET3_LOAD_CONFIG_REG 0x60 269 #define PACKET3_LOAD_CONTEXT_REG 0x61 270 #define PACKET3_LOAD_COMPUTE_STATE 0x62 271 #define PACKET3_LOAD_SH_REG_INDEX 0x63 272 #define PACKET3_SET_CONFIG_REG 0x68 273 #define PACKET3_SET_CONFIG_REG_START 0x00002000 274 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 275 #define PACKET3_SET_CONTEXT_REG 0x69 276 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 277 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 278 #define PACKET3_SET_CONTEXT_REG_INDEX 0x6A 279 #define PACKET3_SET_VGPR_REG_DI_MULTI 0x71 280 #define PACKET3_SET_SH_REG_DI 0x72 281 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 282 #define PACKET3_SET_SH_REG_DI_MULTI 0x74 283 #define PACKET3_GFX_PIPE_LOCK 0x75 284 #define PACKET3_SET_SH_REG 0x76 285 #define PACKET3_SET_SH_REG_START 0x00002c00 286 #define PACKET3_SET_SH_REG_END 0x00003000 287 #define PACKET3_SET_SH_REG_OFFSET 0x77 288 #define PACKET3_SET_QUEUE_REG 0x78 289 #define PACKET3_SET_UCONFIG_REG 0x79 290 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 291 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 292 #define PACKET3_SET_UCONFIG_REG_INDEX 0x7A 293 #define PACKET3_FORWARD_HEADER 0x7C 294 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 295 #define PACKET3_SCRATCH_RAM_READ 0x7E 296 #define PACKET3_LOAD_CONST_RAM 0x80 297 #define PACKET3_WRITE_CONST_RAM 0x81 298 #define PACKET3_DUMP_CONST_RAM 0x83 299 #define PACKET3_INCREMENT_CE_COUNTER 0x84 300 #define PACKET3_INCREMENT_DE_COUNTER 0x85 301 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 302 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 303 #define PACKET3_SWITCH_BUFFER 0x8B 304 #define PACKET3_DISPATCH_DRAW_PREAMBLE 0x8C 305 #define PACKET3_DISPATCH_DRAW_PREAMBLE_ACE 0x8C 306 #define PACKET3_DISPATCH_DRAW 0x8D 307 #define PACKET3_DISPATCH_DRAW_ACE 0x8D 308 #define PACKET3_GET_LOD_STATS 0x8E 309 #define PACKET3_DRAW_MULTI_PREAMBLE 0x8F 310 #define PACKET3_FRAME_CONTROL 0x90 311 # define FRAME_CMD(x) ((x) << 28) 312 /* 313 * x=0: tmz_begin 314 * x=1: tmz_end 315 */ 316 #define PACKET3_INDEX_ATTRIBUTES_INDIRECT 0x91 317 #define PACKET3_WAIT_REG_MEM64 0x93 318 #define PACKET3_COND_PREEMPT 0x94 319 #define PACKET3_HDP_FLUSH 0x95 320 #define PACKET3_COPY_DATA_RB 0x96 321 #define PACKET3_INVALIDATE_TLBS 0x98 322 # define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) 323 # define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) 324 # define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) 325 #define PACKET3_AQL_PACKET 0x99 326 #define PACKET3_DMA_DATA_FILL_MULTI 0x9A 327 #define PACKET3_SET_SH_REG_INDEX 0x9B 328 #define PACKET3_DRAW_INDIRECT_COUNT_MULTI 0x9C 329 #define PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI 0x9D 330 #define PACKET3_DUMP_CONST_RAM_OFFSET 0x9E 331 #define PACKET3_LOAD_CONTEXT_REG_INDEX 0x9F 332 #define PACKET3_SET_RESOURCES 0xA0 333 /* 1. header 334 * 2. CONTROL 335 * 3. QUEUE_MASK_LO [31:0] 336 * 4. QUEUE_MASK_HI [31:0] 337 * 5. GWS_MASK_LO [31:0] 338 * 6. GWS_MASK_HI [31:0] 339 * 7. OAC_MASK [15:0] 340 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] 341 */ 342 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) 343 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) 344 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) 345 #define PACKET3_MAP_PROCESS 0xA1 346 #define PACKET3_MAP_QUEUES 0xA2 347 /* 1. header 348 * 2. CONTROL 349 * 3. CONTROL2 350 * 4. MQD_ADDR_LO [31:0] 351 * 5. MQD_ADDR_HI [31:0] 352 * 6. WPTR_ADDR_LO [31:0] 353 * 7. WPTR_ADDR_HI [31:0] 354 */ 355 /* CONTROL */ 356 # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 357 # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) 358 # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) 359 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) 360 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) 361 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) 362 # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) 363 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 364 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 365 /* CONTROL2 */ 366 # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) 367 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) 368 #define PACKET3_UNMAP_QUEUES 0xA3 369 /* 1. header 370 * 2. CONTROL 371 * 3. CONTROL2 372 * 4. CONTROL3 373 * 5. CONTROL4 374 * 6. CONTROL5 375 */ 376 /* CONTROL */ 377 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) 378 /* 0 - PREEMPT_QUEUES 379 * 1 - RESET_QUEUES 380 * 2 - DISABLE_PROCESS_QUEUES 381 * 3 - PREEMPT_QUEUES_NO_UNMAP 382 */ 383 # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 384 # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 385 # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 386 /* CONTROL2a */ 387 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) 388 /* CONTROL2b */ 389 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) 390 /* CONTROL3a */ 391 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) 392 /* CONTROL3b */ 393 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) 394 /* CONTROL4 */ 395 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) 396 /* CONTROL5 */ 397 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) 398 #define PACKET3_QUERY_STATUS 0xA4 399 /* 1. header 400 * 2. CONTROL 401 * 3. CONTROL2 402 * 4. ADDR_LO [31:0] 403 * 5. ADDR_HI [31:0] 404 * 6. DATA_LO [31:0] 405 * 7. DATA_HI [31:0] 406 */ 407 /* CONTROL */ 408 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) 409 # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) 410 # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) 411 /* CONTROL2a */ 412 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) 413 /* CONTROL2b */ 414 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) 415 # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) 416 #define PACKET3_RUN_LIST 0xA5 417 #define PACKET3_MAP_PROCESS_VM 0xA6 418 419 420 #endif 421
Indexes created Sat Sep 20 22:09:52 GMT 2025