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      1 /*	$NetBSD: sdma_v5_0.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2019 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 
     26 #ifndef __SDMA_V5_0_H__
     27 #define __SDMA_V5_0_H__
     28 
     29 enum sdma_v5_0_utcl2_cache_read_policy {
     30 	CACHE_READ_POLICY_L2__LRU    = 0x00000000,
     31 	CACHE_READ_POLICY_L2__STREAM = 0x00000001,
     32 	CACHE_READ_POLICY_L2__NOA    = 0x00000002,
     33 	CACHE_READ_POLICY_L2__DEFAULT = CACHE_READ_POLICY_L2__NOA,
     34 };
     35 
     36 enum sdma_v5_0_utcl2_cache_write_policy {
     37 	CACHE_WRITE_POLICY_L2__LRU    = 0x00000000,
     38 	CACHE_WRITE_POLICY_L2__STREAM = 0x00000001,
     39 	CACHE_WRITE_POLICY_L2__NOA    = 0x00000002,
     40 	CACHE_WRITE_POLICY_L2__BYPASS = 0x00000003,
     41 	CACHE_WRITE_POLICY_L2__DEFAULT = CACHE_WRITE_POLICY_L2__BYPASS,
     42 };
     43 
     44 extern const struct amd_ip_funcs sdma_v5_0_ip_funcs;
     45 extern const struct amdgpu_ip_block_version sdma_v5_0_ip_block;
     46 
     47 #endif /* __SDMA_V5_0_H__ */
     48