1 /* $NetBSD: soc15d.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef SOC15_H 26 #define SOC15_H 27 28 #define GFX9_NUM_GFX_RINGS 1 29 #define GFX9_NUM_COMPUTE_RINGS 8 30 31 /* 32 * PM4 33 */ 34 #define PACKET_TYPE0 0 35 #define PACKET_TYPE1 1 36 #define PACKET_TYPE2 2 37 #define PACKET_TYPE3 3 38 39 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 40 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 41 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 42 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 43 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 44 ((reg) & 0xFFFF) | \ 45 ((n) & 0x3FFF) << 16) 46 #define CP_PACKET2 0x80000000 47 #define PACKET2_PAD_SHIFT 0 48 #define PACKET2_PAD_MASK (0x3fffffff << 0) 49 50 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 51 52 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 53 (((op) & 0xFF) << 8) | \ 54 ((n) & 0x3FFF) << 16) 55 56 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 57 58 #define PACKETJ_CONDITION_CHECK0 0 59 #define PACKETJ_CONDITION_CHECK1 1 60 #define PACKETJ_CONDITION_CHECK2 2 61 #define PACKETJ_CONDITION_CHECK3 3 62 #define PACKETJ_CONDITION_CHECK4 4 63 #define PACKETJ_CONDITION_CHECK5 5 64 #define PACKETJ_CONDITION_CHECK6 6 65 #define PACKETJ_CONDITION_CHECK7 7 66 67 #define PACKETJ_TYPE0 0 68 #define PACKETJ_TYPE1 1 69 #define PACKETJ_TYPE2 2 70 #define PACKETJ_TYPE3 3 71 #define PACKETJ_TYPE4 4 72 #define PACKETJ_TYPE5 5 73 #define PACKETJ_TYPE6 6 74 #define PACKETJ_TYPE7 7 75 76 #define PACKETJ(reg, r, cond, type) ((reg & 0x3FFFF) | \ 77 ((r & 0x3F) << 18) | \ 78 ((cond & 0xF) << 24) | \ 79 ((type & 0xF) << 28)) 80 81 /* Packet 3 types */ 82 #define PACKET3_NOP 0x10 83 #define PACKET3_SET_BASE 0x11 84 #define PACKET3_BASE_INDEX(x) ((x) << 0) 85 #define CE_PARTITION_BASE 3 86 #define PACKET3_CLEAR_STATE 0x12 87 #define PACKET3_INDEX_BUFFER_SIZE 0x13 88 #define PACKET3_DISPATCH_DIRECT 0x15 89 #define PACKET3_DISPATCH_INDIRECT 0x16 90 #define PACKET3_ATOMIC_GDS 0x1D 91 #define PACKET3_ATOMIC_MEM 0x1E 92 #define PACKET3_OCCLUSION_QUERY 0x1F 93 #define PACKET3_SET_PREDICATION 0x20 94 #define PACKET3_REG_RMW 0x21 95 #define PACKET3_COND_EXEC 0x22 96 #define PACKET3_PRED_EXEC 0x23 97 #define PACKET3_DRAW_INDIRECT 0x24 98 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 99 #define PACKET3_INDEX_BASE 0x26 100 #define PACKET3_DRAW_INDEX_2 0x27 101 #define PACKET3_CONTEXT_CONTROL 0x28 102 #define PACKET3_INDEX_TYPE 0x2A 103 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 104 #define PACKET3_DRAW_INDEX_AUTO 0x2D 105 #define PACKET3_NUM_INSTANCES 0x2F 106 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 107 #define PACKET3_INDIRECT_BUFFER_CONST 0x33 108 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 109 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 110 #define PACKET3_DRAW_PREAMBLE 0x36 111 #define PACKET3_WRITE_DATA 0x37 112 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 113 /* 0 - register 114 * 1 - memory (sync - via GRBM) 115 * 2 - gl2 116 * 3 - gds 117 * 4 - reserved 118 * 5 - memory (async - direct) 119 */ 120 #define WR_ONE_ADDR (1 << 16) 121 #define WR_CONFIRM (1 << 20) 122 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 123 /* 0 - LRU 124 * 1 - Stream 125 */ 126 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 127 /* 0 - me 128 * 1 - pfp 129 * 2 - ce 130 */ 131 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 132 #define PACKET3_MEM_SEMAPHORE 0x39 133 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 134 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 135 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 136 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 137 #define PACKET3_WAIT_REG_MEM 0x3C 138 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 139 /* 0 - always 140 * 1 - < 141 * 2 - <= 142 * 3 - == 143 * 4 - != 144 * 5 - >= 145 * 6 - > 146 */ 147 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 148 /* 0 - reg 149 * 1 - mem 150 */ 151 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 152 /* 0 - wait_reg_mem 153 * 1 - wr_wait_wr_reg 154 */ 155 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 156 /* 0 - me 157 * 1 - pfp 158 */ 159 #define PACKET3_INDIRECT_BUFFER 0x3F 160 #define INDIRECT_BUFFER_VALID (1 << 23) 161 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 162 /* 0 - LRU 163 * 1 - Stream 164 * 2 - Bypass 165 */ 166 #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) 167 #define PACKET3_COPY_DATA 0x40 168 #define PACKET3_PFP_SYNC_ME 0x42 169 #define PACKET3_COND_WRITE 0x45 170 #define PACKET3_EVENT_WRITE 0x46 171 #define EVENT_TYPE(x) ((x) << 0) 172 #define EVENT_INDEX(x) ((x) << 8) 173 /* 0 - any non-TS event 174 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 175 * 2 - SAMPLE_PIPELINESTAT 176 * 3 - SAMPLE_STREAMOUTSTAT* 177 * 4 - *S_PARTIAL_FLUSH 178 */ 179 #define PACKET3_RELEASE_MEM 0x49 180 #define EVENT_TYPE(x) ((x) << 0) 181 #define EVENT_INDEX(x) ((x) << 8) 182 #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 183 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 184 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 185 #define EOP_TCL1_ACTION_EN (1 << 16) 186 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 187 #define EOP_TC_NC_ACTION_EN (1 << 19) 188 #define EOP_TC_MD_ACTION_EN (1 << 21) /* L2 metadata */ 189 190 #define DATA_SEL(x) ((x) << 29) 191 /* 0 - discard 192 * 1 - send low 32bit data 193 * 2 - send 64bit data 194 * 3 - send 64bit GPU counter value 195 * 4 - send 64bit sys counter value 196 */ 197 #define INT_SEL(x) ((x) << 24) 198 /* 0 - none 199 * 1 - interrupt only (DATA_SEL = 0) 200 * 2 - interrupt when data write is confirmed 201 */ 202 #define DST_SEL(x) ((x) << 16) 203 /* 0 - MC 204 * 1 - TC/L2 205 */ 206 207 208 209 #define PACKET3_PREAMBLE_CNTL 0x4A 210 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 211 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 212 #define PACKET3_DMA_DATA 0x50 213 /* 1. header 214 * 2. CONTROL 215 * 3. SRC_ADDR_LO or DATA [31:0] 216 * 4. SRC_ADDR_HI [31:0] 217 * 5. DST_ADDR_LO [31:0] 218 * 6. DST_ADDR_HI [7:0] 219 * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 220 */ 221 /* CONTROL */ 222 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 223 /* 0 - ME 224 * 1 - PFP 225 */ 226 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 227 /* 0 - LRU 228 * 1 - Stream 229 */ 230 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 231 /* 0 - DST_ADDR using DAS 232 * 1 - GDS 233 * 3 - DST_ADDR using L2 234 */ 235 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 236 /* 0 - LRU 237 * 1 - Stream 238 */ 239 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 240 /* 0 - SRC_ADDR using SAS 241 * 1 - GDS 242 * 2 - DATA 243 * 3 - SRC_ADDR using L2 244 */ 245 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 246 /* COMMAND */ 247 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 248 /* 0 - memory 249 * 1 - register 250 */ 251 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 252 /* 0 - memory 253 * 1 - register 254 */ 255 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 256 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 257 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 258 #define PACKET3_AQUIRE_MEM 0x58 259 #define PACKET3_REWIND 0x59 260 #define PACKET3_LOAD_UCONFIG_REG 0x5E 261 #define PACKET3_LOAD_SH_REG 0x5F 262 #define PACKET3_LOAD_CONFIG_REG 0x60 263 #define PACKET3_LOAD_CONTEXT_REG 0x61 264 #define PACKET3_SET_CONFIG_REG 0x68 265 #define PACKET3_SET_CONFIG_REG_START 0x00002000 266 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 267 #define PACKET3_SET_CONTEXT_REG 0x69 268 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 269 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 270 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 271 #define PACKET3_SET_SH_REG 0x76 272 #define PACKET3_SET_SH_REG_START 0x00002c00 273 #define PACKET3_SET_SH_REG_END 0x00003000 274 #define PACKET3_SET_SH_REG_OFFSET 0x77 275 #define PACKET3_SET_QUEUE_REG 0x78 276 #define PACKET3_SET_UCONFIG_REG 0x79 277 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 278 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 279 #define PACKET3_SET_UCONFIG_REG_INDEX_TYPE (2 << 28) 280 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 281 #define PACKET3_SCRATCH_RAM_READ 0x7E 282 #define PACKET3_LOAD_CONST_RAM 0x80 283 #define PACKET3_WRITE_CONST_RAM 0x81 284 #define PACKET3_DUMP_CONST_RAM 0x83 285 #define PACKET3_INCREMENT_CE_COUNTER 0x84 286 #define PACKET3_INCREMENT_DE_COUNTER 0x85 287 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 288 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 289 #define PACKET3_SWITCH_BUFFER 0x8B 290 #define PACKET3_FRAME_CONTROL 0x90 291 # define FRAME_CMD(x) ((x) << 28) 292 /* 293 * x=0: tmz_begin 294 * x=1: tmz_end 295 */ 296 297 #define PACKET3_INVALIDATE_TLBS 0x98 298 # define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) 299 # define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) 300 # define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) 301 # define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29) 302 #define PACKET3_SET_RESOURCES 0xA0 303 /* 1. header 304 * 2. CONTROL 305 * 3. QUEUE_MASK_LO [31:0] 306 * 4. QUEUE_MASK_HI [31:0] 307 * 5. GWS_MASK_LO [31:0] 308 * 6. GWS_MASK_HI [31:0] 309 * 7. OAC_MASK [15:0] 310 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] 311 */ 312 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) 313 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) 314 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) 315 #define PACKET3_MAP_QUEUES 0xA2 316 /* 1. header 317 * 2. CONTROL 318 * 3. CONTROL2 319 * 4. MQD_ADDR_LO [31:0] 320 * 5. MQD_ADDR_HI [31:0] 321 * 6. WPTR_ADDR_LO [31:0] 322 * 7. WPTR_ADDR_HI [31:0] 323 */ 324 /* CONTROL */ 325 # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 326 # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) 327 # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) 328 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) 329 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) 330 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) 331 # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) 332 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 333 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 334 /* CONTROL2 */ 335 # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) 336 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) 337 #define PACKET3_UNMAP_QUEUES 0xA3 338 /* 1. header 339 * 2. CONTROL 340 * 3. CONTROL2 341 * 4. CONTROL3 342 * 5. CONTROL4 343 * 6. CONTROL5 344 */ 345 /* CONTROL */ 346 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) 347 /* 0 - PREEMPT_QUEUES 348 * 1 - RESET_QUEUES 349 * 2 - DISABLE_PROCESS_QUEUES 350 * 3 - PREEMPT_QUEUES_NO_UNMAP 351 */ 352 # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 353 # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 354 # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 355 /* CONTROL2a */ 356 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) 357 /* CONTROL2b */ 358 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) 359 /* CONTROL3a */ 360 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) 361 /* CONTROL3b */ 362 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) 363 /* CONTROL4 */ 364 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) 365 /* CONTROL5 */ 366 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) 367 #define PACKET3_QUERY_STATUS 0xA4 368 /* 1. header 369 * 2. CONTROL 370 * 3. CONTROL2 371 * 4. ADDR_LO [31:0] 372 * 5. ADDR_HI [31:0] 373 * 6. DATA_LO [31:0] 374 * 7. DATA_HI [31:0] 375 */ 376 /* CONTROL */ 377 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) 378 # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) 379 # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) 380 /* CONTROL2a */ 381 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) 382 /* CONTROL2b */ 383 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) 384 # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) 385 386 387 #define VCE_CMD_NO_OP 0x00000000 388 #define VCE_CMD_END 0x00000001 389 #define VCE_CMD_IB 0x00000002 390 #define VCE_CMD_FENCE 0x00000003 391 #define VCE_CMD_TRAP 0x00000004 392 #define VCE_CMD_IB_AUTO 0x00000005 393 #define VCE_CMD_SEMAPHORE 0x00000006 394 395 #define VCE_CMD_IB_VM 0x00000102 396 #define VCE_CMD_WAIT_GE 0x00000106 397 #define VCE_CMD_UPDATE_PTB 0x00000107 398 #define VCE_CMD_FLUSH_TLB 0x00000108 399 #define VCE_CMD_REG_WRITE 0x00000109 400 #define VCE_CMD_REG_WAIT 0x0000010a 401 402 #define HEVC_ENC_CMD_NO_OP 0x00000000 403 #define HEVC_ENC_CMD_END 0x00000001 404 #define HEVC_ENC_CMD_FENCE 0x00000003 405 #define HEVC_ENC_CMD_TRAP 0x00000004 406 #define HEVC_ENC_CMD_IB_VM 0x00000102 407 #define HEVC_ENC_CMD_REG_WRITE 0x00000109 408 #define HEVC_ENC_CMD_REG_WAIT 0x0000010a 409 410 #endif 411
Indexes created Sat Sep 20 22:09:52 GMT 2025