1 /* $NetBSD: tonga_sdma_pkt_open.h,v 1.3 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef __TONGA_SDMA_PKT_OPEN_H_ 26 #define __TONGA_SDMA_PKT_OPEN_H_ 27 28 #define SDMA_OP_NOP 0 29 #define SDMA_OP_COPY 1 30 #define SDMA_OP_WRITE 2 31 #define SDMA_OP_INDIRECT 4 32 #define SDMA_OP_FENCE 5 33 #define SDMA_OP_TRAP 6 34 #define SDMA_OP_SEM 7 35 #define SDMA_OP_POLL_REGMEM 8 36 #define SDMA_OP_COND_EXE 9 37 #define SDMA_OP_ATOMIC 10 38 #define SDMA_OP_CONST_FILL 11 39 #define SDMA_OP_GEN_PTEPDE 12 40 #define SDMA_OP_TIMESTAMP 13 41 #define SDMA_OP_SRBM_WRITE 14 42 #define SDMA_OP_PRE_EXE 15 43 #define SDMA_SUBOP_TIMESTAMP_SET 0 44 #define SDMA_SUBOP_TIMESTAMP_GET 1 45 #define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 46 #define SDMA_SUBOP_COPY_LINEAR 0 47 #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 48 #define SDMA_SUBOP_COPY_TILED 1 49 #define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 50 #define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 51 #define SDMA_SUBOP_COPY_SOA 3 52 #define SDMA_SUBOP_WRITE_LINEAR 0 53 #define SDMA_SUBOP_WRITE_TILED 1 54 55 /*define for op field*/ 56 #define SDMA_PKT_HEADER_op_offset 0 57 #define SDMA_PKT_HEADER_op_mask 0x000000FF 58 #define SDMA_PKT_HEADER_op_shift 0 59 #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) 60 61 /*define for sub_op field*/ 62 #define SDMA_PKT_HEADER_sub_op_offset 0 63 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF 64 #define SDMA_PKT_HEADER_sub_op_shift 8 65 #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) 66 67 /* 68 ** Definitions for SDMA_PKT_COPY_LINEAR packet 69 */ 70 71 /*define for HEADER word*/ 72 /*define for op field*/ 73 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 74 #define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF 75 #define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 76 #define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) 77 78 /*define for sub_op field*/ 79 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 80 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF 81 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 82 #define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) 83 84 /*define for broadcast field*/ 85 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 86 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 87 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 88 #define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) 89 90 /*define for COUNT word*/ 91 /*define for count field*/ 92 #define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 93 #define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF 94 #define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 95 #define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) 96 97 /*define for PARAMETER word*/ 98 /*define for dst_sw field*/ 99 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 100 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 101 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 102 #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 103 104 /*define for dst_ha field*/ 105 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_offset 2 106 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask 0x00000001 107 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_shift 22 108 #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_shift) 109 110 /*define for src_sw field*/ 111 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 112 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 113 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 114 #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 115 116 /*define for src_ha field*/ 117 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_offset 2 118 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask 0x00000001 119 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_shift 30 120 #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_shift) 121 122 /*define for SRC_ADDR_LO word*/ 123 /*define for src_addr_31_0 field*/ 124 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 125 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 126 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 127 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 128 129 /*define for SRC_ADDR_HI word*/ 130 /*define for src_addr_63_32 field*/ 131 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 132 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 133 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 134 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 135 136 /*define for DST_ADDR_LO word*/ 137 /*define for dst_addr_31_0 field*/ 138 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 139 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 140 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 141 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 142 143 /*define for DST_ADDR_HI word*/ 144 /*define for dst_addr_63_32 field*/ 145 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 146 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 147 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 148 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 149 150 151 /* 152 ** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet 153 */ 154 155 /*define for HEADER word*/ 156 /*define for op field*/ 157 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 158 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF 159 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 160 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) 161 162 /*define for sub_op field*/ 163 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 164 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF 165 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 166 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) 167 168 /*define for broadcast field*/ 169 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 170 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 171 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 172 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) 173 174 /*define for COUNT word*/ 175 /*define for count field*/ 176 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 177 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF 178 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 179 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) 180 181 /*define for PARAMETER word*/ 182 /*define for dst2_sw field*/ 183 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 184 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 185 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 186 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) 187 188 /*define for dst2_ha field*/ 189 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_offset 2 190 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask 0x00000001 191 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_shift 14 192 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_shift) 193 194 /*define for dst1_sw field*/ 195 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 196 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 197 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 198 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) 199 200 /*define for dst1_ha field*/ 201 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_offset 2 202 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask 0x00000001 203 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_shift 22 204 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_shift) 205 206 /*define for src_sw field*/ 207 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 208 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 209 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 210 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) 211 212 /*define for src_ha field*/ 213 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_offset 2 214 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask 0x00000001 215 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_shift 30 216 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_shift) 217 218 /*define for SRC_ADDR_LO word*/ 219 /*define for src_addr_31_0 field*/ 220 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 221 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 222 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 223 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 224 225 /*define for SRC_ADDR_HI word*/ 226 /*define for src_addr_63_32 field*/ 227 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 228 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 229 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 230 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 231 232 /*define for DST1_ADDR_LO word*/ 233 /*define for dst1_addr_31_0 field*/ 234 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 235 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF 236 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 237 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) 238 239 /*define for DST1_ADDR_HI word*/ 240 /*define for dst1_addr_63_32 field*/ 241 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 242 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF 243 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 244 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) 245 246 /*define for DST2_ADDR_LO word*/ 247 /*define for dst2_addr_31_0 field*/ 248 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 249 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF 250 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 251 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) 252 253 /*define for DST2_ADDR_HI word*/ 254 /*define for dst2_addr_63_32 field*/ 255 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 256 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF 257 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 258 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) 259 260 261 /* 262 ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet 263 */ 264 265 /*define for HEADER word*/ 266 /*define for op field*/ 267 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 268 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF 269 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 270 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) 271 272 /*define for sub_op field*/ 273 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 274 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF 275 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 276 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) 277 278 /*define for elementsize field*/ 279 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 280 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 281 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 282 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) 283 284 /*define for SRC_ADDR_LO word*/ 285 /*define for src_addr_31_0 field*/ 286 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 287 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 288 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 289 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) 290 291 /*define for SRC_ADDR_HI word*/ 292 /*define for src_addr_63_32 field*/ 293 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 294 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 295 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 296 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) 297 298 /*define for DW_3 word*/ 299 /*define for src_x field*/ 300 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 301 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF 302 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 303 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) 304 305 /*define for src_y field*/ 306 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 307 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF 308 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 309 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) 310 311 /*define for DW_4 word*/ 312 /*define for src_z field*/ 313 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 314 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x000007FF 315 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 316 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) 317 318 /*define for src_pitch field*/ 319 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 320 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x00003FFF 321 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 16 322 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) 323 324 /*define for DW_5 word*/ 325 /*define for src_slice_pitch field*/ 326 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 327 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF 328 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 329 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) 330 331 /*define for DST_ADDR_LO word*/ 332 /*define for dst_addr_31_0 field*/ 333 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 334 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 335 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 336 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) 337 338 /*define for DST_ADDR_HI word*/ 339 /*define for dst_addr_63_32 field*/ 340 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 341 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 342 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 343 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) 344 345 /*define for DW_8 word*/ 346 /*define for dst_x field*/ 347 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 348 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF 349 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 350 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) 351 352 /*define for dst_y field*/ 353 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 354 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF 355 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 356 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) 357 358 /*define for DW_9 word*/ 359 /*define for dst_z field*/ 360 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 361 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x000007FF 362 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 363 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) 364 365 /*define for dst_pitch field*/ 366 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 367 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x00003FFF 368 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 16 369 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) 370 371 /*define for DW_10 word*/ 372 /*define for dst_slice_pitch field*/ 373 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 374 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF 375 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 376 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) 377 378 /*define for DW_11 word*/ 379 /*define for rect_x field*/ 380 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 381 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF 382 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 383 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) 384 385 /*define for rect_y field*/ 386 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 387 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF 388 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 389 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) 390 391 /*define for DW_12 word*/ 392 /*define for rect_z field*/ 393 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 394 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x000007FF 395 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 396 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) 397 398 /*define for dst_sw field*/ 399 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 400 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 401 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 402 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) 403 404 /*define for dst_ha field*/ 405 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_offset 12 406 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask 0x00000001 407 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_shift 22 408 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_shift) 409 410 /*define for src_sw field*/ 411 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 412 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 413 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 414 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) 415 416 /*define for src_ha field*/ 417 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_offset 12 418 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask 0x00000001 419 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_shift 30 420 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_shift) 421 422 423 /* 424 ** Definitions for SDMA_PKT_COPY_TILED packet 425 */ 426 427 /*define for HEADER word*/ 428 /*define for op field*/ 429 #define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 430 #define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF 431 #define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 432 #define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) 433 434 /*define for sub_op field*/ 435 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 436 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF 437 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 438 #define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) 439 440 /*define for detile field*/ 441 #define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 442 #define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 443 #define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 444 #define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) 445 446 /*define for TILED_ADDR_LO word*/ 447 /*define for tiled_addr_31_0 field*/ 448 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 449 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 450 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 451 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) 452 453 /*define for TILED_ADDR_HI word*/ 454 /*define for tiled_addr_63_32 field*/ 455 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 456 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 457 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 458 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) 459 460 /*define for DW_3 word*/ 461 /*define for pitch_in_tile field*/ 462 #define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_offset 3 463 #define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask 0x000007FF 464 #define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift 0 465 #define SDMA_PKT_COPY_TILED_DW_3_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask) << SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift) 466 467 /*define for height field*/ 468 #define SDMA_PKT_COPY_TILED_DW_3_height_offset 3 469 #define SDMA_PKT_COPY_TILED_DW_3_height_mask 0x00003FFF 470 #define SDMA_PKT_COPY_TILED_DW_3_height_shift 16 471 #define SDMA_PKT_COPY_TILED_DW_3_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_height_mask) << SDMA_PKT_COPY_TILED_DW_3_height_shift) 472 473 /*define for DW_4 word*/ 474 /*define for slice_pitch field*/ 475 #define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_offset 4 476 #define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask 0x003FFFFF 477 #define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift 0 478 #define SDMA_PKT_COPY_TILED_DW_4_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask) << SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift) 479 480 /*define for DW_5 word*/ 481 /*define for element_size field*/ 482 #define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 483 #define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 484 #define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 485 #define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) 486 487 /*define for array_mode field*/ 488 #define SDMA_PKT_COPY_TILED_DW_5_array_mode_offset 5 489 #define SDMA_PKT_COPY_TILED_DW_5_array_mode_mask 0x0000000F 490 #define SDMA_PKT_COPY_TILED_DW_5_array_mode_shift 3 491 #define SDMA_PKT_COPY_TILED_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_array_mode_shift) 492 493 /*define for mit_mode field*/ 494 #define SDMA_PKT_COPY_TILED_DW_5_mit_mode_offset 5 495 #define SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask 0x00000007 496 #define SDMA_PKT_COPY_TILED_DW_5_mit_mode_shift 8 497 #define SDMA_PKT_COPY_TILED_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_mit_mode_shift) 498 499 /*define for tilesplit_size field*/ 500 #define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_offset 5 501 #define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask 0x00000007 502 #define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_shift 11 503 #define SDMA_PKT_COPY_TILED_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_shift) 504 505 /*define for bank_w field*/ 506 #define SDMA_PKT_COPY_TILED_DW_5_bank_w_offset 5 507 #define SDMA_PKT_COPY_TILED_DW_5_bank_w_mask 0x00000003 508 #define SDMA_PKT_COPY_TILED_DW_5_bank_w_shift 15 509 #define SDMA_PKT_COPY_TILED_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_DW_5_bank_w_shift) 510 511 /*define for bank_h field*/ 512 #define SDMA_PKT_COPY_TILED_DW_5_bank_h_offset 5 513 #define SDMA_PKT_COPY_TILED_DW_5_bank_h_mask 0x00000003 514 #define SDMA_PKT_COPY_TILED_DW_5_bank_h_shift 18 515 #define SDMA_PKT_COPY_TILED_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_DW_5_bank_h_shift) 516 517 /*define for num_bank field*/ 518 #define SDMA_PKT_COPY_TILED_DW_5_num_bank_offset 5 519 #define SDMA_PKT_COPY_TILED_DW_5_num_bank_mask 0x00000003 520 #define SDMA_PKT_COPY_TILED_DW_5_num_bank_shift 21 521 #define SDMA_PKT_COPY_TILED_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_DW_5_num_bank_shift) 522 523 /*define for mat_aspt field*/ 524 #define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_offset 5 525 #define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask 0x00000003 526 #define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_shift 24 527 #define SDMA_PKT_COPY_TILED_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_DW_5_mat_aspt_shift) 528 529 /*define for pipe_config field*/ 530 #define SDMA_PKT_COPY_TILED_DW_5_pipe_config_offset 5 531 #define SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask 0x0000001F 532 #define SDMA_PKT_COPY_TILED_DW_5_pipe_config_shift 26 533 #define SDMA_PKT_COPY_TILED_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_DW_5_pipe_config_shift) 534 535 /*define for DW_6 word*/ 536 /*define for x field*/ 537 #define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 538 #define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF 539 #define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 540 #define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) 541 542 /*define for y field*/ 543 #define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 544 #define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF 545 #define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 546 #define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) 547 548 /*define for DW_7 word*/ 549 /*define for z field*/ 550 #define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 551 #define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00000FFF 552 #define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 553 #define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) 554 555 /*define for linear_sw field*/ 556 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 557 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 558 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 559 #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) 560 561 /*define for tile_sw field*/ 562 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 563 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 564 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 565 #define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) 566 567 /*define for LINEAR_ADDR_LO word*/ 568 /*define for linear_addr_31_0 field*/ 569 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 570 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 571 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 572 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) 573 574 /*define for LINEAR_ADDR_HI word*/ 575 /*define for linear_addr_63_32 field*/ 576 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 577 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 578 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 579 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) 580 581 /*define for LINEAR_PITCH word*/ 582 /*define for linear_pitch field*/ 583 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 584 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 585 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 586 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) 587 588 /*define for COUNT word*/ 589 /*define for count field*/ 590 #define SDMA_PKT_COPY_TILED_COUNT_count_offset 11 591 #define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x000FFFFF 592 #define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 593 #define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) 594 595 596 /* 597 ** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet 598 */ 599 600 /*define for HEADER word*/ 601 /*define for op field*/ 602 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 603 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF 604 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 605 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) 606 607 /*define for sub_op field*/ 608 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 609 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF 610 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 611 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) 612 613 /*define for videocopy field*/ 614 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 615 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 616 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 617 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) 618 619 /*define for broadcast field*/ 620 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 621 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 622 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 623 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) 624 625 /*define for TILED_ADDR_LO_0 word*/ 626 /*define for tiled_addr0_31_0 field*/ 627 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 628 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF 629 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 630 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) 631 632 /*define for TILED_ADDR_HI_0 word*/ 633 /*define for tiled_addr0_63_32 field*/ 634 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 635 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF 636 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 637 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) 638 639 /*define for TILED_ADDR_LO_1 word*/ 640 /*define for tiled_addr1_31_0 field*/ 641 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 642 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF 643 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 644 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) 645 646 /*define for TILED_ADDR_HI_1 word*/ 647 /*define for tiled_addr1_63_32 field*/ 648 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 649 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF 650 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 651 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) 652 653 /*define for DW_5 word*/ 654 /*define for pitch_in_tile field*/ 655 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_offset 5 656 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask 0x000007FF 657 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift 0 658 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift) 659 660 /*define for height field*/ 661 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_offset 5 662 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask 0x00003FFF 663 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_shift 16 664 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_shift) 665 666 /*define for DW_6 word*/ 667 /*define for slice_pitch field*/ 668 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_offset 6 669 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask 0x003FFFFF 670 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift 0 671 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift) 672 673 /*define for DW_7 word*/ 674 /*define for element_size field*/ 675 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 676 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 677 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 678 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) 679 680 /*define for array_mode field*/ 681 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_offset 7 682 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask 0x0000000F 683 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_shift 3 684 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_shift) 685 686 /*define for mit_mode field*/ 687 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_offset 7 688 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask 0x00000007 689 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_shift 8 690 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIT_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_shift) 691 692 /*define for tilesplit_size field*/ 693 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_offset 7 694 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask 0x00000007 695 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_shift 11 696 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_shift) 697 698 /*define for bank_w field*/ 699 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_offset 7 700 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask 0x00000003 701 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_shift 15 702 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_BANK_W(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_shift) 703 704 /*define for bank_h field*/ 705 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_offset 7 706 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask 0x00000003 707 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_shift 18 708 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_BANK_H(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_shift) 709 710 /*define for num_bank field*/ 711 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_offset 7 712 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask 0x00000003 713 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_shift 21 714 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_NUM_BANK(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_shift) 715 716 /*define for mat_aspt field*/ 717 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_offset 7 718 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask 0x00000003 719 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_shift 24 720 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_shift) 721 722 /*define for pipe_config field*/ 723 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_offset 7 724 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask 0x0000001F 725 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_shift 26 726 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_shift) 727 728 /*define for DW_8 word*/ 729 /*define for x field*/ 730 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 731 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF 732 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 733 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) 734 735 /*define for y field*/ 736 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 737 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF 738 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 739 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) 740 741 /*define for DW_9 word*/ 742 /*define for z field*/ 743 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 744 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00000FFF 745 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 746 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) 747 748 /*define for DW_10 word*/ 749 /*define for dst2_sw field*/ 750 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 751 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 752 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 753 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) 754 755 /*define for dst2_ha field*/ 756 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_offset 10 757 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask 0x00000001 758 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_shift 14 759 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_HA(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_shift) 760 761 /*define for linear_sw field*/ 762 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 763 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 764 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 765 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) 766 767 /*define for tile_sw field*/ 768 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 769 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 770 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 771 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) 772 773 /*define for LINEAR_ADDR_LO word*/ 774 /*define for linear_addr_31_0 field*/ 775 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 776 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 777 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 778 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) 779 780 /*define for LINEAR_ADDR_HI word*/ 781 /*define for linear_addr_63_32 field*/ 782 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 783 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 784 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 785 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) 786 787 /*define for LINEAR_PITCH word*/ 788 /*define for linear_pitch field*/ 789 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 790 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 791 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 792 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) 793 794 /*define for COUNT word*/ 795 /*define for count field*/ 796 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 14 797 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x000FFFFF 798 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 799 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) 800 801 802 /* 803 ** Definitions for SDMA_PKT_COPY_T2T packet 804 */ 805 806 /*define for HEADER word*/ 807 /*define for op field*/ 808 #define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 809 #define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF 810 #define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 811 #define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) 812 813 /*define for sub_op field*/ 814 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 815 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF 816 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 817 #define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) 818 819 /*define for SRC_ADDR_LO word*/ 820 /*define for src_addr_31_0 field*/ 821 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 822 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 823 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 824 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) 825 826 /*define for SRC_ADDR_HI word*/ 827 /*define for src_addr_63_32 field*/ 828 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 829 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 830 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 831 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) 832 833 /*define for DW_3 word*/ 834 /*define for src_x field*/ 835 #define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 836 #define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF 837 #define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 838 #define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) 839 840 /*define for src_y field*/ 841 #define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 842 #define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF 843 #define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 844 #define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) 845 846 /*define for DW_4 word*/ 847 /*define for src_z field*/ 848 #define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 849 #define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x000007FF 850 #define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 851 #define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) 852 853 /*define for src_pitch_in_tile field*/ 854 #define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_offset 4 855 #define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask 0x00000FFF 856 #define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_shift 16 857 #define SDMA_PKT_COPY_T2T_DW_4_SRC_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask) << SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_shift) 858 859 /*define for DW_5 word*/ 860 /*define for src_slice_pitch field*/ 861 #define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_offset 5 862 #define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask 0x003FFFFF 863 #define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift 0 864 #define SDMA_PKT_COPY_T2T_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift) 865 866 /*define for DW_6 word*/ 867 /*define for src_element_size field*/ 868 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 869 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 870 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 871 #define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) 872 873 /*define for src_array_mode field*/ 874 #define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_offset 6 875 #define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask 0x0000000F 876 #define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_shift 3 877 #define SDMA_PKT_COPY_T2T_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_array_mode_shift) 878 879 /*define for src_mit_mode field*/ 880 #define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_offset 6 881 #define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask 0x00000007 882 #define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_shift 8 883 #define SDMA_PKT_COPY_T2T_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_shift) 884 885 /*define for src_tilesplit_size field*/ 886 #define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_offset 6 887 #define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask 0x00000007 888 #define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_shift 11 889 #define SDMA_PKT_COPY_T2T_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_shift) 890 891 /*define for src_bank_w field*/ 892 #define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_offset 6 893 #define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask 0x00000003 894 #define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_shift 15 895 #define SDMA_PKT_COPY_T2T_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_DW_6_src_bank_w_shift) 896 897 /*define for src_bank_h field*/ 898 #define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_offset 6 899 #define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask 0x00000003 900 #define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_shift 18 901 #define SDMA_PKT_COPY_T2T_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_DW_6_src_bank_h_shift) 902 903 /*define for src_num_bank field*/ 904 #define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_offset 6 905 #define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask 0x00000003 906 #define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_shift 21 907 #define SDMA_PKT_COPY_T2T_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_DW_6_src_num_bank_shift) 908 909 /*define for src_mat_aspt field*/ 910 #define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_offset 6 911 #define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask 0x00000003 912 #define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_shift 24 913 #define SDMA_PKT_COPY_T2T_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_shift) 914 915 /*define for src_pipe_config field*/ 916 #define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_offset 6 917 #define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask 0x0000001F 918 #define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_shift 26 919 #define SDMA_PKT_COPY_T2T_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_shift) 920 921 /*define for DST_ADDR_LO word*/ 922 /*define for dst_addr_31_0 field*/ 923 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 924 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 925 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 926 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) 927 928 /*define for DST_ADDR_HI word*/ 929 /*define for dst_addr_63_32 field*/ 930 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 931 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 932 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 933 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) 934 935 /*define for DW_9 word*/ 936 /*define for dst_x field*/ 937 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 938 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF 939 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 940 #define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) 941 942 /*define for dst_y field*/ 943 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 944 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF 945 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 946 #define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) 947 948 /*define for DW_10 word*/ 949 /*define for dst_z field*/ 950 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 951 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x000007FF 952 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 953 #define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) 954 955 /*define for dst_pitch_in_tile field*/ 956 #define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_offset 10 957 #define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask 0x00000FFF 958 #define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_shift 16 959 #define SDMA_PKT_COPY_T2T_DW_10_DST_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_shift) 960 961 /*define for DW_11 word*/ 962 /*define for dst_slice_pitch field*/ 963 #define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_offset 11 964 #define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask 0x003FFFFF 965 #define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift 0 966 #define SDMA_PKT_COPY_T2T_DW_11_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift) 967 968 /*define for DW_12 word*/ 969 /*define for dst_array_mode field*/ 970 #define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_offset 12 971 #define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask 0x0000000F 972 #define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_shift 3 973 #define SDMA_PKT_COPY_T2T_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_shift) 974 975 /*define for dst_mit_mode field*/ 976 #define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_offset 12 977 #define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask 0x00000007 978 #define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_shift 8 979 #define SDMA_PKT_COPY_T2T_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_shift) 980 981 /*define for dst_tilesplit_size field*/ 982 #define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_offset 12 983 #define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask 0x00000007 984 #define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_shift 11 985 #define SDMA_PKT_COPY_T2T_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_shift) 986 987 /*define for dst_bank_w field*/ 988 #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_offset 12 989 #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask 0x00000003 990 #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_shift 15 991 #define SDMA_PKT_COPY_T2T_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_shift) 992 993 /*define for dst_bank_h field*/ 994 #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_offset 12 995 #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask 0x00000003 996 #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_shift 18 997 #define SDMA_PKT_COPY_T2T_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_shift) 998 999 /*define for dst_num_bank field*/ 1000 #define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_offset 12 1001 #define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask 0x00000003 1002 #define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_shift 21 1003 #define SDMA_PKT_COPY_T2T_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_shift) 1004 1005 /*define for dst_mat_aspt field*/ 1006 #define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_offset 12 1007 #define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask 0x00000003 1008 #define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_shift 24 1009 #define SDMA_PKT_COPY_T2T_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_shift) 1010 1011 /*define for dst_pipe_config field*/ 1012 #define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_offset 12 1013 #define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask 0x0000001F 1014 #define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_shift 26 1015 #define SDMA_PKT_COPY_T2T_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_shift) 1016 1017 /*define for DW_13 word*/ 1018 /*define for rect_x field*/ 1019 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 1020 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF 1021 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 1022 #define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) 1023 1024 /*define for rect_y field*/ 1025 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 1026 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF 1027 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 1028 #define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) 1029 1030 /*define for DW_14 word*/ 1031 /*define for rect_z field*/ 1032 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 1033 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x000007FF 1034 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 1035 #define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) 1036 1037 /*define for dst_sw field*/ 1038 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 1039 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 1040 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 1041 #define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) 1042 1043 /*define for src_sw field*/ 1044 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 1045 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 1046 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 1047 #define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) 1048 1049 1050 /* 1051 ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet 1052 */ 1053 1054 /*define for HEADER word*/ 1055 /*define for op field*/ 1056 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 1057 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF 1058 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 1059 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) 1060 1061 /*define for sub_op field*/ 1062 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 1063 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF 1064 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 1065 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) 1066 1067 /*define for detile field*/ 1068 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 1069 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 1070 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 1071 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) 1072 1073 /*define for TILED_ADDR_LO word*/ 1074 /*define for tiled_addr_31_0 field*/ 1075 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 1076 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 1077 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 1078 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) 1079 1080 /*define for TILED_ADDR_HI word*/ 1081 /*define for tiled_addr_63_32 field*/ 1082 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 1083 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 1084 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 1085 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) 1086 1087 /*define for DW_3 word*/ 1088 /*define for tiled_x field*/ 1089 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 1090 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF 1091 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 1092 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) 1093 1094 /*define for tiled_y field*/ 1095 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 1096 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF 1097 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 1098 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) 1099 1100 /*define for DW_4 word*/ 1101 /*define for tiled_z field*/ 1102 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 1103 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x000007FF 1104 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 1105 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) 1106 1107 /*define for pitch_in_tile field*/ 1108 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_offset 4 1109 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask 0x00000FFF 1110 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_shift 16 1111 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_shift) 1112 1113 /*define for DW_5 word*/ 1114 /*define for slice_pitch field*/ 1115 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_offset 5 1116 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask 0x003FFFFF 1117 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift 0 1118 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift) 1119 1120 /*define for DW_6 word*/ 1121 /*define for element_size field*/ 1122 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 1123 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 1124 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 1125 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) 1126 1127 /*define for array_mode field*/ 1128 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_offset 6 1129 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask 0x0000000F 1130 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_shift 3 1131 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_shift) 1132 1133 /*define for mit_mode field*/ 1134 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_offset 6 1135 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask 0x00000007 1136 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_shift 8 1137 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_shift) 1138 1139 /*define for tilesplit_size field*/ 1140 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_offset 6 1141 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask 0x00000007 1142 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_shift 11 1143 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_shift) 1144 1145 /*define for bank_w field*/ 1146 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_offset 6 1147 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask 0x00000003 1148 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_shift 15 1149 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_shift) 1150 1151 /*define for bank_h field*/ 1152 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_offset 6 1153 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask 0x00000003 1154 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_shift 18 1155 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_shift) 1156 1157 /*define for num_bank field*/ 1158 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_offset 6 1159 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask 0x00000003 1160 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_shift 21 1161 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_shift) 1162 1163 /*define for mat_aspt field*/ 1164 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_offset 6 1165 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask 0x00000003 1166 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_shift 24 1167 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_shift) 1168 1169 /*define for pipe_config field*/ 1170 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_offset 6 1171 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask 0x0000001F 1172 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_shift 26 1173 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_shift) 1174 1175 /*define for LINEAR_ADDR_LO word*/ 1176 /*define for linear_addr_31_0 field*/ 1177 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 1178 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1179 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1180 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1181 1182 /*define for LINEAR_ADDR_HI word*/ 1183 /*define for linear_addr_63_32 field*/ 1184 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 1185 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1186 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1187 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1188 1189 /*define for DW_9 word*/ 1190 /*define for linear_x field*/ 1191 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 1192 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF 1193 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 1194 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) 1195 1196 /*define for linear_y field*/ 1197 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 1198 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF 1199 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 1200 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) 1201 1202 /*define for DW_10 word*/ 1203 /*define for linear_z field*/ 1204 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 1205 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x000007FF 1206 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 1207 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) 1208 1209 /*define for linear_pitch field*/ 1210 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 1211 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF 1212 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 1213 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) 1214 1215 /*define for DW_11 word*/ 1216 /*define for linear_slice_pitch field*/ 1217 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 1218 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF 1219 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 1220 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) 1221 1222 /*define for DW_12 word*/ 1223 /*define for rect_x field*/ 1224 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 1225 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF 1226 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 1227 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) 1228 1229 /*define for rect_y field*/ 1230 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 1231 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF 1232 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 1233 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) 1234 1235 /*define for DW_13 word*/ 1236 /*define for rect_z field*/ 1237 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 1238 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x000007FF 1239 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 1240 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) 1241 1242 /*define for linear_sw field*/ 1243 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 1244 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 1245 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 1246 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) 1247 1248 /*define for tile_sw field*/ 1249 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 1250 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 1251 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 1252 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) 1253 1254 1255 /* 1256 ** Definitions for SDMA_PKT_COPY_STRUCT packet 1257 */ 1258 1259 /*define for HEADER word*/ 1260 /*define for op field*/ 1261 #define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 1262 #define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF 1263 #define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 1264 #define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) 1265 1266 /*define for sub_op field*/ 1267 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 1268 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF 1269 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 1270 #define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) 1271 1272 /*define for detile field*/ 1273 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 1274 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 1275 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 1276 #define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) 1277 1278 /*define for SB_ADDR_LO word*/ 1279 /*define for sb_addr_31_0 field*/ 1280 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 1281 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF 1282 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 1283 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) 1284 1285 /*define for SB_ADDR_HI word*/ 1286 /*define for sb_addr_63_32 field*/ 1287 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 1288 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF 1289 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 1290 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) 1291 1292 /*define for START_INDEX word*/ 1293 /*define for start_index field*/ 1294 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 1295 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF 1296 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 1297 #define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) 1298 1299 /*define for COUNT word*/ 1300 /*define for count field*/ 1301 #define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 1302 #define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF 1303 #define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 1304 #define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) 1305 1306 /*define for DW_5 word*/ 1307 /*define for stride field*/ 1308 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 1309 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF 1310 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 1311 #define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) 1312 1313 /*define for struct_sw field*/ 1314 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 1315 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 1316 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 16 1317 #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) 1318 1319 /*define for struct_ha field*/ 1320 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_offset 5 1321 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask 0x00000001 1322 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_shift 22 1323 #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_HA(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_shift) 1324 1325 /*define for linear_sw field*/ 1326 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 1327 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 1328 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 24 1329 #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) 1330 1331 /*define for linear_ha field*/ 1332 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_offset 5 1333 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask 0x00000001 1334 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_shift 30 1335 #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_HA(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_shift) 1336 1337 /*define for LINEAR_ADDR_LO word*/ 1338 /*define for linear_addr_31_0 field*/ 1339 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 1340 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1341 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1342 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1343 1344 /*define for LINEAR_ADDR_HI word*/ 1345 /*define for linear_addr_63_32 field*/ 1346 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 1347 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1348 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1349 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1350 1351 1352 /* 1353 ** Definitions for SDMA_PKT_WRITE_UNTILED packet 1354 */ 1355 1356 /*define for HEADER word*/ 1357 /*define for op field*/ 1358 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 1359 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF 1360 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 1361 #define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) 1362 1363 /*define for sub_op field*/ 1364 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 1365 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF 1366 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 1367 #define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) 1368 1369 /*define for DST_ADDR_LO word*/ 1370 /*define for dst_addr_31_0 field*/ 1371 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 1372 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1373 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 1374 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) 1375 1376 /*define for DST_ADDR_HI word*/ 1377 /*define for dst_addr_63_32 field*/ 1378 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 1379 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1380 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 1381 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) 1382 1383 /*define for DW_3 word*/ 1384 /*define for count field*/ 1385 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 1386 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x003FFFFF 1387 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 1388 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) 1389 1390 /*define for sw field*/ 1391 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 1392 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 1393 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 1394 #define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) 1395 1396 /*define for DATA0 word*/ 1397 /*define for data0 field*/ 1398 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 1399 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF 1400 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 1401 #define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) 1402 1403 1404 /* 1405 ** Definitions for SDMA_PKT_WRITE_TILED packet 1406 */ 1407 1408 /*define for HEADER word*/ 1409 /*define for op field*/ 1410 #define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 1411 #define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF 1412 #define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 1413 #define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) 1414 1415 /*define for sub_op field*/ 1416 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 1417 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF 1418 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 1419 #define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) 1420 1421 /*define for DST_ADDR_LO word*/ 1422 /*define for dst_addr_31_0 field*/ 1423 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 1424 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1425 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 1426 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) 1427 1428 /*define for DST_ADDR_HI word*/ 1429 /*define for dst_addr_63_32 field*/ 1430 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 1431 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1432 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 1433 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) 1434 1435 /*define for DW_3 word*/ 1436 /*define for pitch_in_tile field*/ 1437 #define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_offset 3 1438 #define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask 0x000007FF 1439 #define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift 0 1440 #define SDMA_PKT_WRITE_TILED_DW_3_PITCH_IN_TILE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask) << SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift) 1441 1442 /*define for height field*/ 1443 #define SDMA_PKT_WRITE_TILED_DW_3_height_offset 3 1444 #define SDMA_PKT_WRITE_TILED_DW_3_height_mask 0x00003FFF 1445 #define SDMA_PKT_WRITE_TILED_DW_3_height_shift 16 1446 #define SDMA_PKT_WRITE_TILED_DW_3_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_height_mask) << SDMA_PKT_WRITE_TILED_DW_3_height_shift) 1447 1448 /*define for DW_4 word*/ 1449 /*define for slice_pitch field*/ 1450 #define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_offset 4 1451 #define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask 0x003FFFFF 1452 #define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift 0 1453 #define SDMA_PKT_WRITE_TILED_DW_4_SLICE_PITCH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask) << SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift) 1454 1455 /*define for DW_5 word*/ 1456 /*define for element_size field*/ 1457 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 1458 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 1459 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 1460 #define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) 1461 1462 /*define for array_mode field*/ 1463 #define SDMA_PKT_WRITE_TILED_DW_5_array_mode_offset 5 1464 #define SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask 0x0000000F 1465 #define SDMA_PKT_WRITE_TILED_DW_5_array_mode_shift 3 1466 #define SDMA_PKT_WRITE_TILED_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_array_mode_shift) 1467 1468 /*define for mit_mode field*/ 1469 #define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_offset 5 1470 #define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask 0x00000007 1471 #define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_shift 8 1472 #define SDMA_PKT_WRITE_TILED_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_mit_mode_shift) 1473 1474 /*define for tilesplit_size field*/ 1475 #define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_offset 5 1476 #define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask 0x00000007 1477 #define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_shift 11 1478 #define SDMA_PKT_WRITE_TILED_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_shift) 1479 1480 /*define for bank_w field*/ 1481 #define SDMA_PKT_WRITE_TILED_DW_5_bank_w_offset 5 1482 #define SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask 0x00000003 1483 #define SDMA_PKT_WRITE_TILED_DW_5_bank_w_shift 15 1484 #define SDMA_PKT_WRITE_TILED_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_DW_5_bank_w_shift) 1485 1486 /*define for bank_h field*/ 1487 #define SDMA_PKT_WRITE_TILED_DW_5_bank_h_offset 5 1488 #define SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask 0x00000003 1489 #define SDMA_PKT_WRITE_TILED_DW_5_bank_h_shift 18 1490 #define SDMA_PKT_WRITE_TILED_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_DW_5_bank_h_shift) 1491 1492 /*define for num_bank field*/ 1493 #define SDMA_PKT_WRITE_TILED_DW_5_num_bank_offset 5 1494 #define SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask 0x00000003 1495 #define SDMA_PKT_WRITE_TILED_DW_5_num_bank_shift 21 1496 #define SDMA_PKT_WRITE_TILED_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_DW_5_num_bank_shift) 1497 1498 /*define for mat_aspt field*/ 1499 #define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_offset 5 1500 #define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask 0x00000003 1501 #define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_shift 24 1502 #define SDMA_PKT_WRITE_TILED_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_shift) 1503 1504 /*define for pipe_config field*/ 1505 #define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_offset 5 1506 #define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask 0x0000001F 1507 #define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_shift 26 1508 #define SDMA_PKT_WRITE_TILED_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_DW_5_pipe_config_shift) 1509 1510 /*define for DW_6 word*/ 1511 /*define for x field*/ 1512 #define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 1513 #define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF 1514 #define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 1515 #define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) 1516 1517 /*define for y field*/ 1518 #define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 1519 #define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF 1520 #define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 1521 #define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) 1522 1523 /*define for DW_7 word*/ 1524 /*define for z field*/ 1525 #define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 1526 #define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00000FFF 1527 #define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 1528 #define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) 1529 1530 /*define for sw field*/ 1531 #define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 1532 #define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 1533 #define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 1534 #define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) 1535 1536 /*define for COUNT word*/ 1537 /*define for count field*/ 1538 #define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 1539 #define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x003FFFFF 1540 #define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 1541 #define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) 1542 1543 /*define for DATA0 word*/ 1544 /*define for data0 field*/ 1545 #define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 1546 #define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF 1547 #define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 1548 #define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) 1549 1550 1551 /* 1552 ** Definitions for SDMA_PKT_WRITE_INCR packet 1553 */ 1554 1555 /*define for HEADER word*/ 1556 /*define for op field*/ 1557 #define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 1558 #define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF 1559 #define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 1560 #define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) 1561 1562 /*define for sub_op field*/ 1563 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 1564 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF 1565 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 1566 #define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) 1567 1568 /*define for DST_ADDR_LO word*/ 1569 /*define for dst_addr_31_0 field*/ 1570 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 1571 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1572 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 1573 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) 1574 1575 /*define for DST_ADDR_HI word*/ 1576 /*define for dst_addr_63_32 field*/ 1577 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 1578 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1579 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 1580 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) 1581 1582 /*define for MASK_DW0 word*/ 1583 /*define for mask_dw0 field*/ 1584 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 1585 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 1586 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 1587 #define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) 1588 1589 /*define for MASK_DW1 word*/ 1590 /*define for mask_dw1 field*/ 1591 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 1592 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 1593 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 1594 #define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) 1595 1596 /*define for INIT_DW0 word*/ 1597 /*define for init_dw0 field*/ 1598 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 1599 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF 1600 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 1601 #define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) 1602 1603 /*define for INIT_DW1 word*/ 1604 /*define for init_dw1 field*/ 1605 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 1606 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF 1607 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 1608 #define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) 1609 1610 /*define for INCR_DW0 word*/ 1611 /*define for incr_dw0 field*/ 1612 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 1613 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF 1614 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 1615 #define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) 1616 1617 /*define for INCR_DW1 word*/ 1618 /*define for incr_dw1 field*/ 1619 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 1620 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF 1621 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 1622 #define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) 1623 1624 /*define for COUNT word*/ 1625 /*define for count field*/ 1626 #define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 1627 #define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF 1628 #define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 1629 #define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) 1630 1631 1632 /* 1633 ** Definitions for SDMA_PKT_INDIRECT packet 1634 */ 1635 1636 /*define for HEADER word*/ 1637 /*define for op field*/ 1638 #define SDMA_PKT_INDIRECT_HEADER_op_offset 0 1639 #define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF 1640 #define SDMA_PKT_INDIRECT_HEADER_op_shift 0 1641 #define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) 1642 1643 /*define for sub_op field*/ 1644 #define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 1645 #define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF 1646 #define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 1647 #define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) 1648 1649 /*define for vmid field*/ 1650 #define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 1651 #define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F 1652 #define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 1653 #define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) 1654 1655 /*define for BASE_LO word*/ 1656 /*define for ib_base_31_0 field*/ 1657 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 1658 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF 1659 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 1660 #define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) 1661 1662 /*define for BASE_HI word*/ 1663 /*define for ib_base_63_32 field*/ 1664 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 1665 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF 1666 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 1667 #define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) 1668 1669 /*define for IB_SIZE word*/ 1670 /*define for ib_size field*/ 1671 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 1672 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF 1673 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 1674 #define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) 1675 1676 /*define for CSA_ADDR_LO word*/ 1677 /*define for csa_addr_31_0 field*/ 1678 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 1679 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF 1680 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 1681 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) 1682 1683 /*define for CSA_ADDR_HI word*/ 1684 /*define for csa_addr_63_32 field*/ 1685 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 1686 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF 1687 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 1688 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) 1689 1690 1691 /* 1692 ** Definitions for SDMA_PKT_SEMAPHORE packet 1693 */ 1694 1695 /*define for HEADER word*/ 1696 /*define for op field*/ 1697 #define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 1698 #define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF 1699 #define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 1700 #define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) 1701 1702 /*define for sub_op field*/ 1703 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 1704 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF 1705 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 1706 #define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) 1707 1708 /*define for write_one field*/ 1709 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 1710 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 1711 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 1712 #define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) 1713 1714 /*define for signal field*/ 1715 #define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 1716 #define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 1717 #define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 1718 #define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) 1719 1720 /*define for mailbox field*/ 1721 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 1722 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 1723 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 1724 #define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) 1725 1726 /*define for ADDR_LO word*/ 1727 /*define for addr_31_0 field*/ 1728 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 1729 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 1730 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 1731 #define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) 1732 1733 /*define for ADDR_HI word*/ 1734 /*define for addr_63_32 field*/ 1735 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 1736 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 1737 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 1738 #define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) 1739 1740 1741 /* 1742 ** Definitions for SDMA_PKT_FENCE packet 1743 */ 1744 1745 /*define for HEADER word*/ 1746 /*define for op field*/ 1747 #define SDMA_PKT_FENCE_HEADER_op_offset 0 1748 #define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF 1749 #define SDMA_PKT_FENCE_HEADER_op_shift 0 1750 #define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) 1751 1752 /*define for sub_op field*/ 1753 #define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 1754 #define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF 1755 #define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 1756 #define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) 1757 1758 /*define for ADDR_LO word*/ 1759 /*define for addr_31_0 field*/ 1760 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 1761 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 1762 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 1763 #define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) 1764 1765 /*define for ADDR_HI word*/ 1766 /*define for addr_63_32 field*/ 1767 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 1768 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 1769 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 1770 #define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) 1771 1772 /*define for DATA word*/ 1773 /*define for data field*/ 1774 #define SDMA_PKT_FENCE_DATA_data_offset 3 1775 #define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF 1776 #define SDMA_PKT_FENCE_DATA_data_shift 0 1777 #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) 1778 1779 1780 /* 1781 ** Definitions for SDMA_PKT_SRBM_WRITE packet 1782 */ 1783 1784 /*define for HEADER word*/ 1785 /*define for op field*/ 1786 #define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 1787 #define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF 1788 #define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 1789 #define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) 1790 1791 /*define for sub_op field*/ 1792 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 1793 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF 1794 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 1795 #define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) 1796 1797 /*define for byte_en field*/ 1798 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 1799 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F 1800 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 1801 #define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) 1802 1803 /*define for ADDR word*/ 1804 /*define for addr field*/ 1805 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 1806 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0000FFFF 1807 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 1808 #define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) 1809 1810 /*define for DATA word*/ 1811 /*define for data field*/ 1812 #define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 1813 #define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF 1814 #define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 1815 #define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) 1816 1817 1818 /* 1819 ** Definitions for SDMA_PKT_PRE_EXE packet 1820 */ 1821 1822 /*define for HEADER word*/ 1823 /*define for op field*/ 1824 #define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 1825 #define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF 1826 #define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 1827 #define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) 1828 1829 /*define for sub_op field*/ 1830 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 1831 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF 1832 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 1833 #define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) 1834 1835 /*define for dev_sel field*/ 1836 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 1837 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF 1838 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 1839 #define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) 1840 1841 /*define for EXEC_COUNT word*/ 1842 /*define for exec_count field*/ 1843 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 1844 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 1845 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 1846 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) 1847 1848 1849 /* 1850 ** Definitions for SDMA_PKT_COND_EXE packet 1851 */ 1852 1853 /*define for HEADER word*/ 1854 /*define for op field*/ 1855 #define SDMA_PKT_COND_EXE_HEADER_op_offset 0 1856 #define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF 1857 #define SDMA_PKT_COND_EXE_HEADER_op_shift 0 1858 #define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) 1859 1860 /*define for sub_op field*/ 1861 #define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 1862 #define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF 1863 #define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 1864 #define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) 1865 1866 /*define for ADDR_LO word*/ 1867 /*define for addr_31_0 field*/ 1868 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 1869 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 1870 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 1871 #define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) 1872 1873 /*define for ADDR_HI word*/ 1874 /*define for addr_63_32 field*/ 1875 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 1876 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 1877 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 1878 #define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) 1879 1880 /*define for REFERENCE word*/ 1881 /*define for reference field*/ 1882 #define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 1883 #define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF 1884 #define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 1885 #define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) 1886 1887 /*define for EXEC_COUNT word*/ 1888 /*define for exec_count field*/ 1889 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 1890 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 1891 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 1892 #define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) 1893 1894 1895 /* 1896 ** Definitions for SDMA_PKT_CONSTANT_FILL packet 1897 */ 1898 1899 /*define for HEADER word*/ 1900 /*define for op field*/ 1901 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 1902 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF 1903 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 1904 #define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) 1905 1906 /*define for sub_op field*/ 1907 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 1908 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF 1909 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 1910 #define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) 1911 1912 /*define for sw field*/ 1913 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 1914 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 1915 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 1916 #define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) 1917 1918 /*define for fillsize field*/ 1919 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 1920 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 1921 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 1922 #define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) 1923 1924 /*define for DST_ADDR_LO word*/ 1925 /*define for dst_addr_31_0 field*/ 1926 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 1927 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1928 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 1929 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) 1930 1931 /*define for DST_ADDR_HI word*/ 1932 /*define for dst_addr_63_32 field*/ 1933 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 1934 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1935 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 1936 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) 1937 1938 /*define for DATA word*/ 1939 /*define for src_data_31_0 field*/ 1940 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 1941 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF 1942 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 1943 #define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) 1944 1945 /*define for COUNT word*/ 1946 /*define for count field*/ 1947 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 1948 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF 1949 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 1950 #define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) 1951 1952 1953 /* 1954 ** Definitions for SDMA_PKT_POLL_REGMEM packet 1955 */ 1956 1957 /*define for HEADER word*/ 1958 /*define for op field*/ 1959 #define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 1960 #define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF 1961 #define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 1962 #define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) 1963 1964 /*define for sub_op field*/ 1965 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 1966 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF 1967 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 1968 #define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) 1969 1970 /*define for hdp_flush field*/ 1971 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 1972 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 1973 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 1974 #define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) 1975 1976 /*define for func field*/ 1977 #define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 1978 #define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 1979 #define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 1980 #define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) 1981 1982 /*define for mem_poll field*/ 1983 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 1984 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 1985 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 1986 #define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) 1987 1988 /*define for ADDR_LO word*/ 1989 /*define for addr_31_0 field*/ 1990 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 1991 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 1992 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 1993 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) 1994 1995 /*define for ADDR_HI word*/ 1996 /*define for addr_63_32 field*/ 1997 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 1998 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 1999 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 2000 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) 2001 2002 /*define for VALUE word*/ 2003 /*define for value field*/ 2004 #define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 2005 #define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF 2006 #define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 2007 #define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) 2008 2009 /*define for MASK word*/ 2010 /*define for mask field*/ 2011 #define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 2012 #define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF 2013 #define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 2014 #define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) 2015 2016 /*define for DW5 word*/ 2017 /*define for interval field*/ 2018 #define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 2019 #define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF 2020 #define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 2021 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) 2022 2023 /*define for retry_count field*/ 2024 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 2025 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF 2026 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 2027 #define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) 2028 2029 2030 /* 2031 ** Definitions for SDMA_PKT_ATOMIC packet 2032 */ 2033 2034 /*define for HEADER word*/ 2035 /*define for op field*/ 2036 #define SDMA_PKT_ATOMIC_HEADER_op_offset 0 2037 #define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF 2038 #define SDMA_PKT_ATOMIC_HEADER_op_shift 0 2039 #define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) 2040 2041 /*define for loop field*/ 2042 #define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 2043 #define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 2044 #define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 2045 #define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) 2046 2047 /*define for atomic_op field*/ 2048 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 2049 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F 2050 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 2051 #define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) 2052 2053 /*define for ADDR_LO word*/ 2054 /*define for addr_31_0 field*/ 2055 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 2056 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 2057 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 2058 #define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) 2059 2060 /*define for ADDR_HI word*/ 2061 /*define for addr_63_32 field*/ 2062 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 2063 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 2064 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 2065 #define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) 2066 2067 /*define for SRC_DATA_LO word*/ 2068 /*define for src_data_31_0 field*/ 2069 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 2070 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF 2071 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 2072 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) 2073 2074 /*define for SRC_DATA_HI word*/ 2075 /*define for src_data_63_32 field*/ 2076 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 2077 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF 2078 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 2079 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) 2080 2081 /*define for CMP_DATA_LO word*/ 2082 /*define for cmp_data_31_0 field*/ 2083 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 2084 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF 2085 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 2086 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) 2087 2088 /*define for CMP_DATA_HI word*/ 2089 /*define for cmp_data_63_32 field*/ 2090 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 2091 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF 2092 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 2093 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) 2094 2095 /*define for LOOP_INTERVAL word*/ 2096 /*define for loop_interval field*/ 2097 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 2098 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF 2099 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 2100 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) 2101 2102 2103 /* 2104 ** Definitions for SDMA_PKT_TIMESTAMP_SET packet 2105 */ 2106 2107 /*define for HEADER word*/ 2108 /*define for op field*/ 2109 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 2110 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF 2111 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 2112 #define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) 2113 2114 /*define for sub_op field*/ 2115 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 2116 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF 2117 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 2118 #define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) 2119 2120 /*define for INIT_DATA_LO word*/ 2121 /*define for init_data_31_0 field*/ 2122 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 2123 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF 2124 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 2125 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) 2126 2127 /*define for INIT_DATA_HI word*/ 2128 /*define for init_data_63_32 field*/ 2129 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 2130 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF 2131 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 2132 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) 2133 2134 2135 /* 2136 ** Definitions for SDMA_PKT_TIMESTAMP_GET packet 2137 */ 2138 2139 /*define for HEADER word*/ 2140 /*define for op field*/ 2141 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 2142 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF 2143 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 2144 #define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) 2145 2146 /*define for sub_op field*/ 2147 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 2148 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF 2149 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 2150 #define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) 2151 2152 /*define for WRITE_ADDR_LO word*/ 2153 /*define for write_addr_31_3 field*/ 2154 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 2155 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 2156 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 2157 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) 2158 2159 /*define for WRITE_ADDR_HI word*/ 2160 /*define for write_addr_63_32 field*/ 2161 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 2162 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 2163 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 2164 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) 2165 2166 2167 /* 2168 ** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet 2169 */ 2170 2171 /*define for HEADER word*/ 2172 /*define for op field*/ 2173 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 2174 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF 2175 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 2176 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) 2177 2178 /*define for sub_op field*/ 2179 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 2180 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF 2181 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 2182 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) 2183 2184 /*define for WRITE_ADDR_LO word*/ 2185 /*define for write_addr_31_3 field*/ 2186 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 2187 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 2188 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 2189 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) 2190 2191 /*define for WRITE_ADDR_HI word*/ 2192 /*define for write_addr_63_32 field*/ 2193 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 2194 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 2195 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 2196 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) 2197 2198 2199 /* 2200 ** Definitions for SDMA_PKT_TRAP packet 2201 */ 2202 2203 /*define for HEADER word*/ 2204 /*define for op field*/ 2205 #define SDMA_PKT_TRAP_HEADER_op_offset 0 2206 #define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF 2207 #define SDMA_PKT_TRAP_HEADER_op_shift 0 2208 #define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) 2209 2210 /*define for sub_op field*/ 2211 #define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 2212 #define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF 2213 #define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 2214 #define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) 2215 2216 /*define for INT_CONTEXT word*/ 2217 /*define for int_context field*/ 2218 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 2219 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 2220 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 2221 #define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) 2222 2223 2224 /* 2225 ** Definitions for SDMA_PKT_NOP packet 2226 */ 2227 2228 /*define for HEADER word*/ 2229 /*define for op field*/ 2230 #define SDMA_PKT_NOP_HEADER_op_offset 0 2231 #define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF 2232 #define SDMA_PKT_NOP_HEADER_op_shift 0 2233 #define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) 2234 2235 /*define for sub_op field*/ 2236 #define SDMA_PKT_NOP_HEADER_sub_op_offset 0 2237 #define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF 2238 #define SDMA_PKT_NOP_HEADER_sub_op_shift 8 2239 #define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) 2240 2241 /*define for count field*/ 2242 #define SDMA_PKT_NOP_HEADER_count_offset 0 2243 #define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF 2244 #define SDMA_PKT_NOP_HEADER_count_shift 16 2245 #define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) 2246 2247 #endif /* __TONGA_SDMA_PKT_OPEN_H_ */ 2248
Indexes created Sat Sep 20 22:09:52 GMT 2025