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      1 /*	$NetBSD: umc_v6_1.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2019 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 #ifndef __UMC_V6_1_H__
     26 #define __UMC_V6_1_H__
     27 
     28 #include "soc15_common.h"
     29 #include "amdgpu.h"
     30 
     31 /* HBM  Memory Channel Width */
     32 #define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH	128
     33 /* number of umc channel instance with memory map register access */
     34 #define UMC_V6_1_CHANNEL_INSTANCE_NUM		4
     35 /* number of umc instance with memory map register access */
     36 #define UMC_V6_1_UMC_INSTANCE_NUM		8
     37 /* total channel instances in one umc block */
     38 #define UMC_V6_1_TOTAL_CHANNEL_NUM	(UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM)
     39 /* UMC regiser per channel offset */
     40 #define UMC_V6_1_PER_CHANNEL_OFFSET_VG20	0x800
     41 #define UMC_V6_1_PER_CHANNEL_OFFSET_ARCT	0x400
     42 
     43 /* EccErrCnt max value */
     44 #define UMC_V6_1_CE_CNT_MAX		0xffff
     45 /* umc ce interrupt threshold */
     46 #define UMC_V6_1_CE_INT_THRESHOLD	0xffff
     47 /* umc ce count initial value */
     48 #define UMC_V6_1_CE_CNT_INIT	(UMC_V6_1_CE_CNT_MAX - UMC_V6_1_CE_INT_THRESHOLD)
     49 
     50 extern const struct amdgpu_umc_funcs umc_v6_1_funcs;
     51 extern const uint32_t
     52 	umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM];
     53 
     54 #endif
     55