1 /* $NetBSD: vega10_sdma_pkt_open.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef __VEGA10_SDMA_PKT_OPEN_H_ 26 #define __VEGA10_SDMA_PKT_OPEN_H_ 27 28 #define SDMA_OP_NOP 0 29 #define SDMA_OP_COPY 1 30 #define SDMA_OP_WRITE 2 31 #define SDMA_OP_INDIRECT 4 32 #define SDMA_OP_FENCE 5 33 #define SDMA_OP_TRAP 6 34 #define SDMA_OP_SEM 7 35 #define SDMA_OP_POLL_REGMEM 8 36 #define SDMA_OP_COND_EXE 9 37 #define SDMA_OP_ATOMIC 10 38 #define SDMA_OP_CONST_FILL 11 39 #define SDMA_OP_PTEPDE 12 40 #define SDMA_OP_TIMESTAMP 13 41 #define SDMA_OP_SRBM_WRITE 14 42 #define SDMA_OP_PRE_EXE 15 43 #define SDMA_OP_DUMMY_TRAP 16 44 #define SDMA_SUBOP_TIMESTAMP_SET 0 45 #define SDMA_SUBOP_TIMESTAMP_GET 1 46 #define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 47 #define SDMA_SUBOP_COPY_LINEAR 0 48 #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 49 #define SDMA_SUBOP_COPY_TILED 1 50 #define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 51 #define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 52 #define SDMA_SUBOP_COPY_SOA 3 53 #define SDMA_SUBOP_COPY_DIRTY_PAGE 7 54 #define SDMA_SUBOP_COPY_LINEAR_PHY 8 55 #define SDMA_SUBOP_WRITE_LINEAR 0 56 #define SDMA_SUBOP_WRITE_TILED 1 57 #define SDMA_SUBOP_PTEPDE_GEN 0 58 #define SDMA_SUBOP_PTEPDE_COPY 1 59 #define SDMA_SUBOP_PTEPDE_RMW 2 60 #define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 3 61 #define SDMA_SUBOP_DATA_FILL_MULTI 1 62 #define SDMA_SUBOP_POLL_REG_WRITE_MEM 1 63 #define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2 64 #define SDMA_SUBOP_POLL_MEM_VERIFY 3 65 #define HEADER_AGENT_DISPATCH 4 66 #define HEADER_BARRIER 5 67 #define SDMA_OP_AQL_COPY 0 68 #define SDMA_OP_AQL_BARRIER_OR 0 69 70 /*define for op field*/ 71 #define SDMA_PKT_HEADER_op_offset 0 72 #define SDMA_PKT_HEADER_op_mask 0x000000FF 73 #define SDMA_PKT_HEADER_op_shift 0 74 #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) 75 76 /*define for sub_op field*/ 77 #define SDMA_PKT_HEADER_sub_op_offset 0 78 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF 79 #define SDMA_PKT_HEADER_sub_op_shift 8 80 #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) 81 82 83 /* 84 ** Definitions for SDMA_PKT_COPY_LINEAR packet 85 */ 86 87 /*define for HEADER word*/ 88 /*define for op field*/ 89 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 90 #define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF 91 #define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 92 #define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) 93 94 /*define for sub_op field*/ 95 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 96 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF 97 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 98 #define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) 99 100 /*define for encrypt field*/ 101 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0 102 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001 103 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16 104 #define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) 105 106 /*define for tmz field*/ 107 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0 108 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001 109 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18 110 #define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) 111 112 /*define for broadcast field*/ 113 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 114 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 115 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 116 #define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) 117 118 /*define for COUNT word*/ 119 /*define for count field*/ 120 #define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 121 #define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF 122 #define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 123 #define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) 124 125 /*define for PARAMETER word*/ 126 /*define for dst_sw field*/ 127 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 128 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 129 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 130 #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 131 132 /*define for src_sw field*/ 133 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 134 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 135 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 136 #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 137 138 /*define for SRC_ADDR_LO word*/ 139 /*define for src_addr_31_0 field*/ 140 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 141 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 142 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 143 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 144 145 /*define for SRC_ADDR_HI word*/ 146 /*define for src_addr_63_32 field*/ 147 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 148 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 149 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 150 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 151 152 /*define for DST_ADDR_LO word*/ 153 /*define for dst_addr_31_0 field*/ 154 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 155 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 156 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 157 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 158 159 /*define for DST_ADDR_HI word*/ 160 /*define for dst_addr_63_32 field*/ 161 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 162 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 163 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 164 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 165 166 167 /* 168 ** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet 169 */ 170 171 /*define for HEADER word*/ 172 /*define for op field*/ 173 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0 174 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF 175 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0 176 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) 177 178 /*define for sub_op field*/ 179 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0 180 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF 181 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8 182 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) 183 184 /*define for tmz field*/ 185 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0 186 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001 187 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18 188 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) 189 190 /*define for all field*/ 191 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0 192 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001 193 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31 194 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) 195 196 /*define for COUNT word*/ 197 /*define for count field*/ 198 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1 199 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF 200 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0 201 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) 202 203 /*define for PARAMETER word*/ 204 /*define for dst_sw field*/ 205 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2 206 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003 207 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 16 208 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) 209 210 /*define for dst_gcc field*/ 211 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2 212 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001 213 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19 214 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) 215 216 /*define for dst_sys field*/ 217 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2 218 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001 219 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20 220 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) 221 222 /*define for dst_snoop field*/ 223 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2 224 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001 225 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22 226 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) 227 228 /*define for dst_gpa field*/ 229 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2 230 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001 231 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23 232 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) 233 234 /*define for src_sw field*/ 235 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2 236 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003 237 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24 238 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) 239 240 /*define for src_sys field*/ 241 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2 242 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001 243 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28 244 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) 245 246 /*define for src_snoop field*/ 247 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2 248 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001 249 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30 250 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) 251 252 /*define for src_gpa field*/ 253 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2 254 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001 255 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31 256 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) 257 258 /*define for SRC_ADDR_LO word*/ 259 /*define for src_addr_31_0 field*/ 260 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3 261 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 262 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0 263 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) 264 265 /*define for SRC_ADDR_HI word*/ 266 /*define for src_addr_63_32 field*/ 267 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4 268 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 269 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0 270 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) 271 272 /*define for DST_ADDR_LO word*/ 273 /*define for dst_addr_31_0 field*/ 274 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5 275 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 276 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0 277 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) 278 279 /*define for DST_ADDR_HI word*/ 280 /*define for dst_addr_63_32 field*/ 281 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6 282 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 283 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0 284 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) 285 286 287 /* 288 ** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet 289 */ 290 291 /*define for HEADER word*/ 292 /*define for op field*/ 293 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0 294 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF 295 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0 296 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) 297 298 /*define for sub_op field*/ 299 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0 300 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF 301 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8 302 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) 303 304 /*define for tmz field*/ 305 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0 306 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001 307 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18 308 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) 309 310 /*define for COUNT word*/ 311 /*define for count field*/ 312 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1 313 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF 314 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0 315 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) 316 317 /*define for PARAMETER word*/ 318 /*define for dst_sw field*/ 319 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2 320 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003 321 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 16 322 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) 323 324 /*define for dst_gcc field*/ 325 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2 326 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001 327 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19 328 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) 329 330 /*define for dst_sys field*/ 331 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2 332 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001 333 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20 334 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) 335 336 /*define for dst_log field*/ 337 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2 338 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001 339 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21 340 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) 341 342 /*define for dst_snoop field*/ 343 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2 344 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001 345 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22 346 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) 347 348 /*define for dst_gpa field*/ 349 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2 350 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001 351 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23 352 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) 353 354 /*define for src_sw field*/ 355 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2 356 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003 357 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24 358 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) 359 360 /*define for src_gcc field*/ 361 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2 362 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001 363 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27 364 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) 365 366 /*define for src_sys field*/ 367 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2 368 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001 369 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28 370 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) 371 372 /*define for src_snoop field*/ 373 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2 374 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001 375 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30 376 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) 377 378 /*define for src_gpa field*/ 379 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2 380 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001 381 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31 382 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) 383 384 /*define for SRC_ADDR_LO word*/ 385 /*define for src_addr_31_0 field*/ 386 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 387 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 388 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 389 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 390 391 /*define for SRC_ADDR_HI word*/ 392 /*define for src_addr_63_32 field*/ 393 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 394 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 395 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 396 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 397 398 /*define for DST_ADDR_LO word*/ 399 /*define for dst_addr_31_0 field*/ 400 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 401 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 402 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 403 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 404 405 /*define for DST_ADDR_HI word*/ 406 /*define for dst_addr_63_32 field*/ 407 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 408 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 409 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 410 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 411 412 413 /* 414 ** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet 415 */ 416 417 /*define for HEADER word*/ 418 /*define for op field*/ 419 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 420 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF 421 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 422 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) 423 424 /*define for sub_op field*/ 425 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 426 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF 427 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 428 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) 429 430 /*define for encrypt field*/ 431 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0 432 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001 433 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16 434 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) 435 436 /*define for tmz field*/ 437 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0 438 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001 439 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18 440 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) 441 442 /*define for broadcast field*/ 443 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 444 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 445 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 446 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) 447 448 /*define for COUNT word*/ 449 /*define for count field*/ 450 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 451 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF 452 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 453 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) 454 455 /*define for PARAMETER word*/ 456 /*define for dst2_sw field*/ 457 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 458 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 459 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 460 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) 461 462 /*define for dst1_sw field*/ 463 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 464 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 465 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 466 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) 467 468 /*define for src_sw field*/ 469 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 470 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 471 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 472 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) 473 474 /*define for SRC_ADDR_LO word*/ 475 /*define for src_addr_31_0 field*/ 476 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 477 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 478 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 479 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 480 481 /*define for SRC_ADDR_HI word*/ 482 /*define for src_addr_63_32 field*/ 483 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 484 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 485 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 486 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 487 488 /*define for DST1_ADDR_LO word*/ 489 /*define for dst1_addr_31_0 field*/ 490 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 491 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF 492 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 493 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) 494 495 /*define for DST1_ADDR_HI word*/ 496 /*define for dst1_addr_63_32 field*/ 497 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 498 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF 499 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 500 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) 501 502 /*define for DST2_ADDR_LO word*/ 503 /*define for dst2_addr_31_0 field*/ 504 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 505 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF 506 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 507 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) 508 509 /*define for DST2_ADDR_HI word*/ 510 /*define for dst2_addr_63_32 field*/ 511 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 512 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF 513 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 514 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) 515 516 517 /* 518 ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet 519 */ 520 521 /*define for HEADER word*/ 522 /*define for op field*/ 523 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 524 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF 525 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 526 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) 527 528 /*define for sub_op field*/ 529 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 530 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF 531 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 532 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) 533 534 /*define for tmz field*/ 535 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0 536 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001 537 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18 538 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) 539 540 /*define for elementsize field*/ 541 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 542 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 543 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 544 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) 545 546 /*define for SRC_ADDR_LO word*/ 547 /*define for src_addr_31_0 field*/ 548 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 549 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 550 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 551 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) 552 553 /*define for SRC_ADDR_HI word*/ 554 /*define for src_addr_63_32 field*/ 555 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 556 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 557 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 558 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) 559 560 /*define for DW_3 word*/ 561 /*define for src_x field*/ 562 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 563 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF 564 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 565 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) 566 567 /*define for src_y field*/ 568 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 569 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF 570 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 571 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) 572 573 /*define for DW_4 word*/ 574 /*define for src_z field*/ 575 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 576 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x000007FF 577 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 578 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) 579 580 /*define for src_pitch field*/ 581 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 582 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF 583 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13 584 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) 585 586 /*define for DW_5 word*/ 587 /*define for src_slice_pitch field*/ 588 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 589 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF 590 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 591 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) 592 593 /*define for DST_ADDR_LO word*/ 594 /*define for dst_addr_31_0 field*/ 595 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 596 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 597 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 598 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) 599 600 /*define for DST_ADDR_HI word*/ 601 /*define for dst_addr_63_32 field*/ 602 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 603 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 604 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 605 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) 606 607 /*define for DW_8 word*/ 608 /*define for dst_x field*/ 609 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 610 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF 611 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 612 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) 613 614 /*define for dst_y field*/ 615 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 616 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF 617 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 618 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) 619 620 /*define for DW_9 word*/ 621 /*define for dst_z field*/ 622 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 623 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x000007FF 624 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 625 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) 626 627 /*define for dst_pitch field*/ 628 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 629 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF 630 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13 631 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) 632 633 /*define for DW_10 word*/ 634 /*define for dst_slice_pitch field*/ 635 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 636 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF 637 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 638 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) 639 640 /*define for DW_11 word*/ 641 /*define for rect_x field*/ 642 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 643 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF 644 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 645 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) 646 647 /*define for rect_y field*/ 648 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 649 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF 650 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 651 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) 652 653 /*define for DW_12 word*/ 654 /*define for rect_z field*/ 655 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 656 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x000007FF 657 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 658 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) 659 660 /*define for dst_sw field*/ 661 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 662 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 663 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 664 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) 665 666 /*define for src_sw field*/ 667 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 668 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 669 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 670 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) 671 672 673 /* 674 ** Definitions for SDMA_PKT_COPY_TILED packet 675 */ 676 677 /*define for HEADER word*/ 678 /*define for op field*/ 679 #define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 680 #define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF 681 #define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 682 #define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) 683 684 /*define for sub_op field*/ 685 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 686 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF 687 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 688 #define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) 689 690 /*define for encrypt field*/ 691 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0 692 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001 693 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16 694 #define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) 695 696 /*define for tmz field*/ 697 #define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0 698 #define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001 699 #define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18 700 #define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) 701 702 /*define for mip_max field*/ 703 #define SDMA_PKT_COPY_TILED_HEADER_mip_max_offset 0 704 #define SDMA_PKT_COPY_TILED_HEADER_mip_max_mask 0x0000000F 705 #define SDMA_PKT_COPY_TILED_HEADER_mip_max_shift 20 706 #define SDMA_PKT_COPY_TILED_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_HEADER_mip_max_shift) 707 708 /*define for detile field*/ 709 #define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 710 #define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 711 #define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 712 #define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) 713 714 /*define for TILED_ADDR_LO word*/ 715 /*define for tiled_addr_31_0 field*/ 716 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 717 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 718 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 719 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) 720 721 /*define for TILED_ADDR_HI word*/ 722 /*define for tiled_addr_63_32 field*/ 723 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 724 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 725 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 726 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) 727 728 /*define for DW_3 word*/ 729 /*define for width field*/ 730 #define SDMA_PKT_COPY_TILED_DW_3_width_offset 3 731 #define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF 732 #define SDMA_PKT_COPY_TILED_DW_3_width_shift 0 733 #define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) 734 735 /*define for DW_4 word*/ 736 /*define for height field*/ 737 #define SDMA_PKT_COPY_TILED_DW_4_height_offset 4 738 #define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF 739 #define SDMA_PKT_COPY_TILED_DW_4_height_shift 0 740 #define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) 741 742 /*define for depth field*/ 743 #define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4 744 #define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x000007FF 745 #define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16 746 #define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) 747 748 /*define for DW_5 word*/ 749 /*define for element_size field*/ 750 #define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 751 #define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 752 #define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 753 #define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) 754 755 /*define for swizzle_mode field*/ 756 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5 757 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F 758 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3 759 #define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) 760 761 /*define for dimension field*/ 762 #define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5 763 #define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003 764 #define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9 765 #define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) 766 767 /*define for epitch field*/ 768 #define SDMA_PKT_COPY_TILED_DW_5_epitch_offset 5 769 #define SDMA_PKT_COPY_TILED_DW_5_epitch_mask 0x0000FFFF 770 #define SDMA_PKT_COPY_TILED_DW_5_epitch_shift 16 771 #define SDMA_PKT_COPY_TILED_DW_5_EPITCH(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_epitch_mask) << SDMA_PKT_COPY_TILED_DW_5_epitch_shift) 772 773 /*define for DW_6 word*/ 774 /*define for x field*/ 775 #define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 776 #define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF 777 #define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 778 #define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) 779 780 /*define for y field*/ 781 #define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 782 #define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF 783 #define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 784 #define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) 785 786 /*define for DW_7 word*/ 787 /*define for z field*/ 788 #define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 789 #define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x000007FF 790 #define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 791 #define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) 792 793 /*define for linear_sw field*/ 794 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 795 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 796 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 797 #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) 798 799 /*define for tile_sw field*/ 800 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 801 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 802 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 803 #define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) 804 805 /*define for LINEAR_ADDR_LO word*/ 806 /*define for linear_addr_31_0 field*/ 807 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 808 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 809 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 810 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) 811 812 /*define for LINEAR_ADDR_HI word*/ 813 /*define for linear_addr_63_32 field*/ 814 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 815 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 816 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 817 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) 818 819 /*define for LINEAR_PITCH word*/ 820 /*define for linear_pitch field*/ 821 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 822 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 823 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 824 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) 825 826 /*define for LINEAR_SLICE_PITCH word*/ 827 /*define for linear_slice_pitch field*/ 828 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 829 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 830 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 831 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 832 833 /*define for COUNT word*/ 834 /*define for count field*/ 835 #define SDMA_PKT_COPY_TILED_COUNT_count_offset 12 836 #define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x000FFFFF 837 #define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 838 #define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) 839 840 841 /* 842 ** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet 843 */ 844 845 /*define for HEADER word*/ 846 /*define for op field*/ 847 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 848 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF 849 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 850 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) 851 852 /*define for sub_op field*/ 853 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 854 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF 855 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 856 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) 857 858 /*define for encrypt field*/ 859 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0 860 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001 861 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16 862 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) 863 864 /*define for tmz field*/ 865 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0 866 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001 867 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18 868 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) 869 870 /*define for mip_max field*/ 871 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset 0 872 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask 0x0000000F 873 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift 20 874 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift) 875 876 /*define for videocopy field*/ 877 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 878 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 879 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 880 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) 881 882 /*define for broadcast field*/ 883 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 884 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 885 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 886 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) 887 888 /*define for TILED_ADDR_LO_0 word*/ 889 /*define for tiled_addr0_31_0 field*/ 890 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 891 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF 892 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 893 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) 894 895 /*define for TILED_ADDR_HI_0 word*/ 896 /*define for tiled_addr0_63_32 field*/ 897 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 898 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF 899 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 900 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) 901 902 /*define for TILED_ADDR_LO_1 word*/ 903 /*define for tiled_addr1_31_0 field*/ 904 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 905 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF 906 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 907 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) 908 909 /*define for TILED_ADDR_HI_1 word*/ 910 /*define for tiled_addr1_63_32 field*/ 911 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 912 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF 913 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 914 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) 915 916 /*define for DW_5 word*/ 917 /*define for width field*/ 918 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5 919 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF 920 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0 921 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) 922 923 /*define for DW_6 word*/ 924 /*define for height field*/ 925 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6 926 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF 927 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0 928 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) 929 930 /*define for depth field*/ 931 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6 932 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x000007FF 933 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16 934 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) 935 936 /*define for DW_7 word*/ 937 /*define for element_size field*/ 938 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 939 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 940 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 941 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) 942 943 /*define for swizzle_mode field*/ 944 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7 945 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F 946 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3 947 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) 948 949 /*define for dimension field*/ 950 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7 951 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003 952 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9 953 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) 954 955 /*define for epitch field*/ 956 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset 7 957 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask 0x0000FFFF 958 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift 16 959 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_EPITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift) 960 961 /*define for DW_8 word*/ 962 /*define for x field*/ 963 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 964 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF 965 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 966 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) 967 968 /*define for y field*/ 969 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 970 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF 971 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 972 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) 973 974 /*define for DW_9 word*/ 975 /*define for z field*/ 976 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 977 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x000007FF 978 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 979 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) 980 981 /*define for DW_10 word*/ 982 /*define for dst2_sw field*/ 983 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 984 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 985 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 986 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) 987 988 /*define for linear_sw field*/ 989 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 990 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 991 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 992 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) 993 994 /*define for tile_sw field*/ 995 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 996 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 997 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 998 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) 999 1000 /*define for LINEAR_ADDR_LO word*/ 1001 /*define for linear_addr_31_0 field*/ 1002 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 1003 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1004 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1005 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1006 1007 /*define for LINEAR_ADDR_HI word*/ 1008 /*define for linear_addr_63_32 field*/ 1009 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 1010 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1011 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1012 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1013 1014 /*define for LINEAR_PITCH word*/ 1015 /*define for linear_pitch field*/ 1016 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 1017 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 1018 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 1019 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) 1020 1021 /*define for LINEAR_SLICE_PITCH word*/ 1022 /*define for linear_slice_pitch field*/ 1023 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14 1024 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 1025 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 1026 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 1027 1028 /*define for COUNT word*/ 1029 /*define for count field*/ 1030 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15 1031 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x000FFFFF 1032 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 1033 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) 1034 1035 1036 /* 1037 ** Definitions for SDMA_PKT_COPY_T2T packet 1038 */ 1039 1040 /*define for HEADER word*/ 1041 /*define for op field*/ 1042 #define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 1043 #define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF 1044 #define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 1045 #define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) 1046 1047 /*define for sub_op field*/ 1048 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 1049 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF 1050 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 1051 #define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) 1052 1053 /*define for tmz field*/ 1054 #define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0 1055 #define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001 1056 #define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 18 1057 #define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) 1058 1059 /*define for mip_max field*/ 1060 #define SDMA_PKT_COPY_T2T_HEADER_mip_max_offset 0 1061 #define SDMA_PKT_COPY_T2T_HEADER_mip_max_mask 0x0000000F 1062 #define SDMA_PKT_COPY_T2T_HEADER_mip_max_shift 20 1063 #define SDMA_PKT_COPY_T2T_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_mip_max_mask) << SDMA_PKT_COPY_T2T_HEADER_mip_max_shift) 1064 1065 /*define for SRC_ADDR_LO word*/ 1066 /*define for src_addr_31_0 field*/ 1067 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 1068 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 1069 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 1070 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) 1071 1072 /*define for SRC_ADDR_HI word*/ 1073 /*define for src_addr_63_32 field*/ 1074 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 1075 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 1076 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 1077 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) 1078 1079 /*define for DW_3 word*/ 1080 /*define for src_x field*/ 1081 #define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 1082 #define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF 1083 #define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 1084 #define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) 1085 1086 /*define for src_y field*/ 1087 #define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 1088 #define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF 1089 #define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 1090 #define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) 1091 1092 /*define for DW_4 word*/ 1093 /*define for src_z field*/ 1094 #define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 1095 #define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x000007FF 1096 #define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 1097 #define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) 1098 1099 /*define for src_width field*/ 1100 #define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4 1101 #define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF 1102 #define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 16 1103 #define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) 1104 1105 /*define for DW_5 word*/ 1106 /*define for src_height field*/ 1107 #define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5 1108 #define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF 1109 #define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0 1110 #define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) 1111 1112 /*define for src_depth field*/ 1113 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5 1114 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x000007FF 1115 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 16 1116 #define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) 1117 1118 /*define for DW_6 word*/ 1119 /*define for src_element_size field*/ 1120 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 1121 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 1122 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 1123 #define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) 1124 1125 /*define for src_swizzle_mode field*/ 1126 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6 1127 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F 1128 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 3 1129 #define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) 1130 1131 /*define for src_dimension field*/ 1132 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6 1133 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003 1134 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 9 1135 #define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) 1136 1137 /*define for src_epitch field*/ 1138 #define SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset 6 1139 #define SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask 0x0000FFFF 1140 #define SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift 16 1141 #define SDMA_PKT_COPY_T2T_DW_6_SRC_EPITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask) << SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift) 1142 1143 /*define for DST_ADDR_LO word*/ 1144 /*define for dst_addr_31_0 field*/ 1145 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 1146 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1147 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 1148 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) 1149 1150 /*define for DST_ADDR_HI word*/ 1151 /*define for dst_addr_63_32 field*/ 1152 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 1153 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1154 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 1155 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) 1156 1157 /*define for DW_9 word*/ 1158 /*define for dst_x field*/ 1159 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 1160 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF 1161 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 1162 #define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) 1163 1164 /*define for dst_y field*/ 1165 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 1166 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF 1167 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 1168 #define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) 1169 1170 /*define for DW_10 word*/ 1171 /*define for dst_z field*/ 1172 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 1173 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x000007FF 1174 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 1175 #define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) 1176 1177 /*define for dst_width field*/ 1178 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10 1179 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF 1180 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 16 1181 #define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) 1182 1183 /*define for DW_11 word*/ 1184 /*define for dst_height field*/ 1185 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11 1186 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF 1187 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0 1188 #define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) 1189 1190 /*define for dst_depth field*/ 1191 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11 1192 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x000007FF 1193 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 16 1194 #define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) 1195 1196 /*define for DW_12 word*/ 1197 /*define for dst_element_size field*/ 1198 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12 1199 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007 1200 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0 1201 #define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) 1202 1203 /*define for dst_swizzle_mode field*/ 1204 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12 1205 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F 1206 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 3 1207 #define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) 1208 1209 /*define for dst_dimension field*/ 1210 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12 1211 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003 1212 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 9 1213 #define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) 1214 1215 /*define for dst_epitch field*/ 1216 #define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset 12 1217 #define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask 0x0000FFFF 1218 #define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift 16 1219 #define SDMA_PKT_COPY_T2T_DW_12_DST_EPITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift) 1220 1221 /*define for DW_13 word*/ 1222 /*define for rect_x field*/ 1223 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 1224 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF 1225 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 1226 #define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) 1227 1228 /*define for rect_y field*/ 1229 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 1230 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF 1231 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 1232 #define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) 1233 1234 /*define for DW_14 word*/ 1235 /*define for rect_z field*/ 1236 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 1237 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x000007FF 1238 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 1239 #define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) 1240 1241 /*define for dst_sw field*/ 1242 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 1243 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 1244 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 1245 #define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) 1246 1247 /*define for src_sw field*/ 1248 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 1249 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 1250 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 1251 #define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) 1252 1253 1254 /* 1255 ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet 1256 */ 1257 1258 /*define for HEADER word*/ 1259 /*define for op field*/ 1260 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 1261 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF 1262 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 1263 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) 1264 1265 /*define for sub_op field*/ 1266 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 1267 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF 1268 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 1269 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) 1270 1271 /*define for tmz field*/ 1272 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0 1273 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001 1274 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 18 1275 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) 1276 1277 /*define for mip_max field*/ 1278 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset 0 1279 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask 0x0000000F 1280 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift 20 1281 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift) 1282 1283 /*define for mip_id field*/ 1284 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset 0 1285 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask 0x0000000F 1286 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift 24 1287 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift) 1288 1289 /*define for detile field*/ 1290 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 1291 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 1292 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 1293 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) 1294 1295 /*define for TILED_ADDR_LO word*/ 1296 /*define for tiled_addr_31_0 field*/ 1297 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 1298 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 1299 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 1300 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) 1301 1302 /*define for TILED_ADDR_HI word*/ 1303 /*define for tiled_addr_63_32 field*/ 1304 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 1305 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 1306 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 1307 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) 1308 1309 /*define for DW_3 word*/ 1310 /*define for tiled_x field*/ 1311 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 1312 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF 1313 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 1314 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) 1315 1316 /*define for tiled_y field*/ 1317 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 1318 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF 1319 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 1320 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) 1321 1322 /*define for DW_4 word*/ 1323 /*define for tiled_z field*/ 1324 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 1325 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x000007FF 1326 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 1327 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) 1328 1329 /*define for width field*/ 1330 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4 1331 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF 1332 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 16 1333 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) 1334 1335 /*define for DW_5 word*/ 1336 /*define for height field*/ 1337 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5 1338 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF 1339 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0 1340 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) 1341 1342 /*define for depth field*/ 1343 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5 1344 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x000007FF 1345 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 16 1346 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) 1347 1348 /*define for DW_6 word*/ 1349 /*define for element_size field*/ 1350 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 1351 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 1352 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 1353 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) 1354 1355 /*define for swizzle_mode field*/ 1356 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6 1357 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F 1358 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 3 1359 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) 1360 1361 /*define for dimension field*/ 1362 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6 1363 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003 1364 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 9 1365 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) 1366 1367 /*define for epitch field*/ 1368 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset 6 1369 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask 0x0000FFFF 1370 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift 16 1371 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_EPITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift) 1372 1373 /*define for LINEAR_ADDR_LO word*/ 1374 /*define for linear_addr_31_0 field*/ 1375 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 1376 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1377 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1378 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1379 1380 /*define for LINEAR_ADDR_HI word*/ 1381 /*define for linear_addr_63_32 field*/ 1382 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 1383 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1384 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1385 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1386 1387 /*define for DW_9 word*/ 1388 /*define for linear_x field*/ 1389 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 1390 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF 1391 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 1392 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) 1393 1394 /*define for linear_y field*/ 1395 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 1396 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF 1397 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 1398 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) 1399 1400 /*define for DW_10 word*/ 1401 /*define for linear_z field*/ 1402 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 1403 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x000007FF 1404 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 1405 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) 1406 1407 /*define for linear_pitch field*/ 1408 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 1409 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF 1410 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 1411 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) 1412 1413 /*define for DW_11 word*/ 1414 /*define for linear_slice_pitch field*/ 1415 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 1416 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF 1417 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 1418 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) 1419 1420 /*define for DW_12 word*/ 1421 /*define for rect_x field*/ 1422 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 1423 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF 1424 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 1425 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) 1426 1427 /*define for rect_y field*/ 1428 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 1429 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF 1430 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 1431 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) 1432 1433 /*define for DW_13 word*/ 1434 /*define for rect_z field*/ 1435 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 1436 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x000007FF 1437 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 1438 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) 1439 1440 /*define for linear_sw field*/ 1441 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 1442 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 1443 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 1444 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) 1445 1446 /*define for tile_sw field*/ 1447 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 1448 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 1449 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 1450 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) 1451 1452 1453 /* 1454 ** Definitions for SDMA_PKT_COPY_STRUCT packet 1455 */ 1456 1457 /*define for HEADER word*/ 1458 /*define for op field*/ 1459 #define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 1460 #define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF 1461 #define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 1462 #define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) 1463 1464 /*define for sub_op field*/ 1465 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 1466 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF 1467 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 1468 #define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) 1469 1470 /*define for tmz field*/ 1471 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0 1472 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001 1473 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 18 1474 #define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) 1475 1476 /*define for detile field*/ 1477 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 1478 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 1479 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 1480 #define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) 1481 1482 /*define for SB_ADDR_LO word*/ 1483 /*define for sb_addr_31_0 field*/ 1484 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 1485 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF 1486 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 1487 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) 1488 1489 /*define for SB_ADDR_HI word*/ 1490 /*define for sb_addr_63_32 field*/ 1491 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 1492 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF 1493 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 1494 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) 1495 1496 /*define for START_INDEX word*/ 1497 /*define for start_index field*/ 1498 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 1499 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF 1500 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 1501 #define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) 1502 1503 /*define for COUNT word*/ 1504 /*define for count field*/ 1505 #define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 1506 #define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF 1507 #define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 1508 #define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) 1509 1510 /*define for DW_5 word*/ 1511 /*define for stride field*/ 1512 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 1513 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF 1514 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 1515 #define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) 1516 1517 /*define for linear_sw field*/ 1518 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 1519 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 1520 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 16 1521 #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) 1522 1523 /*define for struct_sw field*/ 1524 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 1525 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 1526 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 24 1527 #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) 1528 1529 /*define for LINEAR_ADDR_LO word*/ 1530 /*define for linear_addr_31_0 field*/ 1531 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 1532 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1533 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1534 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1535 1536 /*define for LINEAR_ADDR_HI word*/ 1537 /*define for linear_addr_63_32 field*/ 1538 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 1539 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1540 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1541 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1542 1543 1544 /* 1545 ** Definitions for SDMA_PKT_WRITE_UNTILED packet 1546 */ 1547 1548 /*define for HEADER word*/ 1549 /*define for op field*/ 1550 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 1551 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF 1552 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 1553 #define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) 1554 1555 /*define for sub_op field*/ 1556 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 1557 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF 1558 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 1559 #define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) 1560 1561 /*define for encrypt field*/ 1562 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0 1563 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001 1564 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 16 1565 #define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) 1566 1567 /*define for tmz field*/ 1568 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0 1569 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001 1570 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 18 1571 #define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) 1572 1573 /*define for DST_ADDR_LO word*/ 1574 /*define for dst_addr_31_0 field*/ 1575 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 1576 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1577 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 1578 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) 1579 1580 /*define for DST_ADDR_HI word*/ 1581 /*define for dst_addr_63_32 field*/ 1582 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 1583 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1584 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 1585 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) 1586 1587 /*define for DW_3 word*/ 1588 /*define for count field*/ 1589 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 1590 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF 1591 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 1592 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) 1593 1594 /*define for sw field*/ 1595 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 1596 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 1597 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 1598 #define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) 1599 1600 /*define for DATA0 word*/ 1601 /*define for data0 field*/ 1602 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 1603 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF 1604 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 1605 #define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) 1606 1607 1608 /* 1609 ** Definitions for SDMA_PKT_WRITE_TILED packet 1610 */ 1611 1612 /*define for HEADER word*/ 1613 /*define for op field*/ 1614 #define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 1615 #define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF 1616 #define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 1617 #define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) 1618 1619 /*define for sub_op field*/ 1620 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 1621 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF 1622 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 1623 #define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) 1624 1625 /*define for encrypt field*/ 1626 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0 1627 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001 1628 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 16 1629 #define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) 1630 1631 /*define for tmz field*/ 1632 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0 1633 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001 1634 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 18 1635 #define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) 1636 1637 /*define for mip_max field*/ 1638 #define SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset 0 1639 #define SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask 0x0000000F 1640 #define SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift 20 1641 #define SDMA_PKT_WRITE_TILED_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask) << SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift) 1642 1643 /*define for DST_ADDR_LO word*/ 1644 /*define for dst_addr_31_0 field*/ 1645 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 1646 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1647 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 1648 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) 1649 1650 /*define for DST_ADDR_HI word*/ 1651 /*define for dst_addr_63_32 field*/ 1652 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 1653 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1654 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 1655 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) 1656 1657 /*define for DW_3 word*/ 1658 /*define for width field*/ 1659 #define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3 1660 #define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF 1661 #define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0 1662 #define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) 1663 1664 /*define for DW_4 word*/ 1665 /*define for height field*/ 1666 #define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4 1667 #define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF 1668 #define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0 1669 #define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) 1670 1671 /*define for depth field*/ 1672 #define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4 1673 #define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x000007FF 1674 #define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 16 1675 #define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) 1676 1677 /*define for DW_5 word*/ 1678 /*define for element_size field*/ 1679 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 1680 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 1681 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 1682 #define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) 1683 1684 /*define for swizzle_mode field*/ 1685 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5 1686 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F 1687 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 3 1688 #define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) 1689 1690 /*define for dimension field*/ 1691 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5 1692 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003 1693 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 9 1694 #define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) 1695 1696 /*define for epitch field*/ 1697 #define SDMA_PKT_WRITE_TILED_DW_5_epitch_offset 5 1698 #define SDMA_PKT_WRITE_TILED_DW_5_epitch_mask 0x0000FFFF 1699 #define SDMA_PKT_WRITE_TILED_DW_5_epitch_shift 16 1700 #define SDMA_PKT_WRITE_TILED_DW_5_EPITCH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_epitch_mask) << SDMA_PKT_WRITE_TILED_DW_5_epitch_shift) 1701 1702 /*define for DW_6 word*/ 1703 /*define for x field*/ 1704 #define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 1705 #define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF 1706 #define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 1707 #define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) 1708 1709 /*define for y field*/ 1710 #define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 1711 #define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF 1712 #define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 1713 #define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) 1714 1715 /*define for DW_7 word*/ 1716 /*define for z field*/ 1717 #define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 1718 #define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x000007FF 1719 #define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 1720 #define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) 1721 1722 /*define for sw field*/ 1723 #define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 1724 #define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 1725 #define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 1726 #define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) 1727 1728 /*define for COUNT word*/ 1729 /*define for count field*/ 1730 #define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 1731 #define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF 1732 #define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 1733 #define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) 1734 1735 /*define for DATA0 word*/ 1736 /*define for data0 field*/ 1737 #define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 1738 #define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF 1739 #define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 1740 #define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) 1741 1742 1743 /* 1744 ** Definitions for SDMA_PKT_PTEPDE_COPY packet 1745 */ 1746 1747 /*define for HEADER word*/ 1748 /*define for op field*/ 1749 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0 1750 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF 1751 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0 1752 #define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) 1753 1754 /*define for sub_op field*/ 1755 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0 1756 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF 1757 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 8 1758 #define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) 1759 1760 /*define for ptepde_op field*/ 1761 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0 1762 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x00000001 1763 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 31 1764 #define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) 1765 1766 /*define for SRC_ADDR_LO word*/ 1767 /*define for src_addr_31_0 field*/ 1768 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1 1769 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 1770 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0 1771 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) 1772 1773 /*define for SRC_ADDR_HI word*/ 1774 /*define for src_addr_63_32 field*/ 1775 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2 1776 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 1777 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0 1778 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) 1779 1780 /*define for DST_ADDR_LO word*/ 1781 /*define for dst_addr_31_0 field*/ 1782 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3 1783 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1784 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0 1785 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) 1786 1787 /*define for DST_ADDR_HI word*/ 1788 /*define for dst_addr_63_32 field*/ 1789 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4 1790 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1791 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0 1792 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) 1793 1794 /*define for MASK_DW0 word*/ 1795 /*define for mask_dw0 field*/ 1796 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5 1797 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 1798 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0 1799 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) 1800 1801 /*define for MASK_DW1 word*/ 1802 /*define for mask_dw1 field*/ 1803 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6 1804 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 1805 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0 1806 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) 1807 1808 /*define for COUNT word*/ 1809 /*define for count field*/ 1810 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7 1811 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF 1812 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0 1813 #define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) 1814 1815 1816 /* 1817 ** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet 1818 */ 1819 1820 /*define for HEADER word*/ 1821 /*define for op field*/ 1822 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0 1823 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF 1824 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0 1825 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) 1826 1827 /*define for sub_op field*/ 1828 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0 1829 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF 1830 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 8 1831 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) 1832 1833 /*define for pte_size field*/ 1834 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0 1835 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003 1836 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 28 1837 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) 1838 1839 /*define for direction field*/ 1840 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0 1841 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001 1842 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 30 1843 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) 1844 1845 /*define for ptepde_op field*/ 1846 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0 1847 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001 1848 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 31 1849 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) 1850 1851 /*define for SRC_ADDR_LO word*/ 1852 /*define for src_addr_31_0 field*/ 1853 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1 1854 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 1855 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0 1856 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) 1857 1858 /*define for SRC_ADDR_HI word*/ 1859 /*define for src_addr_63_32 field*/ 1860 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2 1861 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 1862 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0 1863 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) 1864 1865 /*define for DST_ADDR_LO word*/ 1866 /*define for dst_addr_31_0 field*/ 1867 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3 1868 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1869 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0 1870 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) 1871 1872 /*define for DST_ADDR_HI word*/ 1873 /*define for dst_addr_63_32 field*/ 1874 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4 1875 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1876 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0 1877 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) 1878 1879 /*define for MASK_BIT_FOR_DW word*/ 1880 /*define for mask_first_xfer field*/ 1881 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5 1882 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF 1883 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0 1884 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) 1885 1886 /*define for mask_last_xfer field*/ 1887 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5 1888 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF 1889 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 8 1890 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) 1891 1892 /*define for COUNT_IN_32B_XFER word*/ 1893 /*define for count field*/ 1894 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6 1895 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF 1896 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0 1897 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) 1898 1899 1900 /* 1901 ** Definitions for SDMA_PKT_PTEPDE_RMW packet 1902 */ 1903 1904 /*define for HEADER word*/ 1905 /*define for op field*/ 1906 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0 1907 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF 1908 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0 1909 #define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) 1910 1911 /*define for sub_op field*/ 1912 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0 1913 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF 1914 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 8 1915 #define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) 1916 1917 /*define for gcc field*/ 1918 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0 1919 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001 1920 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 19 1921 #define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) 1922 1923 /*define for sys field*/ 1924 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0 1925 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001 1926 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 20 1927 #define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) 1928 1929 /*define for snp field*/ 1930 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0 1931 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001 1932 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 22 1933 #define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) 1934 1935 /*define for gpa field*/ 1936 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0 1937 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001 1938 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 23 1939 #define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) 1940 1941 /*define for ADDR_LO word*/ 1942 /*define for addr_31_0 field*/ 1943 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1 1944 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 1945 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0 1946 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) 1947 1948 /*define for ADDR_HI word*/ 1949 /*define for addr_63_32 field*/ 1950 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2 1951 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 1952 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0 1953 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) 1954 1955 /*define for MASK_LO word*/ 1956 /*define for mask_31_0 field*/ 1957 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3 1958 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF 1959 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0 1960 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) 1961 1962 /*define for MASK_HI word*/ 1963 /*define for mask_63_32 field*/ 1964 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4 1965 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF 1966 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0 1967 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) 1968 1969 /*define for VALUE_LO word*/ 1970 /*define for value_31_0 field*/ 1971 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5 1972 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF 1973 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0 1974 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) 1975 1976 /*define for VALUE_HI word*/ 1977 /*define for value_63_32 field*/ 1978 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6 1979 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF 1980 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0 1981 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) 1982 1983 1984 /* 1985 ** Definitions for SDMA_PKT_WRITE_INCR packet 1986 */ 1987 1988 /*define for HEADER word*/ 1989 /*define for op field*/ 1990 #define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 1991 #define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF 1992 #define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 1993 #define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) 1994 1995 /*define for sub_op field*/ 1996 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 1997 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF 1998 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 1999 #define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) 2000 2001 /*define for DST_ADDR_LO word*/ 2002 /*define for dst_addr_31_0 field*/ 2003 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 2004 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 2005 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 2006 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) 2007 2008 /*define for DST_ADDR_HI word*/ 2009 /*define for dst_addr_63_32 field*/ 2010 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 2011 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 2012 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 2013 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) 2014 2015 /*define for MASK_DW0 word*/ 2016 /*define for mask_dw0 field*/ 2017 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 2018 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 2019 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 2020 #define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) 2021 2022 /*define for MASK_DW1 word*/ 2023 /*define for mask_dw1 field*/ 2024 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 2025 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 2026 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 2027 #define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) 2028 2029 /*define for INIT_DW0 word*/ 2030 /*define for init_dw0 field*/ 2031 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 2032 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF 2033 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 2034 #define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) 2035 2036 /*define for INIT_DW1 word*/ 2037 /*define for init_dw1 field*/ 2038 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 2039 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF 2040 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 2041 #define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) 2042 2043 /*define for INCR_DW0 word*/ 2044 /*define for incr_dw0 field*/ 2045 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 2046 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF 2047 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 2048 #define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) 2049 2050 /*define for INCR_DW1 word*/ 2051 /*define for incr_dw1 field*/ 2052 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 2053 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF 2054 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 2055 #define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) 2056 2057 /*define for COUNT word*/ 2058 /*define for count field*/ 2059 #define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 2060 #define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF 2061 #define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 2062 #define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) 2063 2064 2065 /* 2066 ** Definitions for SDMA_PKT_INDIRECT packet 2067 */ 2068 2069 /*define for HEADER word*/ 2070 /*define for op field*/ 2071 #define SDMA_PKT_INDIRECT_HEADER_op_offset 0 2072 #define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF 2073 #define SDMA_PKT_INDIRECT_HEADER_op_shift 0 2074 #define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) 2075 2076 /*define for sub_op field*/ 2077 #define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 2078 #define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF 2079 #define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 2080 #define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) 2081 2082 /*define for vmid field*/ 2083 #define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 2084 #define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F 2085 #define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 2086 #define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) 2087 2088 /*define for BASE_LO word*/ 2089 /*define for ib_base_31_0 field*/ 2090 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 2091 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF 2092 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 2093 #define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) 2094 2095 /*define for BASE_HI word*/ 2096 /*define for ib_base_63_32 field*/ 2097 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 2098 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF 2099 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 2100 #define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) 2101 2102 /*define for IB_SIZE word*/ 2103 /*define for ib_size field*/ 2104 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 2105 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF 2106 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 2107 #define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) 2108 2109 /*define for CSA_ADDR_LO word*/ 2110 /*define for csa_addr_31_0 field*/ 2111 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 2112 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF 2113 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 2114 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) 2115 2116 /*define for CSA_ADDR_HI word*/ 2117 /*define for csa_addr_63_32 field*/ 2118 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 2119 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF 2120 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 2121 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) 2122 2123 2124 /* 2125 ** Definitions for SDMA_PKT_SEMAPHORE packet 2126 */ 2127 2128 /*define for HEADER word*/ 2129 /*define for op field*/ 2130 #define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 2131 #define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF 2132 #define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 2133 #define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) 2134 2135 /*define for sub_op field*/ 2136 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 2137 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF 2138 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 2139 #define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) 2140 2141 /*define for write_one field*/ 2142 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 2143 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 2144 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 2145 #define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) 2146 2147 /*define for signal field*/ 2148 #define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 2149 #define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 2150 #define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 2151 #define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) 2152 2153 /*define for mailbox field*/ 2154 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 2155 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 2156 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 2157 #define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) 2158 2159 /*define for ADDR_LO word*/ 2160 /*define for addr_31_0 field*/ 2161 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 2162 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 2163 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 2164 #define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) 2165 2166 /*define for ADDR_HI word*/ 2167 /*define for addr_63_32 field*/ 2168 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 2169 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 2170 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 2171 #define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) 2172 2173 2174 /* 2175 ** Definitions for SDMA_PKT_FENCE packet 2176 */ 2177 2178 /*define for HEADER word*/ 2179 /*define for op field*/ 2180 #define SDMA_PKT_FENCE_HEADER_op_offset 0 2181 #define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF 2182 #define SDMA_PKT_FENCE_HEADER_op_shift 0 2183 #define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) 2184 2185 /*define for sub_op field*/ 2186 #define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 2187 #define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF 2188 #define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 2189 #define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) 2190 2191 /*define for ADDR_LO word*/ 2192 /*define for addr_31_0 field*/ 2193 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 2194 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 2195 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 2196 #define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) 2197 2198 /*define for ADDR_HI word*/ 2199 /*define for addr_63_32 field*/ 2200 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 2201 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 2202 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 2203 #define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) 2204 2205 /*define for DATA word*/ 2206 /*define for data field*/ 2207 #define SDMA_PKT_FENCE_DATA_data_offset 3 2208 #define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF 2209 #define SDMA_PKT_FENCE_DATA_data_shift 0 2210 #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) 2211 2212 2213 /* 2214 ** Definitions for SDMA_PKT_SRBM_WRITE packet 2215 */ 2216 2217 /*define for HEADER word*/ 2218 /*define for op field*/ 2219 #define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 2220 #define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF 2221 #define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 2222 #define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) 2223 2224 /*define for sub_op field*/ 2225 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 2226 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF 2227 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 2228 #define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) 2229 2230 /*define for byte_en field*/ 2231 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 2232 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F 2233 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 2234 #define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) 2235 2236 /*define for ADDR word*/ 2237 /*define for addr field*/ 2238 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 2239 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF 2240 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 2241 #define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) 2242 2243 /*define for DATA word*/ 2244 /*define for data field*/ 2245 #define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 2246 #define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF 2247 #define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 2248 #define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) 2249 2250 2251 /* 2252 ** Definitions for SDMA_PKT_PRE_EXE packet 2253 */ 2254 2255 /*define for HEADER word*/ 2256 /*define for op field*/ 2257 #define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 2258 #define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF 2259 #define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 2260 #define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) 2261 2262 /*define for sub_op field*/ 2263 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 2264 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF 2265 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 2266 #define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) 2267 2268 /*define for dev_sel field*/ 2269 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 2270 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF 2271 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 2272 #define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) 2273 2274 /*define for EXEC_COUNT word*/ 2275 /*define for exec_count field*/ 2276 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 2277 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 2278 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 2279 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) 2280 2281 2282 /* 2283 ** Definitions for SDMA_PKT_COND_EXE packet 2284 */ 2285 2286 /*define for HEADER word*/ 2287 /*define for op field*/ 2288 #define SDMA_PKT_COND_EXE_HEADER_op_offset 0 2289 #define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF 2290 #define SDMA_PKT_COND_EXE_HEADER_op_shift 0 2291 #define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) 2292 2293 /*define for sub_op field*/ 2294 #define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 2295 #define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF 2296 #define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 2297 #define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) 2298 2299 /*define for ADDR_LO word*/ 2300 /*define for addr_31_0 field*/ 2301 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 2302 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 2303 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 2304 #define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) 2305 2306 /*define for ADDR_HI word*/ 2307 /*define for addr_63_32 field*/ 2308 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 2309 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 2310 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 2311 #define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) 2312 2313 /*define for REFERENCE word*/ 2314 /*define for reference field*/ 2315 #define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 2316 #define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF 2317 #define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 2318 #define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) 2319 2320 /*define for EXEC_COUNT word*/ 2321 /*define for exec_count field*/ 2322 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 2323 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 2324 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 2325 #define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) 2326 2327 2328 /* 2329 ** Definitions for SDMA_PKT_CONSTANT_FILL packet 2330 */ 2331 2332 /*define for HEADER word*/ 2333 /*define for op field*/ 2334 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 2335 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF 2336 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 2337 #define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) 2338 2339 /*define for sub_op field*/ 2340 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 2341 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF 2342 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 2343 #define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) 2344 2345 /*define for sw field*/ 2346 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 2347 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 2348 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 2349 #define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) 2350 2351 /*define for fillsize field*/ 2352 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 2353 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 2354 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 2355 #define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) 2356 2357 /*define for DST_ADDR_LO word*/ 2358 /*define for dst_addr_31_0 field*/ 2359 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 2360 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 2361 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 2362 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) 2363 2364 /*define for DST_ADDR_HI word*/ 2365 /*define for dst_addr_63_32 field*/ 2366 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 2367 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 2368 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 2369 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) 2370 2371 /*define for DATA word*/ 2372 /*define for src_data_31_0 field*/ 2373 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 2374 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF 2375 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 2376 #define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) 2377 2378 /*define for COUNT word*/ 2379 /*define for count field*/ 2380 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 2381 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF 2382 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 2383 #define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) 2384 2385 2386 /* 2387 ** Definitions for SDMA_PKT_DATA_FILL_MULTI packet 2388 */ 2389 2390 /*define for HEADER word*/ 2391 /*define for op field*/ 2392 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0 2393 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF 2394 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0 2395 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) 2396 2397 /*define for sub_op field*/ 2398 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0 2399 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF 2400 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 8 2401 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) 2402 2403 /*define for memlog_clr field*/ 2404 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0 2405 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001 2406 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 31 2407 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) 2408 2409 /*define for BYTE_STRIDE word*/ 2410 /*define for byte_stride field*/ 2411 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1 2412 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF 2413 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0 2414 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) 2415 2416 /*define for DMA_COUNT word*/ 2417 /*define for dma_count field*/ 2418 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2 2419 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF 2420 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0 2421 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) 2422 2423 /*define for DST_ADDR_LO word*/ 2424 /*define for dst_addr_31_0 field*/ 2425 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3 2426 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 2427 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0 2428 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) 2429 2430 /*define for DST_ADDR_HI word*/ 2431 /*define for dst_addr_63_32 field*/ 2432 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4 2433 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 2434 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0 2435 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) 2436 2437 /*define for BYTE_COUNT word*/ 2438 /*define for count field*/ 2439 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5 2440 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF 2441 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0 2442 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) 2443 2444 2445 /* 2446 ** Definitions for SDMA_PKT_POLL_REGMEM packet 2447 */ 2448 2449 /*define for HEADER word*/ 2450 /*define for op field*/ 2451 #define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 2452 #define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF 2453 #define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 2454 #define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) 2455 2456 /*define for sub_op field*/ 2457 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 2458 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF 2459 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 2460 #define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) 2461 2462 /*define for hdp_flush field*/ 2463 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 2464 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 2465 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 2466 #define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) 2467 2468 /*define for func field*/ 2469 #define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 2470 #define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 2471 #define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 2472 #define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) 2473 2474 /*define for mem_poll field*/ 2475 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 2476 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 2477 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 2478 #define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) 2479 2480 /*define for ADDR_LO word*/ 2481 /*define for addr_31_0 field*/ 2482 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 2483 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 2484 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 2485 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) 2486 2487 /*define for ADDR_HI word*/ 2488 /*define for addr_63_32 field*/ 2489 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 2490 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 2491 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 2492 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) 2493 2494 /*define for VALUE word*/ 2495 /*define for value field*/ 2496 #define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 2497 #define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF 2498 #define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 2499 #define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) 2500 2501 /*define for MASK word*/ 2502 /*define for mask field*/ 2503 #define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 2504 #define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF 2505 #define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 2506 #define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) 2507 2508 /*define for DW5 word*/ 2509 /*define for interval field*/ 2510 #define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 2511 #define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF 2512 #define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 2513 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) 2514 2515 /*define for retry_count field*/ 2516 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 2517 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF 2518 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 2519 #define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) 2520 2521 2522 /* 2523 ** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet 2524 */ 2525 2526 /*define for HEADER word*/ 2527 /*define for op field*/ 2528 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0 2529 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF 2530 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0 2531 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) 2532 2533 /*define for sub_op field*/ 2534 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0 2535 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF 2536 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 8 2537 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) 2538 2539 /*define for SRC_ADDR word*/ 2540 /*define for addr_31_2 field*/ 2541 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1 2542 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF 2543 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 2 2544 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) 2545 2546 /*define for DST_ADDR_LO word*/ 2547 /*define for addr_31_0 field*/ 2548 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2 2549 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 2550 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 2551 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) 2552 2553 /*define for DST_ADDR_HI word*/ 2554 /*define for addr_63_32 field*/ 2555 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3 2556 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 2557 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 2558 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) 2559 2560 2561 /* 2562 ** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet 2563 */ 2564 2565 /*define for HEADER word*/ 2566 /*define for op field*/ 2567 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0 2568 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF 2569 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0 2570 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) 2571 2572 /*define for sub_op field*/ 2573 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0 2574 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF 2575 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 8 2576 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) 2577 2578 /*define for ea field*/ 2579 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0 2580 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003 2581 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 16 2582 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) 2583 2584 /*define for DST_ADDR_LO word*/ 2585 /*define for addr_31_0 field*/ 2586 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1 2587 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 2588 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 2589 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) 2590 2591 /*define for DST_ADDR_HI word*/ 2592 /*define for addr_63_32 field*/ 2593 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2 2594 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 2595 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 2596 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) 2597 2598 /*define for START_PAGE word*/ 2599 /*define for addr_31_4 field*/ 2600 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3 2601 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF 2602 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 4 2603 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) 2604 2605 /*define for PAGE_NUM word*/ 2606 /*define for page_num_31_0 field*/ 2607 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4 2608 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF 2609 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0 2610 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) 2611 2612 2613 /* 2614 ** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet 2615 */ 2616 2617 /*define for HEADER word*/ 2618 /*define for op field*/ 2619 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0 2620 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF 2621 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0 2622 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) 2623 2624 /*define for sub_op field*/ 2625 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0 2626 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF 2627 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 8 2628 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) 2629 2630 /*define for mode field*/ 2631 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0 2632 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001 2633 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 31 2634 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) 2635 2636 /*define for PATTERN word*/ 2637 /*define for pattern field*/ 2638 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1 2639 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF 2640 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0 2641 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) 2642 2643 /*define for CMP0_ADDR_START_LO word*/ 2644 /*define for cmp0_start_31_0 field*/ 2645 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2 2646 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF 2647 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0 2648 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) 2649 2650 /*define for CMP0_ADDR_START_HI word*/ 2651 /*define for cmp0_start_63_32 field*/ 2652 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3 2653 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF 2654 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0 2655 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) 2656 2657 /*define for CMP0_ADDR_END_LO word*/ 2658 /*define for cmp1_end_31_0 field*/ 2659 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset 4 2660 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF 2661 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift 0 2662 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift) 2663 2664 /*define for CMP0_ADDR_END_HI word*/ 2665 /*define for cmp1_end_63_32 field*/ 2666 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset 5 2667 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF 2668 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift 0 2669 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift) 2670 2671 /*define for CMP1_ADDR_START_LO word*/ 2672 /*define for cmp1_start_31_0 field*/ 2673 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6 2674 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF 2675 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0 2676 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) 2677 2678 /*define for CMP1_ADDR_START_HI word*/ 2679 /*define for cmp1_start_63_32 field*/ 2680 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7 2681 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF 2682 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0 2683 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) 2684 2685 /*define for CMP1_ADDR_END_LO word*/ 2686 /*define for cmp1_end_31_0 field*/ 2687 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8 2688 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF 2689 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0 2690 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) 2691 2692 /*define for CMP1_ADDR_END_HI word*/ 2693 /*define for cmp1_end_63_32 field*/ 2694 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9 2695 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF 2696 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0 2697 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) 2698 2699 /*define for REC_ADDR_LO word*/ 2700 /*define for rec_31_0 field*/ 2701 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10 2702 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF 2703 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0 2704 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) 2705 2706 /*define for REC_ADDR_HI word*/ 2707 /*define for rec_63_32 field*/ 2708 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11 2709 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF 2710 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0 2711 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) 2712 2713 /*define for RESERVED word*/ 2714 /*define for reserved field*/ 2715 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12 2716 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF 2717 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0 2718 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) 2719 2720 2721 /* 2722 ** Definitions for SDMA_PKT_ATOMIC packet 2723 */ 2724 2725 /*define for HEADER word*/ 2726 /*define for op field*/ 2727 #define SDMA_PKT_ATOMIC_HEADER_op_offset 0 2728 #define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF 2729 #define SDMA_PKT_ATOMIC_HEADER_op_shift 0 2730 #define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) 2731 2732 /*define for loop field*/ 2733 #define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 2734 #define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 2735 #define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 2736 #define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) 2737 2738 /*define for tmz field*/ 2739 #define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0 2740 #define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001 2741 #define SDMA_PKT_ATOMIC_HEADER_tmz_shift 18 2742 #define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) 2743 2744 /*define for atomic_op field*/ 2745 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 2746 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F 2747 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 2748 #define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) 2749 2750 /*define for ADDR_LO word*/ 2751 /*define for addr_31_0 field*/ 2752 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 2753 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 2754 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 2755 #define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) 2756 2757 /*define for ADDR_HI word*/ 2758 /*define for addr_63_32 field*/ 2759 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 2760 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 2761 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 2762 #define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) 2763 2764 /*define for SRC_DATA_LO word*/ 2765 /*define for src_data_31_0 field*/ 2766 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 2767 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF 2768 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 2769 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) 2770 2771 /*define for SRC_DATA_HI word*/ 2772 /*define for src_data_63_32 field*/ 2773 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 2774 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF 2775 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 2776 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) 2777 2778 /*define for CMP_DATA_LO word*/ 2779 /*define for cmp_data_31_0 field*/ 2780 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 2781 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF 2782 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 2783 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) 2784 2785 /*define for CMP_DATA_HI word*/ 2786 /*define for cmp_data_63_32 field*/ 2787 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 2788 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF 2789 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 2790 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) 2791 2792 /*define for LOOP_INTERVAL word*/ 2793 /*define for loop_interval field*/ 2794 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 2795 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF 2796 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 2797 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) 2798 2799 2800 /* 2801 ** Definitions for SDMA_PKT_TIMESTAMP_SET packet 2802 */ 2803 2804 /*define for HEADER word*/ 2805 /*define for op field*/ 2806 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 2807 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF 2808 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 2809 #define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) 2810 2811 /*define for sub_op field*/ 2812 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 2813 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF 2814 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 2815 #define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) 2816 2817 /*define for INIT_DATA_LO word*/ 2818 /*define for init_data_31_0 field*/ 2819 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 2820 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF 2821 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 2822 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) 2823 2824 /*define for INIT_DATA_HI word*/ 2825 /*define for init_data_63_32 field*/ 2826 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 2827 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF 2828 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 2829 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) 2830 2831 2832 /* 2833 ** Definitions for SDMA_PKT_TIMESTAMP_GET packet 2834 */ 2835 2836 /*define for HEADER word*/ 2837 /*define for op field*/ 2838 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 2839 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF 2840 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 2841 #define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) 2842 2843 /*define for sub_op field*/ 2844 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 2845 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF 2846 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 2847 #define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) 2848 2849 /*define for WRITE_ADDR_LO word*/ 2850 /*define for write_addr_31_3 field*/ 2851 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 2852 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 2853 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 2854 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) 2855 2856 /*define for WRITE_ADDR_HI word*/ 2857 /*define for write_addr_63_32 field*/ 2858 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 2859 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 2860 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 2861 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) 2862 2863 2864 /* 2865 ** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet 2866 */ 2867 2868 /*define for HEADER word*/ 2869 /*define for op field*/ 2870 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 2871 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF 2872 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 2873 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) 2874 2875 /*define for sub_op field*/ 2876 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 2877 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF 2878 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 2879 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) 2880 2881 /*define for WRITE_ADDR_LO word*/ 2882 /*define for write_addr_31_3 field*/ 2883 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 2884 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 2885 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 2886 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) 2887 2888 /*define for WRITE_ADDR_HI word*/ 2889 /*define for write_addr_63_32 field*/ 2890 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 2891 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 2892 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 2893 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) 2894 2895 2896 /* 2897 ** Definitions for SDMA_PKT_TRAP packet 2898 */ 2899 2900 /*define for HEADER word*/ 2901 /*define for op field*/ 2902 #define SDMA_PKT_TRAP_HEADER_op_offset 0 2903 #define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF 2904 #define SDMA_PKT_TRAP_HEADER_op_shift 0 2905 #define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) 2906 2907 /*define for sub_op field*/ 2908 #define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 2909 #define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF 2910 #define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 2911 #define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) 2912 2913 /*define for INT_CONTEXT word*/ 2914 /*define for int_context field*/ 2915 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 2916 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 2917 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 2918 #define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) 2919 2920 2921 /* 2922 ** Definitions for SDMA_PKT_DUMMY_TRAP packet 2923 */ 2924 2925 /*define for HEADER word*/ 2926 /*define for op field*/ 2927 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0 2928 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF 2929 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0 2930 #define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) 2931 2932 /*define for sub_op field*/ 2933 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0 2934 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF 2935 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 8 2936 #define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) 2937 2938 /*define for INT_CONTEXT word*/ 2939 /*define for int_context field*/ 2940 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1 2941 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 2942 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0 2943 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) 2944 2945 2946 /* 2947 ** Definitions for SDMA_PKT_NOP packet 2948 */ 2949 2950 /*define for HEADER word*/ 2951 /*define for op field*/ 2952 #define SDMA_PKT_NOP_HEADER_op_offset 0 2953 #define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF 2954 #define SDMA_PKT_NOP_HEADER_op_shift 0 2955 #define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) 2956 2957 /*define for sub_op field*/ 2958 #define SDMA_PKT_NOP_HEADER_sub_op_offset 0 2959 #define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF 2960 #define SDMA_PKT_NOP_HEADER_sub_op_shift 8 2961 #define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) 2962 2963 /*define for count field*/ 2964 #define SDMA_PKT_NOP_HEADER_count_offset 0 2965 #define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF 2966 #define SDMA_PKT_NOP_HEADER_count_shift 16 2967 #define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) 2968 2969 /*define for DATA0 word*/ 2970 /*define for data0 field*/ 2971 #define SDMA_PKT_NOP_DATA0_data0_offset 1 2972 #define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF 2973 #define SDMA_PKT_NOP_DATA0_data0_shift 0 2974 #define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) 2975 2976 2977 /* 2978 ** Definitions for SDMA_AQL_PKT_HEADER packet 2979 */ 2980 2981 /*define for HEADER word*/ 2982 /*define for format field*/ 2983 #define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0 2984 #define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF 2985 #define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0 2986 #define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) 2987 2988 /*define for barrier field*/ 2989 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0 2990 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001 2991 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 8 2992 #define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) 2993 2994 /*define for acquire_fence_scope field*/ 2995 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0 2996 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003 2997 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 9 2998 #define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) 2999 3000 /*define for release_fence_scope field*/ 3001 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0 3002 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003 3003 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 11 3004 #define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) 3005 3006 /*define for reserved field*/ 3007 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0 3008 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007 3009 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 13 3010 #define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) 3011 3012 /*define for op field*/ 3013 #define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0 3014 #define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F 3015 #define SDMA_AQL_PKT_HEADER_HEADER_op_shift 16 3016 #define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) 3017 3018 /*define for subop field*/ 3019 #define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0 3020 #define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007 3021 #define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 20 3022 #define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) 3023 3024 3025 /* 3026 ** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet 3027 */ 3028 3029 /*define for HEADER word*/ 3030 /*define for format field*/ 3031 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0 3032 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF 3033 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0 3034 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) 3035 3036 /*define for barrier field*/ 3037 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0 3038 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001 3039 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 8 3040 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) 3041 3042 /*define for acquire_fence_scope field*/ 3043 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0 3044 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003 3045 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 9 3046 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) 3047 3048 /*define for release_fence_scope field*/ 3049 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0 3050 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003 3051 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 11 3052 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) 3053 3054 /*define for reserved field*/ 3055 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0 3056 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007 3057 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 13 3058 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) 3059 3060 /*define for op field*/ 3061 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0 3062 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F 3063 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 16 3064 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) 3065 3066 /*define for subop field*/ 3067 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0 3068 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007 3069 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 20 3070 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) 3071 3072 /*define for RESERVED_DW1 word*/ 3073 /*define for reserved_dw1 field*/ 3074 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1 3075 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF 3076 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0 3077 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) 3078 3079 /*define for RETURN_ADDR_LO word*/ 3080 /*define for return_addr_31_0 field*/ 3081 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2 3082 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF 3083 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0 3084 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) 3085 3086 /*define for RETURN_ADDR_HI word*/ 3087 /*define for return_addr_63_32 field*/ 3088 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3 3089 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF 3090 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0 3091 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) 3092 3093 /*define for COUNT word*/ 3094 /*define for count field*/ 3095 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4 3096 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF 3097 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0 3098 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) 3099 3100 /*define for PARAMETER word*/ 3101 /*define for dst_sw field*/ 3102 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5 3103 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 3104 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 3105 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 3106 3107 /*define for src_sw field*/ 3108 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5 3109 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 3110 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 3111 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 3112 3113 /*define for SRC_ADDR_LO word*/ 3114 /*define for src_addr_31_0 field*/ 3115 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6 3116 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 3117 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 3118 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 3119 3120 /*define for SRC_ADDR_HI word*/ 3121 /*define for src_addr_63_32 field*/ 3122 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7 3123 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 3124 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 3125 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 3126 3127 /*define for DST_ADDR_LO word*/ 3128 /*define for dst_addr_31_0 field*/ 3129 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8 3130 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3131 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 3132 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 3133 3134 /*define for DST_ADDR_HI word*/ 3135 /*define for dst_addr_63_32 field*/ 3136 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9 3137 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3138 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 3139 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 3140 3141 /*define for RESERVED_DW10 word*/ 3142 /*define for reserved_dw10 field*/ 3143 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10 3144 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF 3145 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0 3146 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) 3147 3148 /*define for RESERVED_DW11 word*/ 3149 /*define for reserved_dw11 field*/ 3150 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11 3151 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF 3152 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0 3153 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) 3154 3155 /*define for RESERVED_DW12 word*/ 3156 /*define for reserved_dw12 field*/ 3157 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12 3158 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF 3159 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0 3160 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) 3161 3162 /*define for RESERVED_DW13 word*/ 3163 /*define for reserved_dw13 field*/ 3164 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13 3165 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF 3166 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0 3167 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) 3168 3169 /*define for COMPLETION_SIGNAL_LO word*/ 3170 /*define for completion_signal_31_0 field*/ 3171 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 3172 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF 3173 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 3174 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) 3175 3176 /*define for COMPLETION_SIGNAL_HI word*/ 3177 /*define for completion_signal_63_32 field*/ 3178 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 3179 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF 3180 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 3181 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) 3182 3183 3184 /* 3185 ** Definitions for SDMA_AQL_PKT_BARRIER_OR packet 3186 */ 3187 3188 /*define for HEADER word*/ 3189 /*define for format field*/ 3190 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0 3191 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF 3192 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0 3193 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) 3194 3195 /*define for barrier field*/ 3196 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0 3197 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001 3198 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 8 3199 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) 3200 3201 /*define for acquire_fence_scope field*/ 3202 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0 3203 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003 3204 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 9 3205 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) 3206 3207 /*define for release_fence_scope field*/ 3208 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0 3209 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003 3210 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 11 3211 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) 3212 3213 /*define for reserved field*/ 3214 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0 3215 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007 3216 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 13 3217 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) 3218 3219 /*define for op field*/ 3220 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0 3221 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F 3222 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 16 3223 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) 3224 3225 /*define for subop field*/ 3226 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0 3227 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007 3228 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 20 3229 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) 3230 3231 /*define for RESERVED_DW1 word*/ 3232 /*define for reserved_dw1 field*/ 3233 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1 3234 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF 3235 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0 3236 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) 3237 3238 /*define for DEPENDENT_ADDR_0_LO word*/ 3239 /*define for dependent_addr_0_31_0 field*/ 3240 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2 3241 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF 3242 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0 3243 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) 3244 3245 /*define for DEPENDENT_ADDR_0_HI word*/ 3246 /*define for dependent_addr_0_63_32 field*/ 3247 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3 3248 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF 3249 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0 3250 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) 3251 3252 /*define for DEPENDENT_ADDR_1_LO word*/ 3253 /*define for dependent_addr_1_31_0 field*/ 3254 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4 3255 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF 3256 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0 3257 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) 3258 3259 /*define for DEPENDENT_ADDR_1_HI word*/ 3260 /*define for dependent_addr_1_63_32 field*/ 3261 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5 3262 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF 3263 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0 3264 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) 3265 3266 /*define for DEPENDENT_ADDR_2_LO word*/ 3267 /*define for dependent_addr_2_31_0 field*/ 3268 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6 3269 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF 3270 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0 3271 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) 3272 3273 /*define for DEPENDENT_ADDR_2_HI word*/ 3274 /*define for dependent_addr_2_63_32 field*/ 3275 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7 3276 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF 3277 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0 3278 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) 3279 3280 /*define for DEPENDENT_ADDR_3_LO word*/ 3281 /*define for dependent_addr_3_31_0 field*/ 3282 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8 3283 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF 3284 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0 3285 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) 3286 3287 /*define for DEPENDENT_ADDR_3_HI word*/ 3288 /*define for dependent_addr_3_63_32 field*/ 3289 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9 3290 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF 3291 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0 3292 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) 3293 3294 /*define for DEPENDENT_ADDR_4_LO word*/ 3295 /*define for dependent_addr_4_31_0 field*/ 3296 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10 3297 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF 3298 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0 3299 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) 3300 3301 /*define for DEPENDENT_ADDR_4_HI word*/ 3302 /*define for dependent_addr_4_63_32 field*/ 3303 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11 3304 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF 3305 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0 3306 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) 3307 3308 /*define for RESERVED_DW12 word*/ 3309 /*define for reserved_dw12 field*/ 3310 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset 12 3311 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF 3312 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift 0 3313 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift) 3314 3315 /*define for RESERVED_DW13 word*/ 3316 /*define for reserved_dw13 field*/ 3317 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13 3318 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF 3319 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0 3320 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) 3321 3322 /*define for COMPLETION_SIGNAL_LO word*/ 3323 /*define for completion_signal_31_0 field*/ 3324 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 3325 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF 3326 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 3327 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) 3328 3329 /*define for COMPLETION_SIGNAL_HI word*/ 3330 /*define for completion_signal_63_32 field*/ 3331 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 3332 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF 3333 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 3334 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) 3335 3336 3337 #endif /* __SDMA_PKT_OPEN_H_ */ 3338
Indexes created Tue Sep 23 22:09:46 GMT 2025