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      1 /*	$NetBSD: dpcd_defs.h,v 1.2 2021/12/18 23:45:07 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2012-15 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: AMD
     25  *
     26  */
     27 
     28 #ifndef __DAL_DPCD_DEFS_H__
     29 #define __DAL_DPCD_DEFS_H__
     30 
     31 #include <drm/drm_dp_helper.h>
     32 #ifndef DP_SINK_HW_REVISION_START // can remove this once the define gets into linux drm_dp_helper.h
     33 #define DP_SINK_HW_REVISION_START 0x409
     34 #endif
     35 
     36 enum dpcd_revision {
     37 	DPCD_REV_10 = 0x10,
     38 	DPCD_REV_11 = 0x11,
     39 	DPCD_REV_12 = 0x12,
     40 	DPCD_REV_13 = 0x13,
     41 	DPCD_REV_14 = 0x14
     42 };
     43 
     44 /* these are the types stored at DOWNSTREAMPORT_PRESENT */
     45 enum dpcd_downstream_port_type {
     46 	DOWNSTREAM_DP = 0,
     47 	DOWNSTREAM_VGA,
     48 	DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS,/* DVI, HDMI, DP++ */
     49 	DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */
     50 };
     51 
     52 enum dpcd_link_test_patterns {
     53 	LINK_TEST_PATTERN_NONE = 0,
     54 	LINK_TEST_PATTERN_COLOR_RAMP,
     55 	LINK_TEST_PATTERN_VERTICAL_BARS,
     56 	LINK_TEST_PATTERN_COLOR_SQUARES
     57 };
     58 
     59 enum dpcd_test_color_format {
     60 	TEST_COLOR_FORMAT_RGB = 0,
     61 	TEST_COLOR_FORMAT_YCBCR422,
     62 	TEST_COLOR_FORMAT_YCBCR444
     63 };
     64 
     65 enum dpcd_test_bit_depth {
     66 	TEST_BIT_DEPTH_6 = 0,
     67 	TEST_BIT_DEPTH_8,
     68 	TEST_BIT_DEPTH_10,
     69 	TEST_BIT_DEPTH_12,
     70 	TEST_BIT_DEPTH_16
     71 };
     72 
     73 /* PHY (encoder) test patterns
     74 The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248)
     75 */
     76 enum dpcd_phy_test_patterns {
     77 	PHY_TEST_PATTERN_NONE = 0,
     78 	PHY_TEST_PATTERN_D10_2,
     79 	PHY_TEST_PATTERN_SYMBOL_ERROR,
     80 	PHY_TEST_PATTERN_PRBS7,
     81 	PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */
     82 	PHY_TEST_PATTERN_CP2520_1,
     83 	PHY_TEST_PATTERN_CP2520_2,
     84 	PHY_TEST_PATTERN_CP2520_3, /* same as TPS4 */
     85 };
     86 
     87 enum dpcd_test_dyn_range {
     88 	TEST_DYN_RANGE_VESA = 0,
     89 	TEST_DYN_RANGE_CEA
     90 };
     91 
     92 enum dpcd_audio_test_pattern {
     93 	AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */
     94 	AUDIO_TEST_PATTERN_SAWTOOTH
     95 };
     96 
     97 enum dpcd_audio_sampling_rate {
     98 	AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */
     99 	AUDIO_SAMPLING_RATE_44_1KHZ,
    100 	AUDIO_SAMPLING_RATE_48KHZ,
    101 	AUDIO_SAMPLING_RATE_88_2KHZ,
    102 	AUDIO_SAMPLING_RATE_96KHZ,
    103 	AUDIO_SAMPLING_RATE_176_4KHZ,
    104 	AUDIO_SAMPLING_RATE_192KHZ
    105 };
    106 
    107 enum dpcd_audio_channels {
    108 	AUDIO_CHANNELS_1 = 0,/* direct HW translation */
    109 	AUDIO_CHANNELS_2,
    110 	AUDIO_CHANNELS_3,
    111 	AUDIO_CHANNELS_4,
    112 	AUDIO_CHANNELS_5,
    113 	AUDIO_CHANNELS_6,
    114 	AUDIO_CHANNELS_7,
    115 	AUDIO_CHANNELS_8,
    116 
    117 	AUDIO_CHANNELS_COUNT
    118 };
    119 
    120 enum dpcd_audio_test_pattern_periods {
    121 	DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */
    122 	DPCD_AUDIO_TEST_PATTERN_PERIOD_3,
    123 	DPCD_AUDIO_TEST_PATTERN_PERIOD_6,
    124 	DPCD_AUDIO_TEST_PATTERN_PERIOD_12,
    125 	DPCD_AUDIO_TEST_PATTERN_PERIOD_24,
    126 	DPCD_AUDIO_TEST_PATTERN_PERIOD_48,
    127 	DPCD_AUDIO_TEST_PATTERN_PERIOD_96,
    128 	DPCD_AUDIO_TEST_PATTERN_PERIOD_192,
    129 	DPCD_AUDIO_TEST_PATTERN_PERIOD_384,
    130 	DPCD_AUDIO_TEST_PATTERN_PERIOD_768,
    131 	DPCD_AUDIO_TEST_PATTERN_PERIOD_1536
    132 };
    133 
    134 /* This enum is for programming DPCD TRAINING_PATTERN_SET */
    135 enum dpcd_training_patterns {
    136 	DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */
    137 	DPCD_TRAINING_PATTERN_1,
    138 	DPCD_TRAINING_PATTERN_2,
    139 	DPCD_TRAINING_PATTERN_3,
    140 	DPCD_TRAINING_PATTERN_4 = 7
    141 };
    142 
    143 /* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus
    144 It defines the possible PSR states. */
    145 enum dpcd_psr_sink_states {
    146 	PSR_SINK_STATE_INACTIVE = 0,
    147 	PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1,
    148 	PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2,
    149 	PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3,
    150 	PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4,
    151 	PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7,
    152 };
    153 
    154 #endif /* __DAL_DPCD_DEFS_H__ */
    155