1 /* $NetBSD: amd_pcie.h,v 1.2 2021/12/18 23:45:08 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef __AMD_PCIE_H__ 26 #define __AMD_PCIE_H__ 27 28 /* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */ 29 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000 30 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000 31 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000 32 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000 33 #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000 34 #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16 35 36 /* Following flags shows PCIe link speed supported by ASIC H/W.*/ 37 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001 38 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002 39 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004 40 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008 41 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF 42 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0 43 44 /* gen: chipset 1/2, asic 1/2/3 */ 45 #define AMDGPU_DEFAULT_PCIE_GEN_MASK (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \ 46 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \ 47 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \ 48 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \ 49 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3) 50 51 /* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */ 52 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x00010000 53 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 0x00020000 54 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 0x00040000 55 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 0x00080000 56 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 0x00100000 57 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 0x00200000 58 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 0x00400000 59 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT 16 60 61 /* 1/2/4/8/16 lanes */ 62 #define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \ 63 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \ 64 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \ 65 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \ 66 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 67 68 #endif 69
Indexes created Sat Sep 20 22:09:52 GMT 2025