1 /* $NetBSD: arct_ip_offset.h,v 1.2 2021/12/18 23:45:08 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _arct_ip_offset_HEADER 24 #define _arct_ip_offset_HEADER 25 26 #define MAX_INSTANCE 8 27 #define MAX_SEGMENT 6 28 29 30 struct IP_BASE_INSTANCE 31 { 32 unsigned int segment[MAX_SEGMENT]; 33 }; 34 35 struct IP_BASE 36 { 37 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 38 }; 39 40 41 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x00012460, 0x00408C00, 0, 0, 0 } }, 42 { { 0, 0, 0, 0, 0, 0 } }, 43 { { 0, 0, 0, 0, 0, 0 } }, 44 { { 0, 0, 0, 0, 0, 0 } }, 45 { { 0, 0, 0, 0, 0, 0 } }, 46 { { 0, 0, 0, 0, 0, 0 } }, 47 { { 0, 0, 0, 0, 0, 0 } }, 48 { { 0, 0, 0, 0, 0, 0 } } } }; 49 static const struct IP_BASE CLK_BASE ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, 0 } }, 50 { { 0x000120E0, 0x00016E00, 0x00401C00, 0, 0, 0 } }, 51 { { 0x00012100, 0x00017000, 0x00402000, 0, 0, 0 } }, 52 { { 0x00012120, 0x00017200, 0x00402400, 0, 0, 0 } }, 53 { { 0x000136C0, 0x0001B000, 0x0042D800, 0, 0, 0 } }, 54 { { 0x00013720, 0x0001B200, 0x0042E400, 0, 0, 0 } }, 55 { { 0x000125E0, 0x00017E00, 0x0040BC00, 0, 0, 0 } }, 56 { { 0, 0, 0, 0, 0, 0 } } } }; 57 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x000125C0, 0x0040B800, 0, 0, 0 } }, 58 { { 0, 0, 0, 0, 0, 0 } }, 59 { { 0, 0, 0, 0, 0, 0 } }, 60 { { 0, 0, 0, 0, 0, 0 } }, 61 { { 0, 0, 0, 0, 0, 0 } }, 62 { { 0, 0, 0, 0, 0, 0 } }, 63 { { 0, 0, 0, 0, 0, 0 } }, 64 { { 0, 0, 0, 0, 0, 0 } } } }; 65 static const struct IP_BASE FUSE_BASE ={ { { { 0x000120A0, 0x00017400, 0x00401400, 0, 0, 0 } }, 66 { { 0, 0, 0, 0, 0, 0 } }, 67 { { 0, 0, 0, 0, 0, 0 } }, 68 { { 0, 0, 0, 0, 0, 0 } }, 69 { { 0, 0, 0, 0, 0, 0 } }, 70 { { 0, 0, 0, 0, 0, 0 } }, 71 { { 0, 0, 0, 0, 0, 0 } }, 72 { { 0, 0, 0, 0, 0, 0 } } } }; 73 static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x00012160, 0x00402C00, 0, 0 } }, 74 { { 0, 0, 0, 0, 0, 0 } }, 75 { { 0, 0, 0, 0, 0, 0 } }, 76 { { 0, 0, 0, 0, 0, 0 } }, 77 { { 0, 0, 0, 0, 0, 0 } }, 78 { { 0, 0, 0, 0, 0, 0 } }, 79 { { 0, 0, 0, 0, 0, 0 } }, 80 { { 0, 0, 0, 0, 0, 0 } } } }; 81 static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x00012520, 0x0040A400, 0, 0, 0 } }, 82 { { 0, 0, 0, 0, 0, 0 } }, 83 { { 0, 0, 0, 0, 0, 0 } }, 84 { { 0, 0, 0, 0, 0, 0 } }, 85 { { 0, 0, 0, 0, 0, 0 } }, 86 { { 0, 0, 0, 0, 0, 0 } }, 87 { { 0, 0, 0, 0, 0, 0 } }, 88 { { 0, 0, 0, 0, 0, 0 } } } }; 89 static const struct IP_BASE MMHUB_BASE ={ { { { 0x00012440, 0x0001A000, 0x00408800, 0, 0, 0 } }, 90 { { 0, 0, 0, 0, 0, 0 } }, 91 { { 0, 0, 0, 0, 0, 0 } }, 92 { { 0, 0, 0, 0, 0, 0 } }, 93 { { 0, 0, 0, 0, 0, 0 } }, 94 { { 0, 0, 0, 0, 0, 0 } }, 95 { { 0, 0, 0, 0, 0, 0 } }, 96 { { 0, 0, 0, 0, 0, 0 } } } }; 97 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, 98 { { 0, 0, 0, 0, 0, 0 } }, 99 { { 0, 0, 0, 0, 0, 0 } }, 100 { { 0, 0, 0, 0, 0, 0 } }, 101 { { 0, 0, 0, 0, 0, 0 } }, 102 { { 0, 0, 0, 0, 0, 0 } }, 103 { { 0, 0, 0, 0, 0, 0 } }, 104 { { 0, 0, 0, 0, 0, 0 } } } }; 105 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, 106 { { 0, 0, 0, 0, 0, 0 } }, 107 { { 0, 0, 0, 0, 0, 0 } }, 108 { { 0, 0, 0, 0, 0, 0 } }, 109 { { 0, 0, 0, 0, 0, 0 } }, 110 { { 0, 0, 0, 0, 0, 0 } }, 111 { { 0, 0, 0, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0, 0 } } } }; 113 static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x00012D80, 0x0041B000 } }, 114 { { 0, 0, 0, 0, 0, 0 } }, 115 { { 0, 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0, 0 } }, 118 { { 0, 0, 0, 0, 0, 0 } }, 119 { { 0, 0, 0, 0, 0, 0 } }, 120 { { 0, 0, 0, 0, 0, 0 } } } }; 121 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x00012500, 0x0040A000, 0, 0, 0 } }, 122 { { 0, 0, 0, 0, 0, 0 } }, 123 { { 0, 0, 0, 0, 0, 0 } }, 124 { { 0, 0, 0, 0, 0, 0 } }, 125 { { 0, 0, 0, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0, 0 } } } }; 129 static const struct IP_BASE PCIE0_BASE ={ { { { 0x000128C0, 0x00411800, 0x04440000, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0, 0 } }, 132 { { 0, 0, 0, 0, 0, 0 } }, 133 { { 0, 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0, 0 } }, 135 { { 0, 0, 0, 0, 0, 0 } }, 136 { { 0, 0, 0, 0, 0, 0 } } } }; 137 static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } }, 138 { { 0, 0, 0, 0, 0, 0 } }, 139 { { 0, 0, 0, 0, 0, 0 } }, 140 { { 0, 0, 0, 0, 0, 0 } }, 141 { { 0, 0, 0, 0, 0, 0 } }, 142 { { 0, 0, 0, 0, 0, 0 } }, 143 { { 0, 0, 0, 0, 0, 0 } }, 144 { { 0, 0, 0, 0, 0, 0 } } } }; 145 static const struct IP_BASE SDMA1_BASE ={ { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } }, 146 { { 0, 0, 0, 0, 0, 0 } }, 147 { { 0, 0, 0, 0, 0, 0 } }, 148 { { 0, 0, 0, 0, 0, 0 } }, 149 { { 0, 0, 0, 0, 0, 0 } }, 150 { { 0, 0, 0, 0, 0, 0 } }, 151 { { 0, 0, 0, 0, 0, 0 } }, 152 { { 0, 0, 0, 0, 0, 0 } } } }; 153 static const struct IP_BASE SDMA2_BASE ={ { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } }, 154 { { 0, 0, 0, 0, 0, 0 } }, 155 { { 0, 0, 0, 0, 0, 0 } }, 156 { { 0, 0, 0, 0, 0, 0 } }, 157 { { 0, 0, 0, 0, 0, 0 } }, 158 { { 0, 0, 0, 0, 0, 0 } }, 159 { { 0, 0, 0, 0, 0, 0 } }, 160 { { 0, 0, 0, 0, 0, 0 } } } }; 161 static const struct IP_BASE SDMA3_BASE ={ { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } }, 162 { { 0, 0, 0, 0, 0, 0 } }, 163 { { 0, 0, 0, 0, 0, 0 } }, 164 { { 0, 0, 0, 0, 0, 0 } }, 165 { { 0, 0, 0, 0, 0, 0 } }, 166 { { 0, 0, 0, 0, 0, 0 } }, 167 { { 0, 0, 0, 0, 0, 0 } }, 168 { { 0, 0, 0, 0, 0, 0 } } } }; 169 static const struct IP_BASE SDMA4_BASE ={ { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } }, 170 { { 0, 0, 0, 0, 0, 0 } }, 171 { { 0, 0, 0, 0, 0, 0 } }, 172 { { 0, 0, 0, 0, 0, 0 } }, 173 { { 0, 0, 0, 0, 0, 0 } }, 174 { { 0, 0, 0, 0, 0, 0 } }, 175 { { 0, 0, 0, 0, 0, 0 } }, 176 { { 0, 0, 0, 0, 0, 0 } } } }; 177 static const struct IP_BASE SDMA5_BASE ={ { { { 0x000137C0, 0x0001EC00, 0x0042F800, 0, 0, 0 } }, 178 { { 0, 0, 0, 0, 0, 0 } }, 179 { { 0, 0, 0, 0, 0, 0 } }, 180 { { 0, 0, 0, 0, 0, 0 } }, 181 { { 0, 0, 0, 0, 0, 0 } }, 182 { { 0, 0, 0, 0, 0, 0 } }, 183 { { 0, 0, 0, 0, 0, 0 } }, 184 { { 0, 0, 0, 0, 0, 0 } } } }; 185 static const struct IP_BASE SDMA6_BASE ={ { { { 0x000137E0, 0x0001F000, 0x0042FC00, 0, 0, 0 } }, 186 { { 0, 0, 0, 0, 0, 0 } }, 187 { { 0, 0, 0, 0, 0, 0 } }, 188 { { 0, 0, 0, 0, 0, 0 } }, 189 { { 0, 0, 0, 0, 0, 0 } }, 190 { { 0, 0, 0, 0, 0, 0 } }, 191 { { 0, 0, 0, 0, 0, 0 } }, 192 { { 0, 0, 0, 0, 0, 0 } } } }; 193 static const struct IP_BASE SDMA7_BASE ={ { { { 0x00013800, 0x0001F400, 0x00430000, 0, 0, 0 } }, 194 { { 0, 0, 0, 0, 0, 0 } }, 195 { { 0, 0, 0, 0, 0, 0 } }, 196 { { 0, 0, 0, 0, 0, 0 } }, 197 { { 0, 0, 0, 0, 0, 0 } }, 198 { { 0, 0, 0, 0, 0, 0 } }, 199 { { 0, 0, 0, 0, 0, 0 } }, 200 { { 0, 0, 0, 0, 0, 0 } } } }; 201 static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } }, 202 { { 0, 0, 0, 0, 0, 0 } }, 203 { { 0, 0, 0, 0, 0, 0 } }, 204 { { 0, 0, 0, 0, 0, 0 } }, 205 { { 0, 0, 0, 0, 0, 0 } }, 206 { { 0, 0, 0, 0, 0, 0 } } } }; 207 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, 208 { { 0, 0, 0, 0, 0, 0 } }, 209 { { 0, 0, 0, 0, 0, 0 } }, 210 { { 0, 0, 0, 0, 0, 0 } }, 211 { { 0, 0, 0, 0, 0, 0 } }, 212 { { 0, 0, 0, 0, 0, 0 } } } }; 213 static const struct IP_BASE UMC_BASE ={ { { { 0x000132C0, 0x00014000, 0x00425800, 0, 0, 0 } }, 214 { { 0x000132E0, 0x00054000, 0x00425C00, 0, 0, 0 } }, 215 { { 0x00013300, 0x00094000, 0x00426000, 0, 0, 0 } }, 216 { { 0x00013320, 0x000D4000, 0x00426400, 0, 0, 0 } }, 217 { { 0x00013340, 0x00114000, 0x00426800, 0, 0, 0 } }, 218 { { 0x00013360, 0x00154000, 0x00426C00, 0, 0, 0 } }, 219 { { 0x00013380, 0x00194000, 0x00427000, 0, 0, 0 } }, 220 { { 0x000133A0, 0x001D4000, 0x00427400, 0, 0, 0 } } } }; 221 static const struct IP_BASE UVD_BASE ={ { { { 0x00007800, 0x00007E00, 0x00012180, 0x00403000, 0, 0 } }, 222 { { 0x00007A00, 0x00009000, 0x000136E0, 0x0042DC00, 0, 0 } }, 223 { { 0, 0, 0, 0, 0, 0 } }, 224 { { 0, 0, 0, 0, 0, 0 } }, 225 { { 0, 0, 0, 0, 0, 0 } }, 226 { { 0, 0, 0, 0, 0, 0 } }, 227 { { 0, 0, 0, 0, 0, 0 } }, 228 { { 0, 0, 0, 0, 0, 0 } } } }; 229 static const struct IP_BASE DBGU_IO_BASE ={ { { { 0x000001E0, 0x000125A0, 0x0040B400, 0, 0, 0 } }, 230 { { 0, 0, 0, 0, 0, 0 } }, 231 { { 0, 0, 0, 0, 0, 0 } }, 232 { { 0, 0, 0, 0, 0, 0 } }, 233 { { 0, 0, 0, 0, 0, 0 } }, 234 { { 0, 0, 0, 0, 0, 0 } }, 235 { { 0, 0, 0, 0, 0, 0 } }, 236 { { 0, 0, 0, 0, 0, 0 } } } }; 237 static const struct IP_BASE RSMU_BASE ={ { { { 0x00012000, 0, 0, 0, 0, 0 } }, 238 { { 0, 0, 0, 0, 0, 0 } }, 239 { { 0, 0, 0, 0, 0, 0 } }, 240 { { 0, 0, 0, 0, 0, 0 } }, 241 { { 0, 0, 0, 0, 0, 0 } }, 242 { { 0, 0, 0, 0, 0, 0 } }, 243 { { 0, 0, 0, 0, 0, 0 } }, 244 { { 0, 0, 0, 0, 0, 0 } } } }; 245 246 247 248 #define ATHUB_BASE__INST0_SEG0 0x00000C20 249 #define ATHUB_BASE__INST0_SEG1 0x00012460 250 #define ATHUB_BASE__INST0_SEG2 0x00408C00 251 #define ATHUB_BASE__INST0_SEG3 0 252 #define ATHUB_BASE__INST0_SEG4 0 253 #define ATHUB_BASE__INST0_SEG5 0 254 255 #define ATHUB_BASE__INST1_SEG0 0 256 #define ATHUB_BASE__INST1_SEG1 0 257 #define ATHUB_BASE__INST1_SEG2 0 258 #define ATHUB_BASE__INST1_SEG3 0 259 #define ATHUB_BASE__INST1_SEG4 0 260 #define ATHUB_BASE__INST1_SEG5 0 261 262 #define ATHUB_BASE__INST2_SEG0 0 263 #define ATHUB_BASE__INST2_SEG1 0 264 #define ATHUB_BASE__INST2_SEG2 0 265 #define ATHUB_BASE__INST2_SEG3 0 266 #define ATHUB_BASE__INST2_SEG4 0 267 #define ATHUB_BASE__INST2_SEG5 0 268 269 #define ATHUB_BASE__INST3_SEG0 0 270 #define ATHUB_BASE__INST3_SEG1 0 271 #define ATHUB_BASE__INST3_SEG2 0 272 #define ATHUB_BASE__INST3_SEG3 0 273 #define ATHUB_BASE__INST3_SEG4 0 274 #define ATHUB_BASE__INST3_SEG5 0 275 276 #define ATHUB_BASE__INST4_SEG0 0 277 #define ATHUB_BASE__INST4_SEG1 0 278 #define ATHUB_BASE__INST4_SEG2 0 279 #define ATHUB_BASE__INST4_SEG3 0 280 #define ATHUB_BASE__INST4_SEG4 0 281 #define ATHUB_BASE__INST4_SEG5 0 282 283 #define ATHUB_BASE__INST5_SEG0 0 284 #define ATHUB_BASE__INST5_SEG1 0 285 #define ATHUB_BASE__INST5_SEG2 0 286 #define ATHUB_BASE__INST5_SEG3 0 287 #define ATHUB_BASE__INST5_SEG4 0 288 #define ATHUB_BASE__INST5_SEG5 0 289 290 #define ATHUB_BASE__INST6_SEG0 0 291 #define ATHUB_BASE__INST6_SEG1 0 292 #define ATHUB_BASE__INST6_SEG2 0 293 #define ATHUB_BASE__INST6_SEG3 0 294 #define ATHUB_BASE__INST6_SEG4 0 295 #define ATHUB_BASE__INST6_SEG5 0 296 297 #define ATHUB_BASE__INST7_SEG0 0 298 #define ATHUB_BASE__INST7_SEG1 0 299 #define ATHUB_BASE__INST7_SEG2 0 300 #define ATHUB_BASE__INST7_SEG3 0 301 #define ATHUB_BASE__INST7_SEG4 0 302 #define ATHUB_BASE__INST7_SEG5 0 303 304 #define CLK_BASE__INST0_SEG0 0x000120C0 305 #define CLK_BASE__INST0_SEG1 0x00016C00 306 #define CLK_BASE__INST0_SEG2 0x00401800 307 #define CLK_BASE__INST0_SEG3 0 308 #define CLK_BASE__INST0_SEG4 0 309 #define CLK_BASE__INST0_SEG5 0 310 311 #define CLK_BASE__INST1_SEG0 0x000120E0 312 #define CLK_BASE__INST1_SEG1 0x00016E00 313 #define CLK_BASE__INST1_SEG2 0x00401C00 314 #define CLK_BASE__INST1_SEG3 0 315 #define CLK_BASE__INST1_SEG4 0 316 #define CLK_BASE__INST1_SEG5 0 317 318 #define CLK_BASE__INST2_SEG0 0x00012100 319 #define CLK_BASE__INST2_SEG1 0x00017000 320 #define CLK_BASE__INST2_SEG2 0x00402000 321 #define CLK_BASE__INST2_SEG3 0 322 #define CLK_BASE__INST2_SEG4 0 323 #define CLK_BASE__INST2_SEG5 0 324 325 #define CLK_BASE__INST3_SEG0 0x00012120 326 #define CLK_BASE__INST3_SEG1 0x00017200 327 #define CLK_BASE__INST3_SEG2 0x00402400 328 #define CLK_BASE__INST3_SEG3 0 329 #define CLK_BASE__INST3_SEG4 0 330 #define CLK_BASE__INST3_SEG5 0 331 332 #define CLK_BASE__INST4_SEG0 0x000136C0 333 #define CLK_BASE__INST4_SEG1 0x0001B000 334 #define CLK_BASE__INST4_SEG2 0x0042D800 335 #define CLK_BASE__INST4_SEG3 0 336 #define CLK_BASE__INST4_SEG4 0 337 #define CLK_BASE__INST4_SEG5 0 338 339 #define CLK_BASE__INST5_SEG0 0x00013720 340 #define CLK_BASE__INST5_SEG1 0x0001B200 341 #define CLK_BASE__INST5_SEG2 0x0042E400 342 #define CLK_BASE__INST5_SEG3 0 343 #define CLK_BASE__INST5_SEG4 0 344 #define CLK_BASE__INST5_SEG5 0 345 346 #define CLK_BASE__INST6_SEG0 0x000125E0 347 #define CLK_BASE__INST6_SEG1 0x00017E00 348 #define CLK_BASE__INST6_SEG2 0x0040BC00 349 #define CLK_BASE__INST6_SEG3 0 350 #define CLK_BASE__INST6_SEG4 0 351 #define CLK_BASE__INST6_SEG5 0 352 353 #define CLK_BASE__INST7_SEG0 0 354 #define CLK_BASE__INST7_SEG1 0 355 #define CLK_BASE__INST7_SEG2 0 356 #define CLK_BASE__INST7_SEG3 0 357 #define CLK_BASE__INST7_SEG4 0 358 #define CLK_BASE__INST7_SEG5 0 359 360 #define DF_BASE__INST0_SEG0 0x00007000 361 #define DF_BASE__INST0_SEG1 0x000125C0 362 #define DF_BASE__INST0_SEG2 0x0040B800 363 #define DF_BASE__INST0_SEG3 0 364 #define DF_BASE__INST0_SEG4 0 365 #define DF_BASE__INST0_SEG5 0 366 367 #define DF_BASE__INST1_SEG0 0 368 #define DF_BASE__INST1_SEG1 0 369 #define DF_BASE__INST1_SEG2 0 370 #define DF_BASE__INST1_SEG3 0 371 #define DF_BASE__INST1_SEG4 0 372 #define DF_BASE__INST1_SEG5 0 373 374 #define DF_BASE__INST2_SEG0 0 375 #define DF_BASE__INST2_SEG1 0 376 #define DF_BASE__INST2_SEG2 0 377 #define DF_BASE__INST2_SEG3 0 378 #define DF_BASE__INST2_SEG4 0 379 #define DF_BASE__INST2_SEG5 0 380 381 #define DF_BASE__INST3_SEG0 0 382 #define DF_BASE__INST3_SEG1 0 383 #define DF_BASE__INST3_SEG2 0 384 #define DF_BASE__INST3_SEG3 0 385 #define DF_BASE__INST3_SEG4 0 386 #define DF_BASE__INST3_SEG5 0 387 388 #define DF_BASE__INST4_SEG0 0 389 #define DF_BASE__INST4_SEG1 0 390 #define DF_BASE__INST4_SEG2 0 391 #define DF_BASE__INST4_SEG3 0 392 #define DF_BASE__INST4_SEG4 0 393 #define DF_BASE__INST4_SEG5 0 394 395 #define DF_BASE__INST5_SEG0 0 396 #define DF_BASE__INST5_SEG1 0 397 #define DF_BASE__INST5_SEG2 0 398 #define DF_BASE__INST5_SEG3 0 399 #define DF_BASE__INST5_SEG4 0 400 #define DF_BASE__INST5_SEG5 0 401 402 #define DF_BASE__INST6_SEG0 0 403 #define DF_BASE__INST6_SEG1 0 404 #define DF_BASE__INST6_SEG2 0 405 #define DF_BASE__INST6_SEG3 0 406 #define DF_BASE__INST6_SEG4 0 407 #define DF_BASE__INST6_SEG5 0 408 409 #define DF_BASE__INST7_SEG0 0 410 #define DF_BASE__INST7_SEG1 0 411 #define DF_BASE__INST7_SEG2 0 412 #define DF_BASE__INST7_SEG3 0 413 #define DF_BASE__INST7_SEG4 0 414 #define DF_BASE__INST7_SEG5 0 415 416 #define FUSE_BASE__INST0_SEG0 0x000120A0 417 #define FUSE_BASE__INST0_SEG1 0x00017400 418 #define FUSE_BASE__INST0_SEG2 0x00401400 419 #define FUSE_BASE__INST0_SEG3 0 420 #define FUSE_BASE__INST0_SEG4 0 421 #define FUSE_BASE__INST0_SEG5 0 422 423 #define FUSE_BASE__INST1_SEG0 0 424 #define FUSE_BASE__INST1_SEG1 0 425 #define FUSE_BASE__INST1_SEG2 0 426 #define FUSE_BASE__INST1_SEG3 0 427 #define FUSE_BASE__INST1_SEG4 0 428 #define FUSE_BASE__INST1_SEG5 0 429 430 #define FUSE_BASE__INST2_SEG0 0 431 #define FUSE_BASE__INST2_SEG1 0 432 #define FUSE_BASE__INST2_SEG2 0 433 #define FUSE_BASE__INST2_SEG3 0 434 #define FUSE_BASE__INST2_SEG4 0 435 #define FUSE_BASE__INST2_SEG5 0 436 437 #define FUSE_BASE__INST3_SEG0 0 438 #define FUSE_BASE__INST3_SEG1 0 439 #define FUSE_BASE__INST3_SEG2 0 440 #define FUSE_BASE__INST3_SEG3 0 441 #define FUSE_BASE__INST3_SEG4 0 442 #define FUSE_BASE__INST3_SEG5 0 443 444 #define FUSE_BASE__INST4_SEG0 0 445 #define FUSE_BASE__INST4_SEG1 0 446 #define FUSE_BASE__INST4_SEG2 0 447 #define FUSE_BASE__INST4_SEG3 0 448 #define FUSE_BASE__INST4_SEG4 0 449 #define FUSE_BASE__INST4_SEG5 0 450 451 #define FUSE_BASE__INST5_SEG0 0 452 #define FUSE_BASE__INST5_SEG1 0 453 #define FUSE_BASE__INST5_SEG2 0 454 #define FUSE_BASE__INST5_SEG3 0 455 #define FUSE_BASE__INST5_SEG4 0 456 #define FUSE_BASE__INST5_SEG5 0 457 458 #define FUSE_BASE__INST6_SEG0 0 459 #define FUSE_BASE__INST6_SEG1 0 460 #define FUSE_BASE__INST6_SEG2 0 461 #define FUSE_BASE__INST6_SEG3 0 462 #define FUSE_BASE__INST6_SEG4 0 463 #define FUSE_BASE__INST6_SEG5 0 464 465 #define FUSE_BASE__INST7_SEG0 0 466 #define FUSE_BASE__INST7_SEG1 0 467 #define FUSE_BASE__INST7_SEG2 0 468 #define FUSE_BASE__INST7_SEG3 0 469 #define FUSE_BASE__INST7_SEG4 0 470 #define FUSE_BASE__INST7_SEG5 0 471 472 #define GC_BASE__INST0_SEG0 0x00002000 473 #define GC_BASE__INST0_SEG1 0x0000A000 474 #define GC_BASE__INST0_SEG2 0x00012160 475 #define GC_BASE__INST0_SEG3 0x00402C00 476 #define GC_BASE__INST0_SEG4 0 477 #define GC_BASE__INST0_SEG5 0 478 479 #define GC_BASE__INST1_SEG0 0 480 #define GC_BASE__INST1_SEG1 0 481 #define GC_BASE__INST1_SEG2 0 482 #define GC_BASE__INST1_SEG3 0 483 #define GC_BASE__INST1_SEG4 0 484 #define GC_BASE__INST1_SEG5 0 485 486 #define GC_BASE__INST2_SEG0 0 487 #define GC_BASE__INST2_SEG1 0 488 #define GC_BASE__INST2_SEG2 0 489 #define GC_BASE__INST2_SEG3 0 490 #define GC_BASE__INST2_SEG4 0 491 #define GC_BASE__INST2_SEG5 0 492 493 #define GC_BASE__INST3_SEG0 0 494 #define GC_BASE__INST3_SEG1 0 495 #define GC_BASE__INST3_SEG2 0 496 #define GC_BASE__INST3_SEG3 0 497 #define GC_BASE__INST3_SEG4 0 498 #define GC_BASE__INST3_SEG5 0 499 500 #define GC_BASE__INST4_SEG0 0 501 #define GC_BASE__INST4_SEG1 0 502 #define GC_BASE__INST4_SEG2 0 503 #define GC_BASE__INST4_SEG3 0 504 #define GC_BASE__INST4_SEG4 0 505 #define GC_BASE__INST4_SEG5 0 506 507 #define GC_BASE__INST5_SEG0 0 508 #define GC_BASE__INST5_SEG1 0 509 #define GC_BASE__INST5_SEG2 0 510 #define GC_BASE__INST5_SEG3 0 511 #define GC_BASE__INST5_SEG4 0 512 #define GC_BASE__INST5_SEG5 0 513 514 #define GC_BASE__INST6_SEG0 0 515 #define GC_BASE__INST6_SEG1 0 516 #define GC_BASE__INST6_SEG2 0 517 #define GC_BASE__INST6_SEG3 0 518 #define GC_BASE__INST6_SEG4 0 519 #define GC_BASE__INST6_SEG5 0 520 521 #define GC_BASE__INST7_SEG0 0 522 #define GC_BASE__INST7_SEG1 0 523 #define GC_BASE__INST7_SEG2 0 524 #define GC_BASE__INST7_SEG3 0 525 #define GC_BASE__INST7_SEG4 0 526 #define GC_BASE__INST7_SEG5 0 527 528 #define HDP_BASE__INST0_SEG0 0x00000F20 529 #define HDP_BASE__INST0_SEG1 0x00012520 530 #define HDP_BASE__INST0_SEG2 0x0040A400 531 #define HDP_BASE__INST0_SEG3 0 532 #define HDP_BASE__INST0_SEG4 0 533 #define HDP_BASE__INST0_SEG5 0 534 535 #define HDP_BASE__INST1_SEG0 0 536 #define HDP_BASE__INST1_SEG1 0 537 #define HDP_BASE__INST1_SEG2 0 538 #define HDP_BASE__INST1_SEG3 0 539 #define HDP_BASE__INST1_SEG4 0 540 #define HDP_BASE__INST1_SEG5 0 541 542 #define HDP_BASE__INST2_SEG0 0 543 #define HDP_BASE__INST2_SEG1 0 544 #define HDP_BASE__INST2_SEG2 0 545 #define HDP_BASE__INST2_SEG3 0 546 #define HDP_BASE__INST2_SEG4 0 547 #define HDP_BASE__INST2_SEG5 0 548 549 #define HDP_BASE__INST3_SEG0 0 550 #define HDP_BASE__INST3_SEG1 0 551 #define HDP_BASE__INST3_SEG2 0 552 #define HDP_BASE__INST3_SEG3 0 553 #define HDP_BASE__INST3_SEG4 0 554 #define HDP_BASE__INST3_SEG5 0 555 556 #define HDP_BASE__INST4_SEG0 0 557 #define HDP_BASE__INST4_SEG1 0 558 #define HDP_BASE__INST4_SEG2 0 559 #define HDP_BASE__INST4_SEG3 0 560 #define HDP_BASE__INST4_SEG4 0 561 #define HDP_BASE__INST4_SEG5 0 562 563 #define HDP_BASE__INST5_SEG0 0 564 #define HDP_BASE__INST5_SEG1 0 565 #define HDP_BASE__INST5_SEG2 0 566 #define HDP_BASE__INST5_SEG3 0 567 #define HDP_BASE__INST5_SEG4 0 568 #define HDP_BASE__INST5_SEG5 0 569 570 #define HDP_BASE__INST6_SEG0 0 571 #define HDP_BASE__INST6_SEG1 0 572 #define HDP_BASE__INST6_SEG2 0 573 #define HDP_BASE__INST6_SEG3 0 574 #define HDP_BASE__INST6_SEG4 0 575 #define HDP_BASE__INST6_SEG5 0 576 577 #define HDP_BASE__INST7_SEG0 0 578 #define HDP_BASE__INST7_SEG1 0 579 #define HDP_BASE__INST7_SEG2 0 580 #define HDP_BASE__INST7_SEG3 0 581 #define HDP_BASE__INST7_SEG4 0 582 #define HDP_BASE__INST7_SEG5 0 583 584 #define MMHUB_BASE__INST0_SEG0 0x00012440 585 #define MMHUB_BASE__INST0_SEG1 0x0001A000 586 #define MMHUB_BASE__INST0_SEG2 0x00408800 587 #define MMHUB_BASE__INST0_SEG3 0 588 #define MMHUB_BASE__INST0_SEG4 0 589 #define MMHUB_BASE__INST0_SEG5 0 590 591 #define MMHUB_BASE__INST1_SEG0 0 592 #define MMHUB_BASE__INST1_SEG1 0 593 #define MMHUB_BASE__INST1_SEG2 0 594 #define MMHUB_BASE__INST1_SEG3 0 595 #define MMHUB_BASE__INST1_SEG4 0 596 #define MMHUB_BASE__INST1_SEG5 0 597 598 #define MMHUB_BASE__INST2_SEG0 0 599 #define MMHUB_BASE__INST2_SEG1 0 600 #define MMHUB_BASE__INST2_SEG2 0 601 #define MMHUB_BASE__INST2_SEG3 0 602 #define MMHUB_BASE__INST2_SEG4 0 603 #define MMHUB_BASE__INST2_SEG5 0 604 605 #define MMHUB_BASE__INST3_SEG0 0 606 #define MMHUB_BASE__INST3_SEG1 0 607 #define MMHUB_BASE__INST3_SEG2 0 608 #define MMHUB_BASE__INST3_SEG3 0 609 #define MMHUB_BASE__INST3_SEG4 0 610 #define MMHUB_BASE__INST3_SEG5 0 611 612 #define MMHUB_BASE__INST4_SEG0 0 613 #define MMHUB_BASE__INST4_SEG1 0 614 #define MMHUB_BASE__INST4_SEG2 0 615 #define MMHUB_BASE__INST4_SEG3 0 616 #define MMHUB_BASE__INST4_SEG4 0 617 #define MMHUB_BASE__INST4_SEG5 0 618 619 #define MMHUB_BASE__INST5_SEG0 0 620 #define MMHUB_BASE__INST5_SEG1 0 621 #define MMHUB_BASE__INST5_SEG2 0 622 #define MMHUB_BASE__INST5_SEG3 0 623 #define MMHUB_BASE__INST5_SEG4 0 624 #define MMHUB_BASE__INST5_SEG5 0 625 626 #define MMHUB_BASE__INST6_SEG0 0 627 #define MMHUB_BASE__INST6_SEG1 0 628 #define MMHUB_BASE__INST6_SEG2 0 629 #define MMHUB_BASE__INST6_SEG3 0 630 #define MMHUB_BASE__INST6_SEG4 0 631 #define MMHUB_BASE__INST6_SEG5 0 632 633 #define MMHUB_BASE__INST7_SEG0 0 634 #define MMHUB_BASE__INST7_SEG1 0 635 #define MMHUB_BASE__INST7_SEG2 0 636 #define MMHUB_BASE__INST7_SEG3 0 637 #define MMHUB_BASE__INST7_SEG4 0 638 #define MMHUB_BASE__INST7_SEG5 0 639 640 #define MP0_BASE__INST0_SEG0 0x00013FE0 641 #define MP0_BASE__INST0_SEG1 0x00016000 642 #define MP0_BASE__INST0_SEG2 0x0043FC00 643 #define MP0_BASE__INST0_SEG3 0x00DC0000 644 #define MP0_BASE__INST0_SEG4 0x00E00000 645 #define MP0_BASE__INST0_SEG5 0x00E40000 646 647 #define MP0_BASE__INST1_SEG0 0 648 #define MP0_BASE__INST1_SEG1 0 649 #define MP0_BASE__INST1_SEG2 0 650 #define MP0_BASE__INST1_SEG3 0 651 #define MP0_BASE__INST1_SEG4 0 652 #define MP0_BASE__INST1_SEG5 0 653 654 #define MP0_BASE__INST2_SEG0 0 655 #define MP0_BASE__INST2_SEG1 0 656 #define MP0_BASE__INST2_SEG2 0 657 #define MP0_BASE__INST2_SEG3 0 658 #define MP0_BASE__INST2_SEG4 0 659 #define MP0_BASE__INST2_SEG5 0 660 661 #define MP0_BASE__INST3_SEG0 0 662 #define MP0_BASE__INST3_SEG1 0 663 #define MP0_BASE__INST3_SEG2 0 664 #define MP0_BASE__INST3_SEG3 0 665 #define MP0_BASE__INST3_SEG4 0 666 #define MP0_BASE__INST3_SEG5 0 667 668 #define MP0_BASE__INST4_SEG0 0 669 #define MP0_BASE__INST4_SEG1 0 670 #define MP0_BASE__INST4_SEG2 0 671 #define MP0_BASE__INST4_SEG3 0 672 #define MP0_BASE__INST4_SEG4 0 673 #define MP0_BASE__INST4_SEG5 0 674 675 #define MP0_BASE__INST5_SEG0 0 676 #define MP0_BASE__INST5_SEG1 0 677 #define MP0_BASE__INST5_SEG2 0 678 #define MP0_BASE__INST5_SEG3 0 679 #define MP0_BASE__INST5_SEG4 0 680 #define MP0_BASE__INST5_SEG5 0 681 682 #define MP0_BASE__INST6_SEG0 0 683 #define MP0_BASE__INST6_SEG1 0 684 #define MP0_BASE__INST6_SEG2 0 685 #define MP0_BASE__INST6_SEG3 0 686 #define MP0_BASE__INST6_SEG4 0 687 #define MP0_BASE__INST6_SEG5 0 688 689 #define MP0_BASE__INST7_SEG0 0 690 #define MP0_BASE__INST7_SEG1 0 691 #define MP0_BASE__INST7_SEG2 0 692 #define MP0_BASE__INST7_SEG3 0 693 #define MP0_BASE__INST7_SEG4 0 694 #define MP0_BASE__INST7_SEG5 0 695 696 #define MP1_BASE__INST0_SEG0 0x00012020 697 #define MP1_BASE__INST0_SEG1 0x00016200 698 #define MP1_BASE__INST0_SEG2 0x00400400 699 #define MP1_BASE__INST0_SEG3 0x00E80000 700 #define MP1_BASE__INST0_SEG4 0x00EC0000 701 #define MP1_BASE__INST0_SEG5 0x00F00000 702 703 #define MP1_BASE__INST1_SEG0 0 704 #define MP1_BASE__INST1_SEG1 0 705 #define MP1_BASE__INST1_SEG2 0 706 #define MP1_BASE__INST1_SEG3 0 707 #define MP1_BASE__INST1_SEG4 0 708 #define MP1_BASE__INST1_SEG5 0 709 710 #define MP1_BASE__INST2_SEG0 0 711 #define MP1_BASE__INST2_SEG1 0 712 #define MP1_BASE__INST2_SEG2 0 713 #define MP1_BASE__INST2_SEG3 0 714 #define MP1_BASE__INST2_SEG4 0 715 #define MP1_BASE__INST2_SEG5 0 716 717 #define MP1_BASE__INST3_SEG0 0 718 #define MP1_BASE__INST3_SEG1 0 719 #define MP1_BASE__INST3_SEG2 0 720 #define MP1_BASE__INST3_SEG3 0 721 #define MP1_BASE__INST3_SEG4 0 722 #define MP1_BASE__INST3_SEG5 0 723 724 #define MP1_BASE__INST4_SEG0 0 725 #define MP1_BASE__INST4_SEG1 0 726 #define MP1_BASE__INST4_SEG2 0 727 #define MP1_BASE__INST4_SEG3 0 728 #define MP1_BASE__INST4_SEG4 0 729 #define MP1_BASE__INST4_SEG5 0 730 731 #define MP1_BASE__INST5_SEG0 0 732 #define MP1_BASE__INST5_SEG1 0 733 #define MP1_BASE__INST5_SEG2 0 734 #define MP1_BASE__INST5_SEG3 0 735 #define MP1_BASE__INST5_SEG4 0 736 #define MP1_BASE__INST5_SEG5 0 737 738 #define MP1_BASE__INST6_SEG0 0 739 #define MP1_BASE__INST6_SEG1 0 740 #define MP1_BASE__INST6_SEG2 0 741 #define MP1_BASE__INST6_SEG3 0 742 #define MP1_BASE__INST6_SEG4 0 743 #define MP1_BASE__INST6_SEG5 0 744 745 #define MP1_BASE__INST7_SEG0 0 746 #define MP1_BASE__INST7_SEG1 0 747 #define MP1_BASE__INST7_SEG2 0 748 #define MP1_BASE__INST7_SEG3 0 749 #define MP1_BASE__INST7_SEG4 0 750 #define MP1_BASE__INST7_SEG5 0 751 752 #define NBIF0_BASE__INST0_SEG0 0x00000000 753 #define NBIF0_BASE__INST0_SEG1 0x00000014 754 #define NBIF0_BASE__INST0_SEG2 0x00000D20 755 #define NBIF0_BASE__INST0_SEG3 0x00010400 756 #define NBIF0_BASE__INST0_SEG4 0x00012D80 757 #define NBIF0_BASE__INST0_SEG5 0x0041B000 758 759 #define NBIF0_BASE__INST1_SEG0 0 760 #define NBIF0_BASE__INST1_SEG1 0 761 #define NBIF0_BASE__INST1_SEG2 0 762 #define NBIF0_BASE__INST1_SEG3 0 763 #define NBIF0_BASE__INST1_SEG4 0 764 #define NBIF0_BASE__INST1_SEG5 0 765 766 #define NBIF0_BASE__INST2_SEG0 0 767 #define NBIF0_BASE__INST2_SEG1 0 768 #define NBIF0_BASE__INST2_SEG2 0 769 #define NBIF0_BASE__INST2_SEG3 0 770 #define NBIF0_BASE__INST2_SEG4 0 771 #define NBIF0_BASE__INST2_SEG5 0 772 773 #define NBIF0_BASE__INST3_SEG0 0 774 #define NBIF0_BASE__INST3_SEG1 0 775 #define NBIF0_BASE__INST3_SEG2 0 776 #define NBIF0_BASE__INST3_SEG3 0 777 #define NBIF0_BASE__INST3_SEG4 0 778 #define NBIF0_BASE__INST3_SEG5 0 779 780 #define NBIF0_BASE__INST4_SEG0 0 781 #define NBIF0_BASE__INST4_SEG1 0 782 #define NBIF0_BASE__INST4_SEG2 0 783 #define NBIF0_BASE__INST4_SEG3 0 784 #define NBIF0_BASE__INST4_SEG4 0 785 #define NBIF0_BASE__INST4_SEG5 0 786 787 #define NBIF0_BASE__INST5_SEG0 0 788 #define NBIF0_BASE__INST5_SEG1 0 789 #define NBIF0_BASE__INST5_SEG2 0 790 #define NBIF0_BASE__INST5_SEG3 0 791 #define NBIF0_BASE__INST5_SEG4 0 792 #define NBIF0_BASE__INST5_SEG5 0 793 794 #define NBIF0_BASE__INST6_SEG0 0 795 #define NBIF0_BASE__INST6_SEG1 0 796 #define NBIF0_BASE__INST6_SEG2 0 797 #define NBIF0_BASE__INST6_SEG3 0 798 #define NBIF0_BASE__INST6_SEG4 0 799 #define NBIF0_BASE__INST6_SEG5 0 800 801 #define NBIF0_BASE__INST7_SEG0 0 802 #define NBIF0_BASE__INST7_SEG1 0 803 #define NBIF0_BASE__INST7_SEG2 0 804 #define NBIF0_BASE__INST7_SEG3 0 805 #define NBIF0_BASE__INST7_SEG4 0 806 #define NBIF0_BASE__INST7_SEG5 0 807 808 #define OSSSYS_BASE__INST0_SEG0 0x000010A0 809 #define OSSSYS_BASE__INST0_SEG1 0x00012500 810 #define OSSSYS_BASE__INST0_SEG2 0x0040A000 811 #define OSSSYS_BASE__INST0_SEG3 0 812 #define OSSSYS_BASE__INST0_SEG4 0 813 #define OSSSYS_BASE__INST0_SEG5 0 814 815 #define OSSSYS_BASE__INST1_SEG0 0 816 #define OSSSYS_BASE__INST1_SEG1 0 817 #define OSSSYS_BASE__INST1_SEG2 0 818 #define OSSSYS_BASE__INST1_SEG3 0 819 #define OSSSYS_BASE__INST1_SEG4 0 820 #define OSSSYS_BASE__INST1_SEG5 0 821 822 #define OSSSYS_BASE__INST2_SEG0 0 823 #define OSSSYS_BASE__INST2_SEG1 0 824 #define OSSSYS_BASE__INST2_SEG2 0 825 #define OSSSYS_BASE__INST2_SEG3 0 826 #define OSSSYS_BASE__INST2_SEG4 0 827 #define OSSSYS_BASE__INST2_SEG5 0 828 829 #define OSSSYS_BASE__INST3_SEG0 0 830 #define OSSSYS_BASE__INST3_SEG1 0 831 #define OSSSYS_BASE__INST3_SEG2 0 832 #define OSSSYS_BASE__INST3_SEG3 0 833 #define OSSSYS_BASE__INST3_SEG4 0 834 #define OSSSYS_BASE__INST3_SEG5 0 835 836 #define OSSSYS_BASE__INST4_SEG0 0 837 #define OSSSYS_BASE__INST4_SEG1 0 838 #define OSSSYS_BASE__INST4_SEG2 0 839 #define OSSSYS_BASE__INST4_SEG3 0 840 #define OSSSYS_BASE__INST4_SEG4 0 841 #define OSSSYS_BASE__INST4_SEG5 0 842 843 #define OSSSYS_BASE__INST5_SEG0 0 844 #define OSSSYS_BASE__INST5_SEG1 0 845 #define OSSSYS_BASE__INST5_SEG2 0 846 #define OSSSYS_BASE__INST5_SEG3 0 847 #define OSSSYS_BASE__INST5_SEG4 0 848 #define OSSSYS_BASE__INST5_SEG5 0 849 850 #define OSSSYS_BASE__INST6_SEG0 0 851 #define OSSSYS_BASE__INST6_SEG1 0 852 #define OSSSYS_BASE__INST6_SEG2 0 853 #define OSSSYS_BASE__INST6_SEG3 0 854 #define OSSSYS_BASE__INST6_SEG4 0 855 #define OSSSYS_BASE__INST6_SEG5 0 856 857 #define OSSSYS_BASE__INST7_SEG0 0 858 #define OSSSYS_BASE__INST7_SEG1 0 859 #define OSSSYS_BASE__INST7_SEG2 0 860 #define OSSSYS_BASE__INST7_SEG3 0 861 #define OSSSYS_BASE__INST7_SEG4 0 862 #define OSSSYS_BASE__INST7_SEG5 0 863 864 #define PCIE0_BASE__INST0_SEG0 0x000128C0 865 #define PCIE0_BASE__INST0_SEG1 0x00411800 866 #define PCIE0_BASE__INST0_SEG2 0x04440000 867 #define PCIE0_BASE__INST0_SEG3 0 868 #define PCIE0_BASE__INST0_SEG4 0 869 #define PCIE0_BASE__INST0_SEG5 0 870 871 #define PCIE0_BASE__INST1_SEG0 0 872 #define PCIE0_BASE__INST1_SEG1 0 873 #define PCIE0_BASE__INST1_SEG2 0 874 #define PCIE0_BASE__INST1_SEG3 0 875 #define PCIE0_BASE__INST1_SEG4 0 876 #define PCIE0_BASE__INST1_SEG5 0 877 878 #define PCIE0_BASE__INST2_SEG0 0 879 #define PCIE0_BASE__INST2_SEG1 0 880 #define PCIE0_BASE__INST2_SEG2 0 881 #define PCIE0_BASE__INST2_SEG3 0 882 #define PCIE0_BASE__INST2_SEG4 0 883 #define PCIE0_BASE__INST2_SEG5 0 884 885 #define PCIE0_BASE__INST3_SEG0 0 886 #define PCIE0_BASE__INST3_SEG1 0 887 #define PCIE0_BASE__INST3_SEG2 0 888 #define PCIE0_BASE__INST3_SEG3 0 889 #define PCIE0_BASE__INST3_SEG4 0 890 #define PCIE0_BASE__INST3_SEG5 0 891 892 #define PCIE0_BASE__INST4_SEG0 0 893 #define PCIE0_BASE__INST4_SEG1 0 894 #define PCIE0_BASE__INST4_SEG2 0 895 #define PCIE0_BASE__INST4_SEG3 0 896 #define PCIE0_BASE__INST4_SEG4 0 897 #define PCIE0_BASE__INST4_SEG5 0 898 899 #define PCIE0_BASE__INST5_SEG0 0 900 #define PCIE0_BASE__INST5_SEG1 0 901 #define PCIE0_BASE__INST5_SEG2 0 902 #define PCIE0_BASE__INST5_SEG3 0 903 #define PCIE0_BASE__INST5_SEG4 0 904 #define PCIE0_BASE__INST5_SEG5 0 905 906 #define PCIE0_BASE__INST6_SEG0 0 907 #define PCIE0_BASE__INST6_SEG1 0 908 #define PCIE0_BASE__INST6_SEG2 0 909 #define PCIE0_BASE__INST6_SEG3 0 910 #define PCIE0_BASE__INST6_SEG4 0 911 #define PCIE0_BASE__INST6_SEG5 0 912 913 #define PCIE0_BASE__INST7_SEG0 0 914 #define PCIE0_BASE__INST7_SEG1 0 915 #define PCIE0_BASE__INST7_SEG2 0 916 #define PCIE0_BASE__INST7_SEG3 0 917 #define PCIE0_BASE__INST7_SEG4 0 918 #define PCIE0_BASE__INST7_SEG5 0 919 920 #define SDMA0_BASE__INST0_SEG0 0x00001260 921 #define SDMA0_BASE__INST0_SEG1 0x00012540 922 #define SDMA0_BASE__INST0_SEG2 0x0040A800 923 #define SDMA0_BASE__INST0_SEG3 0 924 #define SDMA0_BASE__INST0_SEG4 0 925 #define SDMA0_BASE__INST0_SEG5 0 926 927 #define SDMA0_BASE__INST1_SEG0 0 928 #define SDMA0_BASE__INST1_SEG1 0 929 #define SDMA0_BASE__INST1_SEG2 0 930 #define SDMA0_BASE__INST1_SEG3 0 931 #define SDMA0_BASE__INST1_SEG4 0 932 #define SDMA0_BASE__INST1_SEG5 0 933 934 #define SDMA0_BASE__INST2_SEG0 0 935 #define SDMA0_BASE__INST2_SEG1 0 936 #define SDMA0_BASE__INST2_SEG2 0 937 #define SDMA0_BASE__INST2_SEG3 0 938 #define SDMA0_BASE__INST2_SEG4 0 939 #define SDMA0_BASE__INST2_SEG5 0 940 941 #define SDMA0_BASE__INST3_SEG0 0 942 #define SDMA0_BASE__INST3_SEG1 0 943 #define SDMA0_BASE__INST3_SEG2 0 944 #define SDMA0_BASE__INST3_SEG3 0 945 #define SDMA0_BASE__INST3_SEG4 0 946 #define SDMA0_BASE__INST3_SEG5 0 947 948 #define SDMA0_BASE__INST4_SEG0 0 949 #define SDMA0_BASE__INST4_SEG1 0 950 #define SDMA0_BASE__INST4_SEG2 0 951 #define SDMA0_BASE__INST4_SEG3 0 952 #define SDMA0_BASE__INST4_SEG4 0 953 #define SDMA0_BASE__INST4_SEG5 0 954 955 #define SDMA0_BASE__INST5_SEG0 0 956 #define SDMA0_BASE__INST5_SEG1 0 957 #define SDMA0_BASE__INST5_SEG2 0 958 #define SDMA0_BASE__INST5_SEG3 0 959 #define SDMA0_BASE__INST5_SEG4 0 960 #define SDMA0_BASE__INST5_SEG5 0 961 962 #define SDMA0_BASE__INST6_SEG0 0 963 #define SDMA0_BASE__INST6_SEG1 0 964 #define SDMA0_BASE__INST6_SEG2 0 965 #define SDMA0_BASE__INST6_SEG3 0 966 #define SDMA0_BASE__INST6_SEG4 0 967 #define SDMA0_BASE__INST6_SEG5 0 968 969 #define SDMA1_BASE__INST0_SEG0 0x00001860 970 #define SDMA1_BASE__INST0_SEG1 0x00012560 971 #define SDMA1_BASE__INST0_SEG2 0x0040AC00 972 #define SDMA1_BASE__INST0_SEG3 0 973 #define SDMA1_BASE__INST0_SEG4 0 974 #define SDMA1_BASE__INST0_SEG5 0 975 976 #define SDMA1_BASE__INST1_SEG0 0 977 #define SDMA1_BASE__INST1_SEG1 0 978 #define SDMA1_BASE__INST1_SEG2 0 979 #define SDMA1_BASE__INST1_SEG3 0 980 #define SDMA1_BASE__INST1_SEG4 0 981 #define SDMA1_BASE__INST1_SEG5 0 982 983 #define SDMA1_BASE__INST2_SEG0 0 984 #define SDMA1_BASE__INST2_SEG1 0 985 #define SDMA1_BASE__INST2_SEG2 0 986 #define SDMA1_BASE__INST2_SEG3 0 987 #define SDMA1_BASE__INST2_SEG4 0 988 #define SDMA1_BASE__INST2_SEG5 0 989 990 #define SDMA1_BASE__INST3_SEG0 0 991 #define SDMA1_BASE__INST3_SEG1 0 992 #define SDMA1_BASE__INST3_SEG2 0 993 #define SDMA1_BASE__INST3_SEG3 0 994 #define SDMA1_BASE__INST3_SEG4 0 995 #define SDMA1_BASE__INST3_SEG5 0 996 997 #define SDMA1_BASE__INST4_SEG0 0 998 #define SDMA1_BASE__INST4_SEG1 0 999 #define SDMA1_BASE__INST4_SEG2 0 1000 #define SDMA1_BASE__INST4_SEG3 0 1001 #define SDMA1_BASE__INST4_SEG4 0 1002 #define SDMA1_BASE__INST4_SEG5 0 1003 1004 #define SDMA1_BASE__INST5_SEG0 0 1005 #define SDMA1_BASE__INST5_SEG1 0 1006 #define SDMA1_BASE__INST5_SEG2 0 1007 #define SDMA1_BASE__INST5_SEG3 0 1008 #define SDMA1_BASE__INST5_SEG4 0 1009 #define SDMA1_BASE__INST5_SEG5 0 1010 1011 1012 #define SDMA1_BASE__INST6_SEG0 0 1013 #define SDMA1_BASE__INST6_SEG1 0 1014 #define SDMA1_BASE__INST6_SEG2 0 1015 #define SDMA1_BASE__INST6_SEG3 0 1016 #define SDMA1_BASE__INST6_SEG4 0 1017 #define SDMA1_BASE__INST6_SEG5 0 1018 1019 1020 #define SDMA2_BASE__INST0_SEG0 0x00013760 1021 #define SDMA2_BASE__INST0_SEG1 0x0001E000 1022 #define SDMA2_BASE__INST0_SEG2 0x0042EC00 1023 #define SDMA2_BASE__INST0_SEG3 0 1024 #define SDMA2_BASE__INST0_SEG4 0 1025 #define SDMA2_BASE__INST0_SEG5 0 1026 1027 1028 #define SDMA2_BASE__INST1_SEG0 0 1029 #define SDMA2_BASE__INST1_SEG1 0 1030 #define SDMA2_BASE__INST1_SEG2 0 1031 #define SDMA2_BASE__INST1_SEG3 0 1032 #define SDMA2_BASE__INST1_SEG4 0 1033 #define SDMA2_BASE__INST1_SEG5 0 1034 1035 #define SDMA2_BASE__INST2_SEG0 0 1036 #define SDMA2_BASE__INST2_SEG1 0 1037 #define SDMA2_BASE__INST2_SEG2 0 1038 #define SDMA2_BASE__INST2_SEG3 0 1039 #define SDMA2_BASE__INST2_SEG4 0 1040 #define SDMA2_BASE__INST2_SEG5 0 1041 1042 #define SDMA2_BASE__INST3_SEG0 0 1043 #define SDMA2_BASE__INST3_SEG1 0 1044 #define SDMA2_BASE__INST3_SEG2 0 1045 #define SDMA2_BASE__INST3_SEG3 0 1046 #define SDMA2_BASE__INST3_SEG4 0 1047 #define SDMA2_BASE__INST3_SEG5 0 1048 1049 #define SDMA2_BASE__INST4_SEG0 0 1050 #define SDMA2_BASE__INST4_SEG1 0 1051 #define SDMA2_BASE__INST4_SEG2 0 1052 #define SDMA2_BASE__INST4_SEG3 0 1053 #define SDMA2_BASE__INST4_SEG4 0 1054 #define SDMA2_BASE__INST4_SEG5 0 1055 1056 #define SDMA2_BASE__INST5_SEG0 0 1057 #define SDMA2_BASE__INST5_SEG1 0 1058 #define SDMA2_BASE__INST5_SEG2 0 1059 #define SDMA2_BASE__INST5_SEG3 0 1060 #define SDMA2_BASE__INST5_SEG4 0 1061 #define SDMA2_BASE__INST5_SEG5 0 1062 1063 #define SDMA2_BASE__INST6_SEG0 0 1064 #define SDMA2_BASE__INST6_SEG1 0 1065 #define SDMA2_BASE__INST6_SEG2 0 1066 #define SDMA2_BASE__INST6_SEG3 0 1067 #define SDMA2_BASE__INST6_SEG4 0 1068 #define SDMA2_BASE__INST6_SEG5 0 1069 1070 #define SDMA3_BASE__INST0_SEG0 0x00013780 1071 #define SDMA3_BASE__INST0_SEG1 0x0001E400 1072 #define SDMA3_BASE__INST0_SEG2 0x0042F000 1073 #define SDMA3_BASE__INST0_SEG3 0 1074 #define SDMA3_BASE__INST0_SEG4 0 1075 #define SDMA3_BASE__INST0_SEG5 0 1076 1077 #define SDMA3_BASE__INST1_SEG0 0 1078 #define SDMA3_BASE__INST1_SEG1 0 1079 #define SDMA3_BASE__INST1_SEG2 0 1080 #define SDMA3_BASE__INST1_SEG3 0 1081 #define SDMA3_BASE__INST1_SEG4 0 1082 #define SDMA3_BASE__INST1_SEG5 0 1083 1084 #define SDMA3_BASE__INST2_SEG0 0 1085 #define SDMA3_BASE__INST2_SEG1 0 1086 #define SDMA3_BASE__INST2_SEG2 0 1087 #define SDMA3_BASE__INST2_SEG3 0 1088 #define SDMA3_BASE__INST2_SEG4 0 1089 #define SDMA3_BASE__INST2_SEG5 0 1090 1091 #define SDMA3_BASE__INST3_SEG0 0 1092 #define SDMA3_BASE__INST3_SEG1 0 1093 #define SDMA3_BASE__INST3_SEG2 0 1094 #define SDMA3_BASE__INST3_SEG3 0 1095 #define SDMA3_BASE__INST3_SEG4 0 1096 #define SDMA3_BASE__INST3_SEG5 0 1097 1098 #define SDMA3_BASE__INST4_SEG0 0 1099 #define SDMA3_BASE__INST4_SEG1 0 1100 #define SDMA3_BASE__INST4_SEG2 0 1101 #define SDMA3_BASE__INST4_SEG3 0 1102 #define SDMA3_BASE__INST4_SEG4 0 1103 #define SDMA3_BASE__INST4_SEG5 0 1104 1105 #define SDMA3_BASE__INST5_SEG0 0 1106 #define SDMA3_BASE__INST5_SEG1 0 1107 #define SDMA3_BASE__INST5_SEG2 0 1108 #define SDMA3_BASE__INST5_SEG3 0 1109 #define SDMA3_BASE__INST5_SEG4 0 1110 #define SDMA3_BASE__INST5_SEG5 0 1111 1112 #define SDMA3_BASE__INST6_SEG0 0 1113 #define SDMA3_BASE__INST6_SEG1 0 1114 #define SDMA3_BASE__INST6_SEG2 0 1115 #define SDMA3_BASE__INST6_SEG3 0 1116 #define SDMA3_BASE__INST6_SEG4 0 1117 #define SDMA3_BASE__INST6_SEG5 0 1118 1119 #define SDMA4_BASE__INST0_SEG0 0x000137A0 1120 #define SDMA4_BASE__INST0_SEG1 0x0001E800 1121 #define SDMA4_BASE__INST0_SEG2 0x0042F400 1122 #define SDMA4_BASE__INST0_SEG3 0 1123 #define SDMA4_BASE__INST0_SEG4 0 1124 #define SDMA4_BASE__INST0_SEG5 0 1125 1126 #define SDMA4_BASE__INST1_SEG0 0 1127 #define SDMA4_BASE__INST1_SEG1 0 1128 #define SDMA4_BASE__INST1_SEG2 0 1129 #define SDMA4_BASE__INST1_SEG3 0 1130 #define SDMA4_BASE__INST1_SEG4 0 1131 #define SDMA4_BASE__INST1_SEG5 0 1132 1133 #define SDMA4_BASE__INST2_SEG0 0 1134 #define SDMA4_BASE__INST2_SEG1 0 1135 #define SDMA4_BASE__INST2_SEG2 0 1136 #define SDMA4_BASE__INST2_SEG3 0 1137 #define SDMA4_BASE__INST2_SEG4 0 1138 #define SDMA4_BASE__INST2_SEG5 0 1139 1140 #define SDMA4_BASE__INST3_SEG0 0 1141 #define SDMA4_BASE__INST3_SEG1 0 1142 #define SDMA4_BASE__INST3_SEG2 0 1143 #define SDMA4_BASE__INST3_SEG3 0 1144 #define SDMA4_BASE__INST3_SEG4 0 1145 #define SDMA4_BASE__INST3_SEG5 0 1146 1147 #define SDMA4_BASE__INST4_SEG0 0 1148 #define SDMA4_BASE__INST4_SEG1 0 1149 #define SDMA4_BASE__INST4_SEG2 0 1150 #define SDMA4_BASE__INST4_SEG3 0 1151 #define SDMA4_BASE__INST4_SEG4 0 1152 #define SDMA4_BASE__INST4_SEG5 0 1153 1154 #define SDMA4_BASE__INST5_SEG0 0 1155 #define SDMA4_BASE__INST5_SEG1 0 1156 #define SDMA4_BASE__INST5_SEG2 0 1157 #define SDMA4_BASE__INST5_SEG3 0 1158 #define SDMA4_BASE__INST5_SEG4 0 1159 #define SDMA4_BASE__INST5_SEG5 0 1160 1161 #define SDMA4_BASE__INST6_SEG0 0 1162 #define SDMA4_BASE__INST6_SEG1 0 1163 #define SDMA4_BASE__INST6_SEG2 0 1164 #define SDMA4_BASE__INST6_SEG3 0 1165 #define SDMA4_BASE__INST6_SEG4 0 1166 #define SDMA4_BASE__INST6_SEG5 0 1167 1168 #define SDMA5_BASE__INST0_SEG0 0x000137C0 1169 #define SDMA5_BASE__INST0_SEG1 0x0001EC00 1170 #define SDMA5_BASE__INST0_SEG2 0x0042F800 1171 #define SDMA5_BASE__INST0_SEG3 0 1172 #define SDMA5_BASE__INST0_SEG4 0 1173 #define SDMA5_BASE__INST0_SEG5 0 1174 1175 #define SDMA5_BASE__INST1_SEG0 0 1176 #define SDMA5_BASE__INST1_SEG1 0 1177 #define SDMA5_BASE__INST1_SEG2 0 1178 #define SDMA5_BASE__INST1_SEG3 0 1179 #define SDMA5_BASE__INST1_SEG4 0 1180 #define SDMA5_BASE__INST1_SEG5 0 1181 1182 #define SDMA5_BASE__INST2_SEG0 0 1183 #define SDMA5_BASE__INST2_SEG1 0 1184 #define SDMA5_BASE__INST2_SEG2 0 1185 #define SDMA5_BASE__INST2_SEG3 0 1186 #define SDMA5_BASE__INST2_SEG4 0 1187 #define SDMA5_BASE__INST2_SEG5 0 1188 1189 #define SDMA5_BASE__INST3_SEG0 0 1190 #define SDMA5_BASE__INST3_SEG1 0 1191 #define SDMA5_BASE__INST3_SEG2 0 1192 #define SDMA5_BASE__INST3_SEG3 0 1193 #define SDMA5_BASE__INST3_SEG4 0 1194 #define SDMA5_BASE__INST3_SEG5 0 1195 1196 #define SDMA5_BASE__INST4_SEG0 0 1197 #define SDMA5_BASE__INST4_SEG1 0 1198 #define SDMA5_BASE__INST4_SEG2 0 1199 #define SDMA5_BASE__INST4_SEG3 0 1200 #define SDMA5_BASE__INST4_SEG4 0 1201 #define SDMA5_BASE__INST4_SEG5 0 1202 1203 #define SDMA5_BASE__INST5_SEG0 0 1204 #define SDMA5_BASE__INST5_SEG1 0 1205 #define SDMA5_BASE__INST5_SEG2 0 1206 #define SDMA5_BASE__INST5_SEG3 0 1207 #define SDMA5_BASE__INST5_SEG4 0 1208 #define SDMA5_BASE__INST5_SEG5 0 1209 1210 #define SDMA5_BASE__INST6_SEG0 0 1211 #define SDMA5_BASE__INST6_SEG1 0 1212 #define SDMA5_BASE__INST6_SEG2 0 1213 #define SDMA5_BASE__INST6_SEG3 0 1214 #define SDMA5_BASE__INST6_SEG4 0 1215 #define SDMA5_BASE__INST6_SEG5 0 1216 1217 #define SDMA6_BASE__INST0_SEG0 0x000137E0 1218 #define SDMA6_BASE__INST0_SEG1 0x0001F000 1219 #define SDMA6_BASE__INST0_SEG2 0x0042FC00 1220 #define SDMA6_BASE__INST0_SEG3 0 1221 #define SDMA6_BASE__INST0_SEG4 0 1222 #define SDMA6_BASE__INST0_SEG5 0 1223 1224 #define SDMA6_BASE__INST1_SEG0 0 1225 #define SDMA6_BASE__INST1_SEG1 0 1226 #define SDMA6_BASE__INST1_SEG2 0 1227 #define SDMA6_BASE__INST1_SEG3 0 1228 #define SDMA6_BASE__INST1_SEG4 0 1229 #define SDMA6_BASE__INST1_SEG5 0 1230 1231 #define SDMA6_BASE__INST2_SEG0 0 1232 #define SDMA6_BASE__INST2_SEG1 0 1233 #define SDMA6_BASE__INST2_SEG2 0 1234 #define SDMA6_BASE__INST2_SEG3 0 1235 #define SDMA6_BASE__INST2_SEG4 0 1236 #define SDMA6_BASE__INST2_SEG5 0 1237 1238 #define SDMA6_BASE__INST3_SEG0 0 1239 #define SDMA6_BASE__INST3_SEG1 0 1240 #define SDMA6_BASE__INST3_SEG2 0 1241 #define SDMA6_BASE__INST3_SEG3 0 1242 #define SDMA6_BASE__INST3_SEG4 0 1243 #define SDMA6_BASE__INST3_SEG5 0 1244 1245 #define SDMA6_BASE__INST4_SEG0 0 1246 #define SDMA6_BASE__INST4_SEG1 0 1247 #define SDMA6_BASE__INST4_SEG2 0 1248 #define SDMA6_BASE__INST4_SEG3 0 1249 #define SDMA6_BASE__INST4_SEG4 0 1250 #define SDMA6_BASE__INST4_SEG5 0 1251 1252 #define SDMA6_BASE__INST5_SEG0 0 1253 #define SDMA6_BASE__INST5_SEG1 0 1254 #define SDMA6_BASE__INST5_SEG2 0 1255 #define SDMA6_BASE__INST5_SEG3 0 1256 #define SDMA6_BASE__INST5_SEG4 0 1257 #define SDMA6_BASE__INST5_SEG5 0 1258 1259 #define SDMA6_BASE__INST6_SEG0 0 1260 #define SDMA6_BASE__INST6_SEG1 0 1261 #define SDMA6_BASE__INST6_SEG2 0 1262 #define SDMA6_BASE__INST6_SEG3 0 1263 #define SDMA6_BASE__INST6_SEG4 0 1264 #define SDMA6_BASE__INST6_SEG5 0 1265 1266 #define SDMA7_BASE__INST0_SEG0 0x00013800 1267 #define SDMA7_BASE__INST0_SEG1 0x0001F400 1268 #define SDMA7_BASE__INST0_SEG2 0x00430000 1269 #define SDMA7_BASE__INST0_SEG3 0 1270 #define SDMA7_BASE__INST0_SEG4 0 1271 #define SDMA7_BASE__INST0_SEG5 0 1272 1273 #define SDMA7_BASE__INST1_SEG0 0 1274 #define SDMA7_BASE__INST1_SEG1 0 1275 #define SDMA7_BASE__INST1_SEG2 0 1276 #define SDMA7_BASE__INST1_SEG3 0 1277 #define SDMA7_BASE__INST1_SEG4 0 1278 #define SDMA7_BASE__INST1_SEG5 0 1279 1280 #define SDMA7_BASE__INST2_SEG0 0 1281 #define SDMA7_BASE__INST2_SEG1 0 1282 #define SDMA7_BASE__INST2_SEG2 0 1283 #define SDMA7_BASE__INST2_SEG3 0 1284 #define SDMA7_BASE__INST2_SEG4 0 1285 #define SDMA7_BASE__INST2_SEG5 0 1286 1287 #define SDMA7_BASE__INST3_SEG0 0 1288 #define SDMA7_BASE__INST3_SEG1 0 1289 #define SDMA7_BASE__INST3_SEG2 0 1290 #define SDMA7_BASE__INST3_SEG3 0 1291 #define SDMA7_BASE__INST3_SEG4 0 1292 #define SDMA7_BASE__INST3_SEG5 0 1293 1294 #define SDMA7_BASE__INST4_SEG0 0 1295 #define SDMA7_BASE__INST4_SEG1 0 1296 #define SDMA7_BASE__INST4_SEG2 0 1297 #define SDMA7_BASE__INST4_SEG3 0 1298 #define SDMA7_BASE__INST4_SEG4 0 1299 #define SDMA7_BASE__INST4_SEG5 0 1300 1301 #define SDMA7_BASE__INST5_SEG0 0 1302 #define SDMA7_BASE__INST5_SEG1 0 1303 #define SDMA7_BASE__INST5_SEG2 0 1304 #define SDMA7_BASE__INST5_SEG3 0 1305 #define SDMA7_BASE__INST5_SEG4 0 1306 #define SDMA7_BASE__INST5_SEG5 0 1307 1308 #define SDMA7_BASE__INST6_SEG0 0 1309 #define SDMA7_BASE__INST6_SEG1 0 1310 #define SDMA7_BASE__INST6_SEG2 0 1311 #define SDMA7_BASE__INST6_SEG3 0 1312 #define SDMA7_BASE__INST6_SEG4 0 1313 #define SDMA7_BASE__INST6_SEG5 0 1314 1315 #define SMUIO_BASE__INST0_SEG0 0x00012080 1316 #define SMUIO_BASE__INST0_SEG1 0x00016800 1317 #define SMUIO_BASE__INST0_SEG2 0x00016A00 1318 #define SMUIO_BASE__INST0_SEG3 0x00401000 1319 #define SMUIO_BASE__INST0_SEG4 0x00440000 1320 #define SMUIO_BASE__INST0_SEG5 0 1321 1322 #define SMUIO_BASE__INST1_SEG0 0 1323 #define SMUIO_BASE__INST1_SEG1 0 1324 #define SMUIO_BASE__INST1_SEG2 0 1325 #define SMUIO_BASE__INST1_SEG3 0 1326 #define SMUIO_BASE__INST1_SEG4 0 1327 #define SMUIO_BASE__INST1_SEG5 0 1328 1329 #define SMUIO_BASE__INST2_SEG0 0 1330 #define SMUIO_BASE__INST2_SEG1 0 1331 #define SMUIO_BASE__INST2_SEG2 0 1332 #define SMUIO_BASE__INST2_SEG3 0 1333 #define SMUIO_BASE__INST2_SEG4 0 1334 #define SMUIO_BASE__INST2_SEG5 0 1335 1336 #define SMUIO_BASE__INST3_SEG0 0 1337 #define SMUIO_BASE__INST3_SEG1 0 1338 #define SMUIO_BASE__INST3_SEG2 0 1339 #define SMUIO_BASE__INST3_SEG3 0 1340 #define SMUIO_BASE__INST3_SEG4 0 1341 #define SMUIO_BASE__INST3_SEG5 0 1342 1343 #define SMUIO_BASE__INST4_SEG0 0 1344 #define SMUIO_BASE__INST4_SEG1 0 1345 #define SMUIO_BASE__INST4_SEG2 0 1346 #define SMUIO_BASE__INST4_SEG3 0 1347 #define SMUIO_BASE__INST4_SEG4 0 1348 #define SMUIO_BASE__INST4_SEG5 0 1349 1350 #define SMUIO_BASE__INST5_SEG0 0 1351 #define SMUIO_BASE__INST5_SEG1 0 1352 #define SMUIO_BASE__INST5_SEG2 0 1353 #define SMUIO_BASE__INST5_SEG3 0 1354 #define SMUIO_BASE__INST5_SEG4 0 1355 #define SMUIO_BASE__INST5_SEG5 0 1356 1357 #define SMUIO_BASE__INST6_SEG0 0 1358 #define SMUIO_BASE__INST6_SEG1 0 1359 #define SMUIO_BASE__INST6_SEG2 0 1360 #define SMUIO_BASE__INST6_SEG3 0 1361 #define SMUIO_BASE__INST6_SEG4 0 1362 #define SMUIO_BASE__INST6_SEG5 0 1363 1364 #define SMUIO_BASE__INST7_SEG0 0 1365 #define SMUIO_BASE__INST7_SEG1 0 1366 #define SMUIO_BASE__INST7_SEG2 0 1367 #define SMUIO_BASE__INST7_SEG3 0 1368 #define SMUIO_BASE__INST7_SEG4 0 1369 #define SMUIO_BASE__INST7_SEG5 0 1370 1371 #define THM_BASE__INST0_SEG0 0x00012060 1372 #define THM_BASE__INST0_SEG1 0x00016600 1373 #define THM_BASE__INST0_SEG2 0x00400C00 1374 #define THM_BASE__INST0_SEG3 0 1375 #define THM_BASE__INST0_SEG4 0 1376 #define THM_BASE__INST0_SEG5 0 1377 1378 #define THM_BASE__INST1_SEG0 0 1379 #define THM_BASE__INST1_SEG1 0 1380 #define THM_BASE__INST1_SEG2 0 1381 #define THM_BASE__INST1_SEG3 0 1382 #define THM_BASE__INST1_SEG4 0 1383 #define THM_BASE__INST1_SEG5 0 1384 1385 #define THM_BASE__INST2_SEG0 0 1386 #define THM_BASE__INST2_SEG1 0 1387 #define THM_BASE__INST2_SEG2 0 1388 #define THM_BASE__INST2_SEG3 0 1389 #define THM_BASE__INST2_SEG4 0 1390 #define THM_BASE__INST2_SEG5 0 1391 1392 #define THM_BASE__INST3_SEG0 0 1393 #define THM_BASE__INST3_SEG1 0 1394 #define THM_BASE__INST3_SEG2 0 1395 #define THM_BASE__INST3_SEG3 0 1396 #define THM_BASE__INST3_SEG4 0 1397 #define THM_BASE__INST3_SEG5 0 1398 1399 #define THM_BASE__INST4_SEG0 0 1400 #define THM_BASE__INST4_SEG1 0 1401 #define THM_BASE__INST4_SEG2 0 1402 #define THM_BASE__INST4_SEG3 0 1403 #define THM_BASE__INST4_SEG4 0 1404 #define THM_BASE__INST4_SEG5 0 1405 1406 #define THM_BASE__INST5_SEG0 0 1407 #define THM_BASE__INST5_SEG1 0 1408 #define THM_BASE__INST5_SEG2 0 1409 #define THM_BASE__INST5_SEG3 0 1410 #define THM_BASE__INST5_SEG4 0 1411 #define THM_BASE__INST5_SEG5 0 1412 1413 #define THM_BASE__INST6_SEG0 0 1414 #define THM_BASE__INST6_SEG1 0 1415 #define THM_BASE__INST6_SEG2 0 1416 #define THM_BASE__INST6_SEG3 0 1417 #define THM_BASE__INST6_SEG4 0 1418 #define THM_BASE__INST6_SEG5 0 1419 1420 #define THM_BASE__INST7_SEG0 0 1421 #define THM_BASE__INST7_SEG1 0 1422 #define THM_BASE__INST7_SEG2 0 1423 #define THM_BASE__INST7_SEG3 0 1424 #define THM_BASE__INST7_SEG4 0 1425 #define THM_BASE__INST7_SEG5 0 1426 1427 #define UMC_BASE__INST0_SEG0 0x000132C0 1428 #define UMC_BASE__INST0_SEG1 0x00014000 1429 #define UMC_BASE__INST0_SEG2 0x00425800 1430 #define UMC_BASE__INST0_SEG3 0 1431 #define UMC_BASE__INST0_SEG4 0 1432 #define UMC_BASE__INST0_SEG5 0 1433 1434 #define UMC_BASE__INST1_SEG0 0x000132E0 1435 #define UMC_BASE__INST1_SEG1 0x00054000 1436 #define UMC_BASE__INST1_SEG2 0x00425C00 1437 #define UMC_BASE__INST1_SEG3 0 1438 #define UMC_BASE__INST1_SEG4 0 1439 #define UMC_BASE__INST1_SEG5 0 1440 1441 #define UMC_BASE__INST2_SEG0 0x00013300 1442 #define UMC_BASE__INST2_SEG1 0x00094000 1443 #define UMC_BASE__INST2_SEG2 0x00426000 1444 #define UMC_BASE__INST2_SEG3 0 1445 #define UMC_BASE__INST2_SEG4 0 1446 #define UMC_BASE__INST2_SEG5 0 1447 1448 #define UMC_BASE__INST3_SEG0 0x00013320 1449 #define UMC_BASE__INST3_SEG1 0x000D4000 1450 #define UMC_BASE__INST3_SEG2 0x00426400 1451 #define UMC_BASE__INST3_SEG3 0 1452 #define UMC_BASE__INST3_SEG4 0 1453 #define UMC_BASE__INST3_SEG5 0 1454 1455 #define UMC_BASE__INST4_SEG0 0x00013340 1456 #define UMC_BASE__INST4_SEG1 0x00114000 1457 #define UMC_BASE__INST4_SEG2 0x00426800 1458 #define UMC_BASE__INST4_SEG3 0 1459 #define UMC_BASE__INST4_SEG4 0 1460 #define UMC_BASE__INST4_SEG5 0 1461 1462 #define UMC_BASE__INST5_SEG0 0x00013360 1463 #define UMC_BASE__INST5_SEG1 0x00154000 1464 #define UMC_BASE__INST5_SEG2 0x00426C00 1465 #define UMC_BASE__INST5_SEG3 0 1466 #define UMC_BASE__INST5_SEG4 0 1467 #define UMC_BASE__INST5_SEG5 0 1468 1469 #define UMC_BASE__INST6_SEG0 0x00013380 1470 #define UMC_BASE__INST6_SEG1 0x00194000 1471 #define UMC_BASE__INST6_SEG2 0x00427000 1472 #define UMC_BASE__INST6_SEG3 0 1473 #define UMC_BASE__INST6_SEG4 0 1474 #define UMC_BASE__INST6_SEG5 0 1475 1476 #define UMC_BASE__INST7_SEG0 0x000133A0 1477 #define UMC_BASE__INST7_SEG1 0x001D4000 1478 #define UMC_BASE__INST7_SEG2 0x00427400 1479 #define UMC_BASE__INST7_SEG3 0 1480 #define UMC_BASE__INST7_SEG4 0 1481 #define UMC_BASE__INST7_SEG5 0 1482 1483 #define UVD_BASE__INST0_SEG0 0x00007800 1484 #define UVD_BASE__INST0_SEG1 0x00007E00 1485 #define UVD_BASE__INST0_SEG2 0x00012180 1486 #define UVD_BASE__INST0_SEG3 0x00403000 1487 #define UVD_BASE__INST0_SEG4 0 1488 #define UVD_BASE__INST0_SEG5 0 1489 1490 #define UVD_BASE__INST1_SEG0 0x00007A00 1491 #define UVD_BASE__INST1_SEG1 0x00009000 1492 #define UVD_BASE__INST1_SEG2 0x000136E0 1493 #define UVD_BASE__INST1_SEG3 0x0042DC00 1494 #define UVD_BASE__INST1_SEG4 0 1495 #define UVD_BASE__INST1_SEG5 0 1496 1497 #define UVD_BASE__INST2_SEG0 0 1498 #define UVD_BASE__INST2_SEG1 0 1499 #define UVD_BASE__INST2_SEG2 0 1500 #define UVD_BASE__INST2_SEG3 0 1501 #define UVD_BASE__INST2_SEG4 0 1502 #define UVD_BASE__INST2_SEG5 0 1503 1504 #define UVD_BASE__INST3_SEG0 0 1505 #define UVD_BASE__INST3_SEG1 0 1506 #define UVD_BASE__INST3_SEG2 0 1507 #define UVD_BASE__INST3_SEG3 0 1508 #define UVD_BASE__INST3_SEG4 0 1509 #define UVD_BASE__INST3_SEG5 0 1510 1511 #define UVD_BASE__INST4_SEG0 0 1512 #define UVD_BASE__INST4_SEG1 0 1513 #define UVD_BASE__INST4_SEG2 0 1514 #define UVD_BASE__INST4_SEG3 0 1515 #define UVD_BASE__INST4_SEG4 0 1516 #define UVD_BASE__INST4_SEG5 0 1517 1518 #define UVD_BASE__INST5_SEG0 0 1519 #define UVD_BASE__INST5_SEG1 0 1520 #define UVD_BASE__INST5_SEG2 0 1521 #define UVD_BASE__INST5_SEG3 0 1522 #define UVD_BASE__INST5_SEG4 0 1523 #define UVD_BASE__INST5_SEG5 0 1524 1525 #define UVD_BASE__INST6_SEG0 0 1526 #define UVD_BASE__INST6_SEG1 0 1527 #define UVD_BASE__INST6_SEG2 0 1528 #define UVD_BASE__INST6_SEG3 0 1529 #define UVD_BASE__INST6_SEG4 0 1530 #define UVD_BASE__INST6_SEG5 0 1531 1532 #define UVD_BASE__INST7_SEG0 0 1533 #define UVD_BASE__INST7_SEG1 0 1534 #define UVD_BASE__INST7_SEG2 0 1535 #define UVD_BASE__INST7_SEG3 0 1536 #define UVD_BASE__INST7_SEG4 0 1537 #define UVD_BASE__INST7_SEG5 0 1538 1539 #define DBGU_IO_BASE__INST0_SEG0 0x000001E0 1540 #define DBGU_IO_BASE__INST0_SEG1 0x000125A0 1541 #define DBGU_IO_BASE__INST0_SEG2 0x0040B400 1542 #define DBGU_IO_BASE__INST0_SEG3 0 1543 #define DBGU_IO_BASE__INST0_SEG4 0 1544 #define DBGU_IO_BASE__INST0_SEG5 0 1545 1546 #define DBGU_IO_BASE__INST1_SEG0 0 1547 #define DBGU_IO_BASE__INST1_SEG1 0 1548 #define DBGU_IO_BASE__INST1_SEG2 0 1549 #define DBGU_IO_BASE__INST1_SEG3 0 1550 #define DBGU_IO_BASE__INST1_SEG4 0 1551 #define DBGU_IO_BASE__INST1_SEG5 0 1552 1553 #define DBGU_IO_BASE__INST2_SEG0 0 1554 #define DBGU_IO_BASE__INST2_SEG1 0 1555 #define DBGU_IO_BASE__INST2_SEG2 0 1556 #define DBGU_IO_BASE__INST2_SEG3 0 1557 #define DBGU_IO_BASE__INST2_SEG4 0 1558 #define DBGU_IO_BASE__INST2_SEG5 0 1559 1560 #define DBGU_IO_BASE__INST3_SEG0 0 1561 #define DBGU_IO_BASE__INST3_SEG1 0 1562 #define DBGU_IO_BASE__INST3_SEG2 0 1563 #define DBGU_IO_BASE__INST3_SEG3 0 1564 #define DBGU_IO_BASE__INST3_SEG4 0 1565 #define DBGU_IO_BASE__INST3_SEG5 0 1566 1567 #define DBGU_IO_BASE__INST4_SEG0 0 1568 #define DBGU_IO_BASE__INST4_SEG1 0 1569 #define DBGU_IO_BASE__INST4_SEG2 0 1570 #define DBGU_IO_BASE__INST4_SEG3 0 1571 #define DBGU_IO_BASE__INST4_SEG4 0 1572 #define DBGU_IO_BASE__INST4_SEG5 0 1573 1574 #define DBGU_IO_BASE__INST5_SEG0 0 1575 #define DBGU_IO_BASE__INST5_SEG1 0 1576 #define DBGU_IO_BASE__INST5_SEG2 0 1577 #define DBGU_IO_BASE__INST5_SEG3 0 1578 #define DBGU_IO_BASE__INST5_SEG4 0 1579 #define DBGU_IO_BASE__INST5_SEG5 0 1580 1581 #define DBGU_IO_BASE__INST6_SEG0 0 1582 #define DBGU_IO_BASE__INST6_SEG1 0 1583 #define DBGU_IO_BASE__INST6_SEG2 0 1584 #define DBGU_IO_BASE__INST6_SEG3 0 1585 #define DBGU_IO_BASE__INST6_SEG4 0 1586 #define DBGU_IO_BASE__INST6_SEG5 0 1587 1588 #define DBGU_IO_BASE__INST7_SEG0 0 1589 #define DBGU_IO_BASE__INST7_SEG1 0 1590 #define DBGU_IO_BASE__INST7_SEG2 0 1591 #define DBGU_IO_BASE__INST7_SEG3 0 1592 #define DBGU_IO_BASE__INST7_SEG4 0 1593 #define DBGU_IO_BASE__INST7_SEG5 0 1594 1595 #define RSMU_BASE__INST0_SEG0 0x00012000 1596 #define RSMU_BASE__INST0_SEG1 0 1597 #define RSMU_BASE__INST0_SEG2 0 1598 #define RSMU_BASE__INST0_SEG3 0 1599 #define RSMU_BASE__INST0_SEG4 0 1600 #define RSMU_BASE__INST0_SEG5 0 1601 1602 #define RSMU_BASE__INST1_SEG0 0 1603 #define RSMU_BASE__INST1_SEG1 0 1604 #define RSMU_BASE__INST1_SEG2 0 1605 #define RSMU_BASE__INST1_SEG3 0 1606 #define RSMU_BASE__INST1_SEG4 0 1607 #define RSMU_BASE__INST1_SEG5 0 1608 1609 #define RSMU_BASE__INST2_SEG0 0 1610 #define RSMU_BASE__INST2_SEG1 0 1611 #define RSMU_BASE__INST2_SEG2 0 1612 #define RSMU_BASE__INST2_SEG3 0 1613 #define RSMU_BASE__INST2_SEG4 0 1614 #define RSMU_BASE__INST2_SEG5 0 1615 1616 #define RSMU_BASE__INST3_SEG0 0 1617 #define RSMU_BASE__INST3_SEG1 0 1618 #define RSMU_BASE__INST3_SEG2 0 1619 #define RSMU_BASE__INST3_SEG3 0 1620 #define RSMU_BASE__INST3_SEG4 0 1621 #define RSMU_BASE__INST3_SEG5 0 1622 1623 #define RSMU_BASE__INST4_SEG0 0 1624 #define RSMU_BASE__INST4_SEG1 0 1625 #define RSMU_BASE__INST4_SEG2 0 1626 #define RSMU_BASE__INST4_SEG3 0 1627 #define RSMU_BASE__INST4_SEG4 0 1628 #define RSMU_BASE__INST4_SEG5 0 1629 1630 #define RSMU_BASE__INST5_SEG0 0 1631 #define RSMU_BASE__INST5_SEG1 0 1632 #define RSMU_BASE__INST5_SEG2 0 1633 #define RSMU_BASE__INST5_SEG3 0 1634 #define RSMU_BASE__INST5_SEG4 0 1635 #define RSMU_BASE__INST5_SEG5 0 1636 1637 #define RSMU_BASE__INST6_SEG0 0 1638 #define RSMU_BASE__INST6_SEG1 0 1639 #define RSMU_BASE__INST6_SEG2 0 1640 #define RSMU_BASE__INST6_SEG3 0 1641 #define RSMU_BASE__INST6_SEG4 0 1642 #define RSMU_BASE__INST6_SEG5 0 1643 1644 #define RSMU_BASE__INST7_SEG0 0 1645 #define RSMU_BASE__INST7_SEG1 0 1646 #define RSMU_BASE__INST7_SEG2 0 1647 #define RSMU_BASE__INST7_SEG3 0 1648 #define RSMU_BASE__INST7_SEG4 0 1649 #define RSMU_BASE__INST7_SEG5 0 1650 1651 1652 #endif 1653
Indexes created Sat Sep 20 22:09:52 GMT 2025