1 /* $NetBSD: navi10_ip_offset.h,v 1.2 2021/12/18 23:45:08 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _navi10_ip_offset_HEADER 24 #define _navi10_ip_offset_HEADER 25 26 #define MAX_INSTANCE 6 27 #define MAX_SEGMENT 6 28 29 30 struct IP_BASE_INSTANCE { 31 unsigned int segment[MAX_SEGMENT]; 32 }; 33 34 struct IP_BASE { 35 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 36 }; 37 38 39 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0, 0 } }, 40 { { 0, 0, 0, 0, 0, 0 } }, 41 { { 0, 0, 0, 0, 0, 0 } }, 42 { { 0, 0, 0, 0, 0, 0 } }, 43 { { 0, 0, 0, 0, 0, 0 } }, 44 { { 0, 0, 0, 0, 0, 0 } } } }; 45 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x00017E00, 0x0001B000 } }, 46 { { 0, 0, 0, 0, 0, 0 } }, 47 { { 0, 0, 0, 0, 0, 0 } }, 48 { { 0, 0, 0, 0, 0, 0 } }, 49 { { 0, 0, 0, 0, 0, 0 } }, 50 { { 0, 0, 0, 0, 0, 0 } } } }; 51 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0, 0 } }, 52 { { 0, 0, 0, 0, 0, 0 } }, 53 { { 0, 0, 0, 0, 0, 0 } }, 54 { { 0, 0, 0, 0, 0, 0 } }, 55 { { 0, 0, 0, 0, 0, 0 } }, 56 { { 0, 0, 0, 0, 0, 0 } } } }; 57 static const struct IP_BASE DCN_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0, 0 } }, 58 { { 0, 0, 0, 0, 0, 0 } }, 59 { { 0, 0, 0, 0, 0, 0 } }, 60 { { 0, 0, 0, 0, 0, 0 } }, 61 { { 0, 0, 0, 0, 0, 0 } }, 62 { { 0, 0, 0, 0, 0, 0 } } } }; 63 static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0, 0 } }, 64 { { 0, 0, 0, 0, 0, 0 } }, 65 { { 0, 0, 0, 0, 0, 0 } }, 66 { { 0, 0, 0, 0, 0, 0 } }, 67 { { 0, 0, 0, 0, 0, 0 } }, 68 { { 0, 0, 0, 0, 0, 0 } } } }; 69 static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0, 0, 0, 0 } }, 70 { { 0, 0, 0, 0, 0, 0 } }, 71 { { 0, 0, 0, 0, 0, 0 } }, 72 { { 0, 0, 0, 0, 0, 0 } }, 73 { { 0, 0, 0, 0, 0, 0 } }, 74 { { 0, 0, 0, 0, 0, 0 } } } }; 75 static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } }, 76 { { 0, 0, 0, 0, 0, 0 } }, 77 { { 0, 0, 0, 0, 0, 0 } }, 78 { { 0, 0, 0, 0, 0, 0 } }, 79 { { 0, 0, 0, 0, 0, 0 } }, 80 { { 0, 0, 0, 0, 0, 0 } } } }; 81 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } }, 82 { { 0, 0, 0, 0, 0, 0 } }, 83 { { 0, 0, 0, 0, 0, 0 } }, 84 { { 0, 0, 0, 0, 0, 0 } }, 85 { { 0, 0, 0, 0, 0, 0 } }, 86 { { 0, 0, 0, 0, 0, 0 } } } }; 87 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, 88 { { 0, 0, 0, 0, 0, 0 } }, 89 { { 0, 0, 0, 0, 0, 0 } }, 90 { { 0, 0, 0, 0, 0, 0 } }, 91 { { 0, 0, 0, 0, 0, 0 } }, 92 { { 0, 0, 0, 0, 0, 0 } } } }; 93 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, 94 { { 0, 0, 0, 0, 0, 0 } }, 95 { { 0, 0, 0, 0, 0, 0 } }, 96 { { 0, 0, 0, 0, 0, 0 } }, 97 { { 0, 0, 0, 0, 0, 0 } }, 98 { { 0, 0, 0, 0, 0, 0 } } } }; 99 static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } }, 100 { { 0, 0, 0, 0, 0, 0 } }, 101 { { 0, 0, 0, 0, 0, 0 } }, 102 { { 0, 0, 0, 0, 0, 0 } }, 103 { { 0, 0, 0, 0, 0, 0 } }, 104 { { 0, 0, 0, 0, 0, 0 } } } }; 105 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } }, 106 { { 0, 0, 0, 0, 0, 0 } }, 107 { { 0, 0, 0, 0, 0, 0 } }, 108 { { 0, 0, 0, 0, 0, 0 } }, 109 { { 0, 0, 0, 0, 0, 0 } }, 110 { { 0, 0, 0, 0, 0, 0 } } } }; 111 static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0, 0 } }, 115 { { 0, 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0, 0 } } } }; 117 static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } }, 118 { { 0, 0, 0, 0, 0, 0 } }, 119 { { 0, 0, 0, 0, 0, 0 } }, 120 { { 0, 0, 0, 0, 0, 0 } }, 121 { { 0, 0, 0, 0, 0, 0 } }, 122 { { 0, 0, 0, 0, 0, 0 } } } }; 123 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, 124 { { 0, 0, 0, 0, 0, 0 } }, 125 { { 0, 0, 0, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0, 0 } } } }; 129 static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0, 0 } }, 132 { { 0, 0, 0, 0, 0, 0 } }, 133 { { 0, 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0, 0 } } } }; 135 static const struct IP_BASE VCN_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } }, 136 { { 0, 0, 0, 0, 0, 0 } }, 137 { { 0, 0, 0, 0, 0, 0 } }, 138 { { 0, 0, 0, 0, 0, 0 } }, 139 { { 0, 0, 0, 0, 0, 0 } }, 140 { { 0, 0, 0, 0, 0, 0 } } } }; 141 142 143 #define ATHUB_BASE__INST0_SEG0 0x00000C00 144 #define ATHUB_BASE__INST0_SEG1 0 145 #define ATHUB_BASE__INST0_SEG2 0 146 #define ATHUB_BASE__INST0_SEG3 0 147 #define ATHUB_BASE__INST0_SEG4 0 148 #define ATHUB_BASE__INST0_SEG5 0 149 150 #define ATHUB_BASE__INST1_SEG0 0 151 #define ATHUB_BASE__INST1_SEG1 0 152 #define ATHUB_BASE__INST1_SEG2 0 153 #define ATHUB_BASE__INST1_SEG3 0 154 #define ATHUB_BASE__INST1_SEG4 0 155 #define ATHUB_BASE__INST1_SEG5 0 156 157 #define ATHUB_BASE__INST2_SEG0 0 158 #define ATHUB_BASE__INST2_SEG1 0 159 #define ATHUB_BASE__INST2_SEG2 0 160 #define ATHUB_BASE__INST2_SEG3 0 161 #define ATHUB_BASE__INST2_SEG4 0 162 #define ATHUB_BASE__INST2_SEG5 0 163 164 #define ATHUB_BASE__INST3_SEG0 0 165 #define ATHUB_BASE__INST3_SEG1 0 166 #define ATHUB_BASE__INST3_SEG2 0 167 #define ATHUB_BASE__INST3_SEG3 0 168 #define ATHUB_BASE__INST3_SEG4 0 169 #define ATHUB_BASE__INST3_SEG5 0 170 171 #define ATHUB_BASE__INST4_SEG0 0 172 #define ATHUB_BASE__INST4_SEG1 0 173 #define ATHUB_BASE__INST4_SEG2 0 174 #define ATHUB_BASE__INST4_SEG3 0 175 #define ATHUB_BASE__INST4_SEG4 0 176 #define ATHUB_BASE__INST4_SEG5 0 177 178 #define ATHUB_BASE__INST5_SEG0 0 179 #define ATHUB_BASE__INST5_SEG1 0 180 #define ATHUB_BASE__INST5_SEG2 0 181 #define ATHUB_BASE__INST5_SEG3 0 182 #define ATHUB_BASE__INST5_SEG4 0 183 #define ATHUB_BASE__INST5_SEG5 0 184 185 #define CLK_BASE__INST0_SEG0 0x00016C00 186 #define CLK_BASE__INST0_SEG1 0x00016E00 187 #define CLK_BASE__INST0_SEG2 0x00017000 188 #define CLK_BASE__INST0_SEG3 0x00017200 189 #define CLK_BASE__INST0_SEG4 0x00017E00 190 #define CLK_BASE__INST0_SEG5 0x0001B000 191 192 #define CLK_BASE__INST1_SEG0 0 193 #define CLK_BASE__INST1_SEG1 0 194 #define CLK_BASE__INST1_SEG2 0 195 #define CLK_BASE__INST1_SEG3 0 196 #define CLK_BASE__INST1_SEG4 0 197 #define CLK_BASE__INST1_SEG5 0 198 199 #define CLK_BASE__INST2_SEG0 0 200 #define CLK_BASE__INST2_SEG1 0 201 #define CLK_BASE__INST2_SEG2 0 202 #define CLK_BASE__INST2_SEG3 0 203 #define CLK_BASE__INST2_SEG4 0 204 #define CLK_BASE__INST2_SEG5 0 205 206 #define CLK_BASE__INST3_SEG0 0 207 #define CLK_BASE__INST3_SEG1 0 208 #define CLK_BASE__INST3_SEG2 0 209 #define CLK_BASE__INST3_SEG3 0 210 #define CLK_BASE__INST3_SEG4 0 211 #define CLK_BASE__INST3_SEG5 0 212 213 #define CLK_BASE__INST4_SEG0 0 214 #define CLK_BASE__INST4_SEG1 0 215 #define CLK_BASE__INST4_SEG2 0 216 #define CLK_BASE__INST4_SEG3 0 217 #define CLK_BASE__INST4_SEG4 0 218 #define CLK_BASE__INST4_SEG5 0 219 220 #define CLK_BASE__INST5_SEG0 0 221 #define CLK_BASE__INST5_SEG1 0 222 #define CLK_BASE__INST5_SEG2 0 223 #define CLK_BASE__INST5_SEG3 0 224 #define CLK_BASE__INST5_SEG4 0 225 #define CLK_BASE__INST5_SEG5 0 226 227 #define DF_BASE__INST0_SEG0 0x00007000 228 #define DF_BASE__INST0_SEG1 0 229 #define DF_BASE__INST0_SEG2 0 230 #define DF_BASE__INST0_SEG3 0 231 #define DF_BASE__INST0_SEG4 0 232 #define DF_BASE__INST0_SEG5 0 233 234 #define DF_BASE__INST1_SEG0 0 235 #define DF_BASE__INST1_SEG1 0 236 #define DF_BASE__INST1_SEG2 0 237 #define DF_BASE__INST1_SEG3 0 238 #define DF_BASE__INST1_SEG4 0 239 #define DF_BASE__INST1_SEG5 0 240 241 #define DF_BASE__INST2_SEG0 0 242 #define DF_BASE__INST2_SEG1 0 243 #define DF_BASE__INST2_SEG2 0 244 #define DF_BASE__INST2_SEG3 0 245 #define DF_BASE__INST2_SEG4 0 246 #define DF_BASE__INST2_SEG5 0 247 248 #define DF_BASE__INST3_SEG0 0 249 #define DF_BASE__INST3_SEG1 0 250 #define DF_BASE__INST3_SEG2 0 251 #define DF_BASE__INST3_SEG3 0 252 #define DF_BASE__INST3_SEG4 0 253 #define DF_BASE__INST3_SEG5 0 254 255 #define DF_BASE__INST4_SEG0 0 256 #define DF_BASE__INST4_SEG1 0 257 #define DF_BASE__INST4_SEG2 0 258 #define DF_BASE__INST4_SEG3 0 259 #define DF_BASE__INST4_SEG4 0 260 #define DF_BASE__INST4_SEG5 0 261 262 #define DF_BASE__INST5_SEG0 0 263 #define DF_BASE__INST5_SEG1 0 264 #define DF_BASE__INST5_SEG2 0 265 #define DF_BASE__INST5_SEG3 0 266 #define DF_BASE__INST5_SEG4 0 267 #define DF_BASE__INST5_SEG5 0 268 269 #define DCN_BASE__INST0_SEG0 0x00000012 270 #define DCN_BASE__INST0_SEG1 0x000000C0 271 #define DCN_BASE__INST0_SEG2 0x000034C0 272 #define DCN_BASE__INST0_SEG3 0x00009000 273 #define DCN_BASE__INST0_SEG4 0 274 #define DCN_BASE__INST0_SEG5 0 275 276 #define DCN_BASE__INST1_SEG0 0 277 #define DCN_BASE__INST1_SEG1 0 278 #define DCN_BASE__INST1_SEG2 0 279 #define DCN_BASE__INST1_SEG3 0 280 #define DCN_BASE__INST1_SEG4 0 281 #define DCN_BASE__INST1_SEG5 0 282 283 #define DCN_BASE__INST2_SEG0 0 284 #define DCN_BASE__INST2_SEG1 0 285 #define DCN_BASE__INST2_SEG2 0 286 #define DCN_BASE__INST2_SEG3 0 287 #define DCN_BASE__INST2_SEG4 0 288 #define DCN_BASE__INST2_SEG5 0 289 290 #define DCN_BASE__INST3_SEG0 0 291 #define DCN_BASE__INST3_SEG1 0 292 #define DCN_BASE__INST3_SEG2 0 293 #define DCN_BASE__INST3_SEG3 0 294 #define DCN_BASE__INST3_SEG4 0 295 #define DCN_BASE__INST3_SEG5 0 296 297 #define DCN_BASE__INST4_SEG0 0 298 #define DCN_BASE__INST4_SEG1 0 299 #define DCN_BASE__INST4_SEG2 0 300 #define DCN_BASE__INST4_SEG3 0 301 #define DCN_BASE__INST4_SEG4 0 302 #define DCN_BASE__INST4_SEG5 0 303 304 #define DCN_BASE__INST5_SEG0 0 305 #define DCN_BASE__INST5_SEG1 0 306 #define DCN_BASE__INST5_SEG2 0 307 #define DCN_BASE__INST5_SEG3 0 308 #define DCN_BASE__INST5_SEG4 0 309 #define DCN_BASE__INST5_SEG5 0 310 311 #define FUSE_BASE__INST0_SEG0 0x00017400 312 #define FUSE_BASE__INST0_SEG1 0 313 #define FUSE_BASE__INST0_SEG2 0 314 #define FUSE_BASE__INST0_SEG3 0 315 #define FUSE_BASE__INST0_SEG4 0 316 #define FUSE_BASE__INST0_SEG5 0 317 318 #define FUSE_BASE__INST1_SEG0 0 319 #define FUSE_BASE__INST1_SEG1 0 320 #define FUSE_BASE__INST1_SEG2 0 321 #define FUSE_BASE__INST1_SEG3 0 322 #define FUSE_BASE__INST1_SEG4 0 323 #define FUSE_BASE__INST1_SEG5 0 324 325 #define FUSE_BASE__INST2_SEG0 0 326 #define FUSE_BASE__INST2_SEG1 0 327 #define FUSE_BASE__INST2_SEG2 0 328 #define FUSE_BASE__INST2_SEG3 0 329 #define FUSE_BASE__INST2_SEG4 0 330 #define FUSE_BASE__INST2_SEG5 0 331 332 #define FUSE_BASE__INST3_SEG0 0 333 #define FUSE_BASE__INST3_SEG1 0 334 #define FUSE_BASE__INST3_SEG2 0 335 #define FUSE_BASE__INST3_SEG3 0 336 #define FUSE_BASE__INST3_SEG4 0 337 #define FUSE_BASE__INST3_SEG5 0 338 339 #define FUSE_BASE__INST4_SEG0 0 340 #define FUSE_BASE__INST4_SEG1 0 341 #define FUSE_BASE__INST4_SEG2 0 342 #define FUSE_BASE__INST4_SEG3 0 343 #define FUSE_BASE__INST4_SEG4 0 344 #define FUSE_BASE__INST4_SEG5 0 345 346 #define FUSE_BASE__INST5_SEG0 0 347 #define FUSE_BASE__INST5_SEG1 0 348 #define FUSE_BASE__INST5_SEG2 0 349 #define FUSE_BASE__INST5_SEG3 0 350 #define FUSE_BASE__INST5_SEG4 0 351 #define FUSE_BASE__INST5_SEG5 0 352 353 #define GC_BASE__INST0_SEG0 0x00001260 354 #define GC_BASE__INST0_SEG1 0x0000A000 355 #define GC_BASE__INST0_SEG2 0 356 #define GC_BASE__INST0_SEG3 0 357 #define GC_BASE__INST0_SEG4 0 358 #define GC_BASE__INST0_SEG5 0 359 360 #define GC_BASE__INST1_SEG0 0 361 #define GC_BASE__INST1_SEG1 0 362 #define GC_BASE__INST1_SEG2 0 363 #define GC_BASE__INST1_SEG3 0 364 #define GC_BASE__INST1_SEG4 0 365 #define GC_BASE__INST1_SEG5 0 366 367 #define GC_BASE__INST2_SEG0 0 368 #define GC_BASE__INST2_SEG1 0 369 #define GC_BASE__INST2_SEG2 0 370 #define GC_BASE__INST2_SEG3 0 371 #define GC_BASE__INST2_SEG4 0 372 #define GC_BASE__INST2_SEG5 0 373 374 #define GC_BASE__INST3_SEG0 0 375 #define GC_BASE__INST3_SEG1 0 376 #define GC_BASE__INST3_SEG2 0 377 #define GC_BASE__INST3_SEG3 0 378 #define GC_BASE__INST3_SEG4 0 379 #define GC_BASE__INST3_SEG5 0 380 381 #define GC_BASE__INST4_SEG0 0 382 #define GC_BASE__INST4_SEG1 0 383 #define GC_BASE__INST4_SEG2 0 384 #define GC_BASE__INST4_SEG3 0 385 #define GC_BASE__INST4_SEG4 0 386 #define GC_BASE__INST4_SEG5 0 387 388 #define GC_BASE__INST5_SEG0 0 389 #define GC_BASE__INST5_SEG1 0 390 #define GC_BASE__INST5_SEG2 0 391 #define GC_BASE__INST5_SEG3 0 392 #define GC_BASE__INST5_SEG4 0 393 #define GC_BASE__INST5_SEG5 0 394 395 #define HDP_BASE__INST0_SEG0 0x00000F20 396 #define HDP_BASE__INST0_SEG1 0 397 #define HDP_BASE__INST0_SEG2 0 398 #define HDP_BASE__INST0_SEG3 0 399 #define HDP_BASE__INST0_SEG4 0 400 #define HDP_BASE__INST0_SEG5 0 401 402 #define HDP_BASE__INST1_SEG0 0 403 #define HDP_BASE__INST1_SEG1 0 404 #define HDP_BASE__INST1_SEG2 0 405 #define HDP_BASE__INST1_SEG3 0 406 #define HDP_BASE__INST1_SEG4 0 407 #define HDP_BASE__INST1_SEG5 0 408 409 #define HDP_BASE__INST2_SEG0 0 410 #define HDP_BASE__INST2_SEG1 0 411 #define HDP_BASE__INST2_SEG2 0 412 #define HDP_BASE__INST2_SEG3 0 413 #define HDP_BASE__INST2_SEG4 0 414 #define HDP_BASE__INST2_SEG5 0 415 416 #define HDP_BASE__INST3_SEG0 0 417 #define HDP_BASE__INST3_SEG1 0 418 #define HDP_BASE__INST3_SEG2 0 419 #define HDP_BASE__INST3_SEG3 0 420 #define HDP_BASE__INST3_SEG4 0 421 #define HDP_BASE__INST3_SEG5 0 422 423 #define HDP_BASE__INST4_SEG0 0 424 #define HDP_BASE__INST4_SEG1 0 425 #define HDP_BASE__INST4_SEG2 0 426 #define HDP_BASE__INST4_SEG3 0 427 #define HDP_BASE__INST4_SEG4 0 428 #define HDP_BASE__INST4_SEG5 0 429 430 #define HDP_BASE__INST5_SEG0 0 431 #define HDP_BASE__INST5_SEG1 0 432 #define HDP_BASE__INST5_SEG2 0 433 #define HDP_BASE__INST5_SEG3 0 434 #define HDP_BASE__INST5_SEG4 0 435 #define HDP_BASE__INST5_SEG5 0 436 437 #define MMHUB_BASE__INST0_SEG0 0x0001A000 438 #define MMHUB_BASE__INST0_SEG1 0 439 #define MMHUB_BASE__INST0_SEG2 0 440 #define MMHUB_BASE__INST0_SEG3 0 441 #define MMHUB_BASE__INST0_SEG4 0 442 #define MMHUB_BASE__INST0_SEG5 0 443 444 #define MMHUB_BASE__INST1_SEG0 0 445 #define MMHUB_BASE__INST1_SEG1 0 446 #define MMHUB_BASE__INST1_SEG2 0 447 #define MMHUB_BASE__INST1_SEG3 0 448 #define MMHUB_BASE__INST1_SEG4 0 449 #define MMHUB_BASE__INST1_SEG5 0 450 451 #define MMHUB_BASE__INST2_SEG0 0 452 #define MMHUB_BASE__INST2_SEG1 0 453 #define MMHUB_BASE__INST2_SEG2 0 454 #define MMHUB_BASE__INST2_SEG3 0 455 #define MMHUB_BASE__INST2_SEG4 0 456 #define MMHUB_BASE__INST2_SEG5 0 457 458 #define MMHUB_BASE__INST3_SEG0 0 459 #define MMHUB_BASE__INST3_SEG1 0 460 #define MMHUB_BASE__INST3_SEG2 0 461 #define MMHUB_BASE__INST3_SEG3 0 462 #define MMHUB_BASE__INST3_SEG4 0 463 #define MMHUB_BASE__INST3_SEG5 0 464 465 #define MMHUB_BASE__INST4_SEG0 0 466 #define MMHUB_BASE__INST4_SEG1 0 467 #define MMHUB_BASE__INST4_SEG2 0 468 #define MMHUB_BASE__INST4_SEG3 0 469 #define MMHUB_BASE__INST4_SEG4 0 470 #define MMHUB_BASE__INST4_SEG5 0 471 472 #define MMHUB_BASE__INST5_SEG0 0 473 #define MMHUB_BASE__INST5_SEG1 0 474 #define MMHUB_BASE__INST5_SEG2 0 475 #define MMHUB_BASE__INST5_SEG3 0 476 #define MMHUB_BASE__INST5_SEG4 0 477 #define MMHUB_BASE__INST5_SEG5 0 478 479 #define MP0_BASE__INST0_SEG0 0x00016000 480 #define MP0_BASE__INST0_SEG1 0 481 #define MP0_BASE__INST0_SEG2 0 482 #define MP0_BASE__INST0_SEG3 0 483 #define MP0_BASE__INST0_SEG4 0 484 #define MP0_BASE__INST0_SEG5 0 485 486 #define MP0_BASE__INST1_SEG0 0 487 #define MP0_BASE__INST1_SEG1 0 488 #define MP0_BASE__INST1_SEG2 0 489 #define MP0_BASE__INST1_SEG3 0 490 #define MP0_BASE__INST1_SEG4 0 491 #define MP0_BASE__INST1_SEG5 0 492 493 #define MP0_BASE__INST2_SEG0 0 494 #define MP0_BASE__INST2_SEG1 0 495 #define MP0_BASE__INST2_SEG2 0 496 #define MP0_BASE__INST2_SEG3 0 497 #define MP0_BASE__INST2_SEG4 0 498 #define MP0_BASE__INST2_SEG5 0 499 500 #define MP0_BASE__INST3_SEG0 0 501 #define MP0_BASE__INST3_SEG1 0 502 #define MP0_BASE__INST3_SEG2 0 503 #define MP0_BASE__INST3_SEG3 0 504 #define MP0_BASE__INST3_SEG4 0 505 #define MP0_BASE__INST3_SEG5 0 506 507 #define MP0_BASE__INST4_SEG0 0 508 #define MP0_BASE__INST4_SEG1 0 509 #define MP0_BASE__INST4_SEG2 0 510 #define MP0_BASE__INST4_SEG3 0 511 #define MP0_BASE__INST4_SEG4 0 512 #define MP0_BASE__INST4_SEG5 0 513 514 #define MP0_BASE__INST5_SEG0 0 515 #define MP0_BASE__INST5_SEG1 0 516 #define MP0_BASE__INST5_SEG2 0 517 #define MP0_BASE__INST5_SEG3 0 518 #define MP0_BASE__INST5_SEG4 0 519 #define MP0_BASE__INST5_SEG5 0 520 521 #define MP1_BASE__INST0_SEG0 0x00016000 522 #define MP1_BASE__INST0_SEG1 0 523 #define MP1_BASE__INST0_SEG2 0 524 #define MP1_BASE__INST0_SEG3 0 525 #define MP1_BASE__INST0_SEG4 0 526 #define MP1_BASE__INST0_SEG5 0 527 528 #define MP1_BASE__INST1_SEG0 0 529 #define MP1_BASE__INST1_SEG1 0 530 #define MP1_BASE__INST1_SEG2 0 531 #define MP1_BASE__INST1_SEG3 0 532 #define MP1_BASE__INST1_SEG4 0 533 #define MP1_BASE__INST1_SEG5 0 534 535 #define MP1_BASE__INST2_SEG0 0 536 #define MP1_BASE__INST2_SEG1 0 537 #define MP1_BASE__INST2_SEG2 0 538 #define MP1_BASE__INST2_SEG3 0 539 #define MP1_BASE__INST2_SEG4 0 540 #define MP1_BASE__INST2_SEG5 0 541 542 #define MP1_BASE__INST3_SEG0 0 543 #define MP1_BASE__INST3_SEG1 0 544 #define MP1_BASE__INST3_SEG2 0 545 #define MP1_BASE__INST3_SEG3 0 546 #define MP1_BASE__INST3_SEG4 0 547 #define MP1_BASE__INST3_SEG5 0 548 549 #define MP1_BASE__INST4_SEG0 0 550 #define MP1_BASE__INST4_SEG1 0 551 #define MP1_BASE__INST4_SEG2 0 552 #define MP1_BASE__INST4_SEG3 0 553 #define MP1_BASE__INST4_SEG4 0 554 #define MP1_BASE__INST4_SEG5 0 555 556 #define MP1_BASE__INST5_SEG0 0 557 #define MP1_BASE__INST5_SEG1 0 558 #define MP1_BASE__INST5_SEG2 0 559 #define MP1_BASE__INST5_SEG3 0 560 #define MP1_BASE__INST5_SEG4 0 561 #define MP1_BASE__INST5_SEG5 0 562 563 #define NBIO_BASE__INST0_SEG0 0x00000000 564 #define NBIO_BASE__INST0_SEG1 0x00000014 565 #define NBIO_BASE__INST0_SEG2 0x00000D20 566 #define NBIO_BASE__INST0_SEG3 0x00010400 567 #define NBIO_BASE__INST0_SEG4 0 568 #define NBIO_BASE__INST0_SEG5 0 569 570 #define NBIO_BASE__INST1_SEG0 0 571 #define NBIO_BASE__INST1_SEG1 0 572 #define NBIO_BASE__INST1_SEG2 0 573 #define NBIO_BASE__INST1_SEG3 0 574 #define NBIO_BASE__INST1_SEG4 0 575 #define NBIO_BASE__INST1_SEG5 0 576 577 #define NBIO_BASE__INST2_SEG0 0 578 #define NBIO_BASE__INST2_SEG1 0 579 #define NBIO_BASE__INST2_SEG2 0 580 #define NBIO_BASE__INST2_SEG3 0 581 #define NBIO_BASE__INST2_SEG4 0 582 #define NBIO_BASE__INST2_SEG5 0 583 584 #define NBIO_BASE__INST3_SEG0 0 585 #define NBIO_BASE__INST3_SEG1 0 586 #define NBIO_BASE__INST3_SEG2 0 587 #define NBIO_BASE__INST3_SEG3 0 588 #define NBIO_BASE__INST3_SEG4 0 589 #define NBIO_BASE__INST3_SEG5 0 590 591 #define NBIO_BASE__INST4_SEG0 0 592 #define NBIO_BASE__INST4_SEG1 0 593 #define NBIO_BASE__INST4_SEG2 0 594 #define NBIO_BASE__INST4_SEG3 0 595 #define NBIO_BASE__INST4_SEG4 0 596 #define NBIO_BASE__INST4_SEG5 0 597 598 #define NBIO_BASE__INST5_SEG0 0 599 #define NBIO_BASE__INST5_SEG1 0 600 #define NBIO_BASE__INST5_SEG2 0 601 #define NBIO_BASE__INST5_SEG3 0 602 #define NBIO_BASE__INST5_SEG4 0 603 #define NBIO_BASE__INST5_SEG5 0 604 605 #define OSSSYS_BASE__INST0_SEG0 0x000010A0 606 #define OSSSYS_BASE__INST0_SEG1 0 607 #define OSSSYS_BASE__INST0_SEG2 0 608 #define OSSSYS_BASE__INST0_SEG3 0 609 #define OSSSYS_BASE__INST0_SEG4 0 610 #define OSSSYS_BASE__INST0_SEG5 0 611 612 #define OSSSYS_BASE__INST1_SEG0 0 613 #define OSSSYS_BASE__INST1_SEG1 0 614 #define OSSSYS_BASE__INST1_SEG2 0 615 #define OSSSYS_BASE__INST1_SEG3 0 616 #define OSSSYS_BASE__INST1_SEG4 0 617 #define OSSSYS_BASE__INST1_SEG5 0 618 619 #define OSSSYS_BASE__INST2_SEG0 0 620 #define OSSSYS_BASE__INST2_SEG1 0 621 #define OSSSYS_BASE__INST2_SEG2 0 622 #define OSSSYS_BASE__INST2_SEG3 0 623 #define OSSSYS_BASE__INST2_SEG4 0 624 #define OSSSYS_BASE__INST2_SEG5 0 625 626 #define OSSSYS_BASE__INST3_SEG0 0 627 #define OSSSYS_BASE__INST3_SEG1 0 628 #define OSSSYS_BASE__INST3_SEG2 0 629 #define OSSSYS_BASE__INST3_SEG3 0 630 #define OSSSYS_BASE__INST3_SEG4 0 631 #define OSSSYS_BASE__INST3_SEG5 0 632 633 #define OSSSYS_BASE__INST4_SEG0 0 634 #define OSSSYS_BASE__INST4_SEG1 0 635 #define OSSSYS_BASE__INST4_SEG2 0 636 #define OSSSYS_BASE__INST4_SEG3 0 637 #define OSSSYS_BASE__INST4_SEG4 0 638 #define OSSSYS_BASE__INST4_SEG5 0 639 640 #define OSSSYS_BASE__INST5_SEG0 0 641 #define OSSSYS_BASE__INST5_SEG1 0 642 #define OSSSYS_BASE__INST5_SEG2 0 643 #define OSSSYS_BASE__INST5_SEG3 0 644 #define OSSSYS_BASE__INST5_SEG4 0 645 #define OSSSYS_BASE__INST5_SEG5 0 646 647 #define RSMU_BASE__INST0_SEG0 0x00012000 648 #define RSMU_BASE__INST0_SEG1 0 649 #define RSMU_BASE__INST0_SEG2 0 650 #define RSMU_BASE__INST0_SEG3 0 651 #define RSMU_BASE__INST0_SEG4 0 652 #define RSMU_BASE__INST0_SEG5 0 653 654 #define RSMU_BASE__INST1_SEG0 0 655 #define RSMU_BASE__INST1_SEG1 0 656 #define RSMU_BASE__INST1_SEG2 0 657 #define RSMU_BASE__INST1_SEG3 0 658 #define RSMU_BASE__INST1_SEG4 0 659 #define RSMU_BASE__INST1_SEG5 0 660 661 #define RSMU_BASE__INST2_SEG0 0 662 #define RSMU_BASE__INST2_SEG1 0 663 #define RSMU_BASE__INST2_SEG2 0 664 #define RSMU_BASE__INST2_SEG3 0 665 #define RSMU_BASE__INST2_SEG4 0 666 #define RSMU_BASE__INST2_SEG5 0 667 668 #define RSMU_BASE__INST3_SEG0 0 669 #define RSMU_BASE__INST3_SEG1 0 670 #define RSMU_BASE__INST3_SEG2 0 671 #define RSMU_BASE__INST3_SEG3 0 672 #define RSMU_BASE__INST3_SEG4 0 673 #define RSMU_BASE__INST3_SEG5 0 674 675 #define RSMU_BASE__INST4_SEG0 0 676 #define RSMU_BASE__INST4_SEG1 0 677 #define RSMU_BASE__INST4_SEG2 0 678 #define RSMU_BASE__INST4_SEG3 0 679 #define RSMU_BASE__INST4_SEG4 0 680 #define RSMU_BASE__INST4_SEG5 0 681 682 #define RSMU_BASE__INST5_SEG0 0 683 #define RSMU_BASE__INST5_SEG1 0 684 #define RSMU_BASE__INST5_SEG2 0 685 #define RSMU_BASE__INST5_SEG3 0 686 #define RSMU_BASE__INST5_SEG4 0 687 #define RSMU_BASE__INST5_SEG5 0 688 689 #define SMUIO_BASE__INST0_SEG0 0x00016800 690 #define SMUIO_BASE__INST0_SEG1 0x00016A00 691 #define SMUIO_BASE__INST0_SEG2 0 692 #define SMUIO_BASE__INST0_SEG3 0 693 #define SMUIO_BASE__INST0_SEG4 0 694 #define SMUIO_BASE__INST0_SEG5 0 695 696 #define SMUIO_BASE__INST1_SEG0 0 697 #define SMUIO_BASE__INST1_SEG1 0 698 #define SMUIO_BASE__INST1_SEG2 0 699 #define SMUIO_BASE__INST1_SEG3 0 700 #define SMUIO_BASE__INST1_SEG4 0 701 #define SMUIO_BASE__INST1_SEG5 0 702 703 #define SMUIO_BASE__INST2_SEG0 0 704 #define SMUIO_BASE__INST2_SEG1 0 705 #define SMUIO_BASE__INST2_SEG2 0 706 #define SMUIO_BASE__INST2_SEG3 0 707 #define SMUIO_BASE__INST2_SEG4 0 708 #define SMUIO_BASE__INST2_SEG5 0 709 710 #define SMUIO_BASE__INST3_SEG0 0 711 #define SMUIO_BASE__INST3_SEG1 0 712 #define SMUIO_BASE__INST3_SEG2 0 713 #define SMUIO_BASE__INST3_SEG3 0 714 #define SMUIO_BASE__INST3_SEG4 0 715 #define SMUIO_BASE__INST3_SEG5 0 716 717 #define SMUIO_BASE__INST4_SEG0 0 718 #define SMUIO_BASE__INST4_SEG1 0 719 #define SMUIO_BASE__INST4_SEG2 0 720 #define SMUIO_BASE__INST4_SEG3 0 721 #define SMUIO_BASE__INST4_SEG4 0 722 #define SMUIO_BASE__INST4_SEG5 0 723 724 #define SMUIO_BASE__INST5_SEG0 0 725 #define SMUIO_BASE__INST5_SEG1 0 726 #define SMUIO_BASE__INST5_SEG2 0 727 #define SMUIO_BASE__INST5_SEG3 0 728 #define SMUIO_BASE__INST5_SEG4 0 729 #define SMUIO_BASE__INST5_SEG5 0 730 731 #define THM_BASE__INST0_SEG0 0x00016600 732 #define THM_BASE__INST0_SEG1 0 733 #define THM_BASE__INST0_SEG2 0 734 #define THM_BASE__INST0_SEG3 0 735 #define THM_BASE__INST0_SEG4 0 736 #define THM_BASE__INST0_SEG5 0 737 738 #define THM_BASE__INST1_SEG0 0 739 #define THM_BASE__INST1_SEG1 0 740 #define THM_BASE__INST1_SEG2 0 741 #define THM_BASE__INST1_SEG3 0 742 #define THM_BASE__INST1_SEG4 0 743 #define THM_BASE__INST1_SEG5 0 744 745 #define THM_BASE__INST2_SEG0 0 746 #define THM_BASE__INST2_SEG1 0 747 #define THM_BASE__INST2_SEG2 0 748 #define THM_BASE__INST2_SEG3 0 749 #define THM_BASE__INST2_SEG4 0 750 #define THM_BASE__INST2_SEG5 0 751 752 #define THM_BASE__INST3_SEG0 0 753 #define THM_BASE__INST3_SEG1 0 754 #define THM_BASE__INST3_SEG2 0 755 #define THM_BASE__INST3_SEG3 0 756 #define THM_BASE__INST3_SEG4 0 757 #define THM_BASE__INST3_SEG5 0 758 759 #define THM_BASE__INST4_SEG0 0 760 #define THM_BASE__INST4_SEG1 0 761 #define THM_BASE__INST4_SEG2 0 762 #define THM_BASE__INST4_SEG3 0 763 #define THM_BASE__INST4_SEG4 0 764 #define THM_BASE__INST4_SEG5 0 765 766 #define THM_BASE__INST5_SEG0 0 767 #define THM_BASE__INST5_SEG1 0 768 #define THM_BASE__INST5_SEG2 0 769 #define THM_BASE__INST5_SEG3 0 770 #define THM_BASE__INST5_SEG4 0 771 #define THM_BASE__INST5_SEG5 0 772 773 #define UMC_BASE__INST0_SEG0 0x00014000 774 #define UMC_BASE__INST0_SEG1 0 775 #define UMC_BASE__INST0_SEG2 0 776 #define UMC_BASE__INST0_SEG3 0 777 #define UMC_BASE__INST0_SEG4 0 778 #define UMC_BASE__INST0_SEG5 0 779 780 #define UMC_BASE__INST1_SEG0 0 781 #define UMC_BASE__INST1_SEG1 0 782 #define UMC_BASE__INST1_SEG2 0 783 #define UMC_BASE__INST1_SEG3 0 784 #define UMC_BASE__INST1_SEG4 0 785 #define UMC_BASE__INST1_SEG5 0 786 787 #define UMC_BASE__INST2_SEG0 0 788 #define UMC_BASE__INST2_SEG1 0 789 #define UMC_BASE__INST2_SEG2 0 790 #define UMC_BASE__INST2_SEG3 0 791 #define UMC_BASE__INST2_SEG4 0 792 #define UMC_BASE__INST2_SEG5 0 793 794 #define UMC_BASE__INST3_SEG0 0 795 #define UMC_BASE__INST3_SEG1 0 796 #define UMC_BASE__INST3_SEG2 0 797 #define UMC_BASE__INST3_SEG3 0 798 #define UMC_BASE__INST3_SEG4 0 799 #define UMC_BASE__INST3_SEG5 0 800 801 #define UMC_BASE__INST4_SEG0 0 802 #define UMC_BASE__INST4_SEG1 0 803 #define UMC_BASE__INST4_SEG2 0 804 #define UMC_BASE__INST4_SEG3 0 805 #define UMC_BASE__INST4_SEG4 0 806 #define UMC_BASE__INST4_SEG5 0 807 808 #define UMC_BASE__INST5_SEG0 0 809 #define UMC_BASE__INST5_SEG1 0 810 #define UMC_BASE__INST5_SEG2 0 811 #define UMC_BASE__INST5_SEG3 0 812 #define UMC_BASE__INST5_SEG4 0 813 #define UMC_BASE__INST5_SEG5 0 814 815 #define VCN_BASE__INST0_SEG0 0x00007800 816 #define VCN_BASE__INST0_SEG1 0x00007E00 817 #define VCN_BASE__INST0_SEG2 0 818 #define VCN_BASE__INST0_SEG3 0 819 #define VCN_BASE__INST0_SEG4 0 820 #define VCN_BASE__INST0_SEG5 0 821 822 #define VCN_BASE__INST1_SEG0 0 823 #define VCN_BASE__INST1_SEG1 0 824 #define VCN_BASE__INST1_SEG2 0 825 #define VCN_BASE__INST1_SEG3 0 826 #define VCN_BASE__INST1_SEG4 0 827 #define VCN_BASE__INST1_SEG5 0 828 829 #define VCN_BASE__INST2_SEG0 0 830 #define VCN_BASE__INST2_SEG1 0 831 #define VCN_BASE__INST2_SEG2 0 832 #define VCN_BASE__INST2_SEG3 0 833 #define VCN_BASE__INST2_SEG4 0 834 #define VCN_BASE__INST2_SEG5 0 835 836 #define VCN_BASE__INST3_SEG0 0 837 #define VCN_BASE__INST3_SEG1 0 838 #define VCN_BASE__INST3_SEG2 0 839 #define VCN_BASE__INST3_SEG3 0 840 #define VCN_BASE__INST3_SEG4 0 841 #define VCN_BASE__INST3_SEG5 0 842 843 #define VCN_BASE__INST4_SEG0 0 844 #define VCN_BASE__INST4_SEG1 0 845 #define VCN_BASE__INST4_SEG2 0 846 #define VCN_BASE__INST4_SEG3 0 847 #define VCN_BASE__INST4_SEG4 0 848 #define VCN_BASE__INST4_SEG5 0 849 850 #define VCN_BASE__INST5_SEG0 0 851 #define VCN_BASE__INST5_SEG1 0 852 #define VCN_BASE__INST5_SEG2 0 853 #define VCN_BASE__INST5_SEG3 0 854 #define VCN_BASE__INST5_SEG4 0 855 #define VCN_BASE__INST5_SEG5 0 856 857 #endif 858
Indexes created Sat Sep 20 22:09:52 GMT 2025