1 /* $NetBSD: navi14_ip_offset.h,v 1.2 2021/12/18 23:45:08 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _navi14_ip_offset_HEADER 24 #define _navi14_ip_offset_HEADER 25 26 #define MAX_INSTANCE 7 27 #define MAX_SEGMENT 5 28 29 30 struct IP_BASE_INSTANCE 31 { 32 unsigned int segment[MAX_SEGMENT]; 33 }; 34 35 struct IP_BASE 36 { 37 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 38 }; 39 40 41 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } }, 42 { { 0, 0, 0, 0, 0 } }, 43 { { 0, 0, 0, 0, 0 } }, 44 { { 0, 0, 0, 0, 0 } }, 45 { { 0, 0, 0, 0, 0 } }, 46 { { 0, 0, 0, 0, 0 } }, 47 { { 0, 0, 0, 0, 0 } } } }; 48 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, 49 { { 0x00016E00, 0x02401C00, 0, 0, 0 } }, 50 { { 0x00017000, 0x02402000, 0, 0, 0 } }, 51 { { 0x00017200, 0x02402400, 0, 0, 0 } }, 52 { { 0x0001B000, 0x0242D800, 0, 0, 0 } }, 53 { { 0x00017E00, 0x0240BC00, 0, 0, 0 } }, 54 { { 0, 0, 0, 0, 0 } } } }; 55 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, 56 { { 0, 0, 0, 0, 0 } }, 57 { { 0, 0, 0, 0, 0 } }, 58 { { 0, 0, 0, 0, 0 } }, 59 { { 0, 0, 0, 0, 0 } }, 60 { { 0, 0, 0, 0, 0 } }, 61 { { 0, 0, 0, 0, 0 } } } }; 62 static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } }, 63 { { 0, 0, 0, 0, 0 } }, 64 { { 0, 0, 0, 0, 0 } }, 65 { { 0, 0, 0, 0, 0 } }, 66 { { 0, 0, 0, 0, 0 } }, 67 { { 0, 0, 0, 0, 0 } }, 68 { { 0, 0, 0, 0, 0 } } } }; 69 static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, 70 { { 0, 0, 0, 0, 0 } }, 71 { { 0, 0, 0, 0, 0 } }, 72 { { 0, 0, 0, 0, 0 } }, 73 { { 0, 0, 0, 0, 0 } }, 74 { { 0, 0, 0, 0, 0 } }, 75 { { 0, 0, 0, 0, 0 } } } }; 76 static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, 77 { { 0, 0, 0, 0, 0 } }, 78 { { 0, 0, 0, 0, 0 } }, 79 { { 0, 0, 0, 0, 0 } }, 80 { { 0, 0, 0, 0, 0 } }, 81 { { 0, 0, 0, 0, 0 } }, 82 { { 0, 0, 0, 0, 0 } } } }; 83 static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } }, 84 { { 0, 0, 0, 0, 0 } }, 85 { { 0, 0, 0, 0, 0 } }, 86 { { 0, 0, 0, 0, 0 } }, 87 { { 0, 0, 0, 0, 0 } }, 88 { { 0, 0, 0, 0, 0 } }, 89 { { 0, 0, 0, 0, 0 } } } }; 90 static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, 91 { { 0, 0, 0, 0, 0 } }, 92 { { 0, 0, 0, 0, 0 } }, 93 { { 0, 0, 0, 0, 0 } }, 94 { { 0, 0, 0, 0, 0 } }, 95 { { 0, 0, 0, 0, 0 } }, 96 { { 0, 0, 0, 0, 0 } } } }; 97 static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } }, 98 { { 0, 0, 0, 0, 0 } }, 99 { { 0, 0, 0, 0, 0 } }, 100 { { 0, 0, 0, 0, 0 } }, 101 { { 0, 0, 0, 0, 0 } }, 102 { { 0, 0, 0, 0, 0 } }, 103 { { 0, 0, 0, 0, 0 } } } }; 104 static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } }, 105 { { 0, 0, 0, 0, 0 } }, 106 { { 0, 0, 0, 0, 0 } }, 107 { { 0, 0, 0, 0, 0 } }, 108 { { 0, 0, 0, 0, 0 } }, 109 { { 0, 0, 0, 0, 0 } }, 110 { { 0, 0, 0, 0, 0 } } } }; 111 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0 } }, 115 { { 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0 } } } }; 118 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, 119 { { 0, 0, 0, 0, 0 } }, 120 { { 0, 0, 0, 0, 0 } }, 121 { { 0, 0, 0, 0, 0 } }, 122 { { 0, 0, 0, 0, 0 } }, 123 { { 0, 0, 0, 0, 0 } }, 124 { { 0, 0, 0, 0, 0 } } } }; 125 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, 126 { { 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0 } } } }; 132 static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, 133 { { 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0 } }, 135 { { 0, 0, 0, 0, 0 } }, 136 { { 0, 0, 0, 0, 0 } }, 137 { { 0, 0, 0, 0, 0 } }, 138 { { 0, 0, 0, 0, 0 } } } }; 139 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, 140 { { 0, 0, 0, 0, 0 } }, 141 { { 0, 0, 0, 0, 0 } }, 142 { { 0, 0, 0, 0, 0 } }, 143 { { 0, 0, 0, 0, 0 } }, 144 { { 0, 0, 0, 0, 0 } }, 145 { { 0, 0, 0, 0, 0 } } } }; 146 static const struct IP_BASE PCIE0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, 147 { { 0, 0, 0, 0, 0 } }, 148 { { 0, 0, 0, 0, 0 } }, 149 { { 0, 0, 0, 0, 0 } }, 150 { { 0, 0, 0, 0, 0 } }, 151 { { 0, 0, 0, 0, 0 } }, 152 { { 0, 0, 0, 0, 0 } } } }; 153 static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, 154 { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, 155 { { 0, 0, 0, 0, 0 } }, 156 { { 0, 0, 0, 0, 0 } }, 157 { { 0, 0, 0, 0, 0 } }, 158 { { 0, 0, 0, 0, 0 } }, 159 { { 0, 0, 0, 0, 0 } } } }; 160 static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } }, 161 { { 0, 0, 0, 0, 0 } }, 162 { { 0, 0, 0, 0, 0 } }, 163 { { 0, 0, 0, 0, 0 } }, 164 { { 0, 0, 0, 0, 0 } }, 165 { { 0, 0, 0, 0, 0 } }, 166 { { 0, 0, 0, 0, 0 } } } }; 167 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, 168 { { 0, 0, 0, 0, 0 } }, 169 { { 0, 0, 0, 0, 0 } }, 170 { { 0, 0, 0, 0, 0 } }, 171 { { 0, 0, 0, 0, 0 } }, 172 { { 0, 0, 0, 0, 0 } }, 173 { { 0, 0, 0, 0, 0 } } } }; 174 static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } }, 175 { { 0x00054000, 0x02425C00, 0, 0, 0 } }, 176 { { 0x00094000, 0x02426000, 0, 0, 0 } }, 177 { { 0x000D4000, 0x02426400, 0, 0, 0 } }, 178 { { 0, 0, 0, 0, 0 } }, 179 { { 0, 0, 0, 0, 0 } }, 180 { { 0, 0, 0, 0, 0 } } } }; 181 static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, 182 { { 0, 0, 0, 0, 0 } }, 183 { { 0, 0, 0, 0, 0 } }, 184 { { 0, 0, 0, 0, 0 } }, 185 { { 0, 0, 0, 0, 0 } }, 186 { { 0, 0, 0, 0, 0 } }, 187 { { 0, 0, 0, 0, 0 } } } }; 188 static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } }, 189 { { 0, 0, 0, 0, 0 } }, 190 { { 0, 0, 0, 0, 0 } }, 191 { { 0, 0, 0, 0, 0 } }, 192 { { 0, 0, 0, 0, 0 } }, 193 { { 0, 0, 0, 0, 0 } }, 194 { { 0, 0, 0, 0, 0 } } } }; 195 196 197 #define ATHUB_BASE__INST0_SEG0 0x00000C00 198 #define ATHUB_BASE__INST0_SEG1 0x02408C00 199 #define ATHUB_BASE__INST0_SEG2 0 200 #define ATHUB_BASE__INST0_SEG3 0 201 #define ATHUB_BASE__INST0_SEG4 0 202 203 #define ATHUB_BASE__INST1_SEG0 0 204 #define ATHUB_BASE__INST1_SEG1 0 205 #define ATHUB_BASE__INST1_SEG2 0 206 #define ATHUB_BASE__INST1_SEG3 0 207 #define ATHUB_BASE__INST1_SEG4 0 208 209 #define ATHUB_BASE__INST2_SEG0 0 210 #define ATHUB_BASE__INST2_SEG1 0 211 #define ATHUB_BASE__INST2_SEG2 0 212 #define ATHUB_BASE__INST2_SEG3 0 213 #define ATHUB_BASE__INST2_SEG4 0 214 215 #define ATHUB_BASE__INST3_SEG0 0 216 #define ATHUB_BASE__INST3_SEG1 0 217 #define ATHUB_BASE__INST3_SEG2 0 218 #define ATHUB_BASE__INST3_SEG3 0 219 #define ATHUB_BASE__INST3_SEG4 0 220 221 #define ATHUB_BASE__INST4_SEG0 0 222 #define ATHUB_BASE__INST4_SEG1 0 223 #define ATHUB_BASE__INST4_SEG2 0 224 #define ATHUB_BASE__INST4_SEG3 0 225 #define ATHUB_BASE__INST4_SEG4 0 226 227 #define ATHUB_BASE__INST5_SEG0 0 228 #define ATHUB_BASE__INST5_SEG1 0 229 #define ATHUB_BASE__INST5_SEG2 0 230 #define ATHUB_BASE__INST5_SEG3 0 231 #define ATHUB_BASE__INST5_SEG4 0 232 233 #define ATHUB_BASE__INST6_SEG0 0 234 #define ATHUB_BASE__INST6_SEG1 0 235 #define ATHUB_BASE__INST6_SEG2 0 236 #define ATHUB_BASE__INST6_SEG3 0 237 #define ATHUB_BASE__INST6_SEG4 0 238 239 #define CLK_BASE__INST0_SEG0 0x00016C00 240 #define CLK_BASE__INST0_SEG1 0x02401800 241 #define CLK_BASE__INST0_SEG2 0 242 #define CLK_BASE__INST0_SEG3 0 243 #define CLK_BASE__INST0_SEG4 0 244 245 #define CLK_BASE__INST1_SEG0 0x00016E00 246 #define CLK_BASE__INST1_SEG1 0x02401C00 247 #define CLK_BASE__INST1_SEG2 0 248 #define CLK_BASE__INST1_SEG3 0 249 #define CLK_BASE__INST1_SEG4 0 250 251 #define CLK_BASE__INST2_SEG0 0x00017000 252 #define CLK_BASE__INST2_SEG1 0x02402000 253 #define CLK_BASE__INST2_SEG2 0 254 #define CLK_BASE__INST2_SEG3 0 255 #define CLK_BASE__INST2_SEG4 0 256 257 #define CLK_BASE__INST3_SEG0 0x00017200 258 #define CLK_BASE__INST3_SEG1 0x02402400 259 #define CLK_BASE__INST3_SEG2 0 260 #define CLK_BASE__INST3_SEG3 0 261 #define CLK_BASE__INST3_SEG4 0 262 263 #define CLK_BASE__INST4_SEG0 0x0001B000 264 #define CLK_BASE__INST4_SEG1 0x0242D800 265 #define CLK_BASE__INST4_SEG2 0 266 #define CLK_BASE__INST4_SEG3 0 267 #define CLK_BASE__INST4_SEG4 0 268 269 #define CLK_BASE__INST5_SEG0 0x00017E00 270 #define CLK_BASE__INST5_SEG1 0x0240BC00 271 #define CLK_BASE__INST5_SEG2 0 272 #define CLK_BASE__INST5_SEG3 0 273 #define CLK_BASE__INST5_SEG4 0 274 275 #define CLK_BASE__INST6_SEG0 0 276 #define CLK_BASE__INST6_SEG1 0 277 #define CLK_BASE__INST6_SEG2 0 278 #define CLK_BASE__INST6_SEG3 0 279 #define CLK_BASE__INST6_SEG4 0 280 281 #define DF_BASE__INST0_SEG0 0x00007000 282 #define DF_BASE__INST0_SEG1 0x0240B800 283 #define DF_BASE__INST0_SEG2 0 284 #define DF_BASE__INST0_SEG3 0 285 #define DF_BASE__INST0_SEG4 0 286 287 #define DF_BASE__INST1_SEG0 0 288 #define DF_BASE__INST1_SEG1 0 289 #define DF_BASE__INST1_SEG2 0 290 #define DF_BASE__INST1_SEG3 0 291 #define DF_BASE__INST1_SEG4 0 292 293 #define DF_BASE__INST2_SEG0 0 294 #define DF_BASE__INST2_SEG1 0 295 #define DF_BASE__INST2_SEG2 0 296 #define DF_BASE__INST2_SEG3 0 297 #define DF_BASE__INST2_SEG4 0 298 299 #define DF_BASE__INST3_SEG0 0 300 #define DF_BASE__INST3_SEG1 0 301 #define DF_BASE__INST3_SEG2 0 302 #define DF_BASE__INST3_SEG3 0 303 #define DF_BASE__INST3_SEG4 0 304 305 #define DF_BASE__INST4_SEG0 0 306 #define DF_BASE__INST4_SEG1 0 307 #define DF_BASE__INST4_SEG2 0 308 #define DF_BASE__INST4_SEG3 0 309 #define DF_BASE__INST4_SEG4 0 310 311 #define DF_BASE__INST5_SEG0 0 312 #define DF_BASE__INST5_SEG1 0 313 #define DF_BASE__INST5_SEG2 0 314 #define DF_BASE__INST5_SEG3 0 315 #define DF_BASE__INST5_SEG4 0 316 317 #define DF_BASE__INST6_SEG0 0 318 #define DF_BASE__INST6_SEG1 0 319 #define DF_BASE__INST6_SEG2 0 320 #define DF_BASE__INST6_SEG3 0 321 #define DF_BASE__INST6_SEG4 0 322 323 #define DIO_BASE__INST0_SEG0 0x02404000 324 #define DIO_BASE__INST0_SEG1 0 325 #define DIO_BASE__INST0_SEG2 0 326 #define DIO_BASE__INST0_SEG3 0 327 #define DIO_BASE__INST0_SEG4 0 328 329 #define DIO_BASE__INST1_SEG0 0 330 #define DIO_BASE__INST1_SEG1 0 331 #define DIO_BASE__INST1_SEG2 0 332 #define DIO_BASE__INST1_SEG3 0 333 #define DIO_BASE__INST1_SEG4 0 334 335 #define DIO_BASE__INST2_SEG0 0 336 #define DIO_BASE__INST2_SEG1 0 337 #define DIO_BASE__INST2_SEG2 0 338 #define DIO_BASE__INST2_SEG3 0 339 #define DIO_BASE__INST2_SEG4 0 340 341 #define DIO_BASE__INST3_SEG0 0 342 #define DIO_BASE__INST3_SEG1 0 343 #define DIO_BASE__INST3_SEG2 0 344 #define DIO_BASE__INST3_SEG3 0 345 #define DIO_BASE__INST3_SEG4 0 346 347 #define DIO_BASE__INST4_SEG0 0 348 #define DIO_BASE__INST4_SEG1 0 349 #define DIO_BASE__INST4_SEG2 0 350 #define DIO_BASE__INST4_SEG3 0 351 #define DIO_BASE__INST4_SEG4 0 352 353 #define DIO_BASE__INST5_SEG0 0 354 #define DIO_BASE__INST5_SEG1 0 355 #define DIO_BASE__INST5_SEG2 0 356 #define DIO_BASE__INST5_SEG3 0 357 #define DIO_BASE__INST5_SEG4 0 358 359 #define DIO_BASE__INST6_SEG0 0 360 #define DIO_BASE__INST6_SEG1 0 361 #define DIO_BASE__INST6_SEG2 0 362 #define DIO_BASE__INST6_SEG3 0 363 #define DIO_BASE__INST6_SEG4 0 364 365 #define DMU_BASE__INST0_SEG0 0x00000012 366 #define DMU_BASE__INST0_SEG1 0x000000C0 367 #define DMU_BASE__INST0_SEG2 0x000034C0 368 #define DMU_BASE__INST0_SEG3 0x00009000 369 #define DMU_BASE__INST0_SEG4 0x02403C00 370 371 #define DMU_BASE__INST1_SEG0 0 372 #define DMU_BASE__INST1_SEG1 0 373 #define DMU_BASE__INST1_SEG2 0 374 #define DMU_BASE__INST1_SEG3 0 375 #define DMU_BASE__INST1_SEG4 0 376 377 #define DMU_BASE__INST2_SEG0 0 378 #define DMU_BASE__INST2_SEG1 0 379 #define DMU_BASE__INST2_SEG2 0 380 #define DMU_BASE__INST2_SEG3 0 381 #define DMU_BASE__INST2_SEG4 0 382 383 #define DMU_BASE__INST3_SEG0 0 384 #define DMU_BASE__INST3_SEG1 0 385 #define DMU_BASE__INST3_SEG2 0 386 #define DMU_BASE__INST3_SEG3 0 387 #define DMU_BASE__INST3_SEG4 0 388 389 #define DMU_BASE__INST4_SEG0 0 390 #define DMU_BASE__INST4_SEG1 0 391 #define DMU_BASE__INST4_SEG2 0 392 #define DMU_BASE__INST4_SEG3 0 393 #define DMU_BASE__INST4_SEG4 0 394 395 #define DMU_BASE__INST5_SEG0 0 396 #define DMU_BASE__INST5_SEG1 0 397 #define DMU_BASE__INST5_SEG2 0 398 #define DMU_BASE__INST5_SEG3 0 399 #define DMU_BASE__INST5_SEG4 0 400 401 #define DMU_BASE__INST6_SEG0 0 402 #define DMU_BASE__INST6_SEG1 0 403 #define DMU_BASE__INST6_SEG2 0 404 #define DMU_BASE__INST6_SEG3 0 405 #define DMU_BASE__INST6_SEG4 0 406 407 #define DPCS_BASE__INST0_SEG0 0x00000012 408 #define DPCS_BASE__INST0_SEG1 0x000000C0 409 #define DPCS_BASE__INST0_SEG2 0x000034C0 410 #define DPCS_BASE__INST0_SEG3 0x00009000 411 #define DPCS_BASE__INST0_SEG4 0x02403C00 412 413 #define DPCS_BASE__INST1_SEG0 0 414 #define DPCS_BASE__INST1_SEG1 0 415 #define DPCS_BASE__INST1_SEG2 0 416 #define DPCS_BASE__INST1_SEG3 0 417 #define DPCS_BASE__INST1_SEG4 0 418 419 #define DPCS_BASE__INST2_SEG0 0 420 #define DPCS_BASE__INST2_SEG1 0 421 #define DPCS_BASE__INST2_SEG2 0 422 #define DPCS_BASE__INST2_SEG3 0 423 #define DPCS_BASE__INST2_SEG4 0 424 425 #define DPCS_BASE__INST3_SEG0 0 426 #define DPCS_BASE__INST3_SEG1 0 427 #define DPCS_BASE__INST3_SEG2 0 428 #define DPCS_BASE__INST3_SEG3 0 429 #define DPCS_BASE__INST3_SEG4 0 430 431 #define DPCS_BASE__INST4_SEG0 0 432 #define DPCS_BASE__INST4_SEG1 0 433 #define DPCS_BASE__INST4_SEG2 0 434 #define DPCS_BASE__INST4_SEG3 0 435 #define DPCS_BASE__INST4_SEG4 0 436 437 #define DPCS_BASE__INST5_SEG0 0 438 #define DPCS_BASE__INST5_SEG1 0 439 #define DPCS_BASE__INST5_SEG2 0 440 #define DPCS_BASE__INST5_SEG3 0 441 #define DPCS_BASE__INST5_SEG4 0 442 443 #define DPCS_BASE__INST6_SEG0 0 444 #define DPCS_BASE__INST6_SEG1 0 445 #define DPCS_BASE__INST6_SEG2 0 446 #define DPCS_BASE__INST6_SEG3 0 447 #define DPCS_BASE__INST6_SEG4 0 448 449 #define FUSE_BASE__INST0_SEG0 0x00017400 450 #define FUSE_BASE__INST0_SEG1 0x02401400 451 #define FUSE_BASE__INST0_SEG2 0 452 #define FUSE_BASE__INST0_SEG3 0 453 #define FUSE_BASE__INST0_SEG4 0 454 455 #define FUSE_BASE__INST1_SEG0 0 456 #define FUSE_BASE__INST1_SEG1 0 457 #define FUSE_BASE__INST1_SEG2 0 458 #define FUSE_BASE__INST1_SEG3 0 459 #define FUSE_BASE__INST1_SEG4 0 460 461 #define FUSE_BASE__INST2_SEG0 0 462 #define FUSE_BASE__INST2_SEG1 0 463 #define FUSE_BASE__INST2_SEG2 0 464 #define FUSE_BASE__INST2_SEG3 0 465 #define FUSE_BASE__INST2_SEG4 0 466 467 #define FUSE_BASE__INST3_SEG0 0 468 #define FUSE_BASE__INST3_SEG1 0 469 #define FUSE_BASE__INST3_SEG2 0 470 #define FUSE_BASE__INST3_SEG3 0 471 #define FUSE_BASE__INST3_SEG4 0 472 473 #define FUSE_BASE__INST4_SEG0 0 474 #define FUSE_BASE__INST4_SEG1 0 475 #define FUSE_BASE__INST4_SEG2 0 476 #define FUSE_BASE__INST4_SEG3 0 477 #define FUSE_BASE__INST4_SEG4 0 478 479 #define FUSE_BASE__INST5_SEG0 0 480 #define FUSE_BASE__INST5_SEG1 0 481 #define FUSE_BASE__INST5_SEG2 0 482 #define FUSE_BASE__INST5_SEG3 0 483 #define FUSE_BASE__INST5_SEG4 0 484 485 #define FUSE_BASE__INST6_SEG0 0 486 #define FUSE_BASE__INST6_SEG1 0 487 #define FUSE_BASE__INST6_SEG2 0 488 #define FUSE_BASE__INST6_SEG3 0 489 #define FUSE_BASE__INST6_SEG4 0 490 491 #define GC_BASE__INST0_SEG0 0x00001260 492 #define GC_BASE__INST0_SEG1 0x0000A000 493 #define GC_BASE__INST0_SEG2 0x02402C00 494 #define GC_BASE__INST0_SEG3 0 495 #define GC_BASE__INST0_SEG4 0 496 497 #define GC_BASE__INST1_SEG0 0 498 #define GC_BASE__INST1_SEG1 0 499 #define GC_BASE__INST1_SEG2 0 500 #define GC_BASE__INST1_SEG3 0 501 #define GC_BASE__INST1_SEG4 0 502 503 #define GC_BASE__INST2_SEG0 0 504 #define GC_BASE__INST2_SEG1 0 505 #define GC_BASE__INST2_SEG2 0 506 #define GC_BASE__INST2_SEG3 0 507 #define GC_BASE__INST2_SEG4 0 508 509 #define GC_BASE__INST3_SEG0 0 510 #define GC_BASE__INST3_SEG1 0 511 #define GC_BASE__INST3_SEG2 0 512 #define GC_BASE__INST3_SEG3 0 513 #define GC_BASE__INST3_SEG4 0 514 515 #define GC_BASE__INST4_SEG0 0 516 #define GC_BASE__INST4_SEG1 0 517 #define GC_BASE__INST4_SEG2 0 518 #define GC_BASE__INST4_SEG3 0 519 #define GC_BASE__INST4_SEG4 0 520 521 #define GC_BASE__INST5_SEG0 0 522 #define GC_BASE__INST5_SEG1 0 523 #define GC_BASE__INST5_SEG2 0 524 #define GC_BASE__INST5_SEG3 0 525 #define GC_BASE__INST5_SEG4 0 526 527 #define GC_BASE__INST6_SEG0 0 528 #define GC_BASE__INST6_SEG1 0 529 #define GC_BASE__INST6_SEG2 0 530 #define GC_BASE__INST6_SEG3 0 531 #define GC_BASE__INST6_SEG4 0 532 533 #define HDA_BASE__INST0_SEG0 0x004C0000 534 #define HDA_BASE__INST0_SEG1 0x02404800 535 #define HDA_BASE__INST0_SEG2 0 536 #define HDA_BASE__INST0_SEG3 0 537 #define HDA_BASE__INST0_SEG4 0 538 539 #define HDA_BASE__INST1_SEG0 0 540 #define HDA_BASE__INST1_SEG1 0 541 #define HDA_BASE__INST1_SEG2 0 542 #define HDA_BASE__INST1_SEG3 0 543 #define HDA_BASE__INST1_SEG4 0 544 545 #define HDA_BASE__INST2_SEG0 0 546 #define HDA_BASE__INST2_SEG1 0 547 #define HDA_BASE__INST2_SEG2 0 548 #define HDA_BASE__INST2_SEG3 0 549 #define HDA_BASE__INST2_SEG4 0 550 551 #define HDA_BASE__INST3_SEG0 0 552 #define HDA_BASE__INST3_SEG1 0 553 #define HDA_BASE__INST3_SEG2 0 554 #define HDA_BASE__INST3_SEG3 0 555 #define HDA_BASE__INST3_SEG4 0 556 557 #define HDA_BASE__INST4_SEG0 0 558 #define HDA_BASE__INST4_SEG1 0 559 #define HDA_BASE__INST4_SEG2 0 560 #define HDA_BASE__INST4_SEG3 0 561 #define HDA_BASE__INST4_SEG4 0 562 563 #define HDA_BASE__INST5_SEG0 0 564 #define HDA_BASE__INST5_SEG1 0 565 #define HDA_BASE__INST5_SEG2 0 566 #define HDA_BASE__INST5_SEG3 0 567 #define HDA_BASE__INST5_SEG4 0 568 569 #define HDA_BASE__INST6_SEG0 0 570 #define HDA_BASE__INST6_SEG1 0 571 #define HDA_BASE__INST6_SEG2 0 572 #define HDA_BASE__INST6_SEG3 0 573 #define HDA_BASE__INST6_SEG4 0 574 575 #define HDP_BASE__INST0_SEG0 0x00000F20 576 #define HDP_BASE__INST0_SEG1 0x0240A400 577 #define HDP_BASE__INST0_SEG2 0 578 #define HDP_BASE__INST0_SEG3 0 579 #define HDP_BASE__INST0_SEG4 0 580 581 #define HDP_BASE__INST1_SEG0 0 582 #define HDP_BASE__INST1_SEG1 0 583 #define HDP_BASE__INST1_SEG2 0 584 #define HDP_BASE__INST1_SEG3 0 585 #define HDP_BASE__INST1_SEG4 0 586 587 #define HDP_BASE__INST2_SEG0 0 588 #define HDP_BASE__INST2_SEG1 0 589 #define HDP_BASE__INST2_SEG2 0 590 #define HDP_BASE__INST2_SEG3 0 591 #define HDP_BASE__INST2_SEG4 0 592 593 #define HDP_BASE__INST3_SEG0 0 594 #define HDP_BASE__INST3_SEG1 0 595 #define HDP_BASE__INST3_SEG2 0 596 #define HDP_BASE__INST3_SEG3 0 597 #define HDP_BASE__INST3_SEG4 0 598 599 #define HDP_BASE__INST4_SEG0 0 600 #define HDP_BASE__INST4_SEG1 0 601 #define HDP_BASE__INST4_SEG2 0 602 #define HDP_BASE__INST4_SEG3 0 603 #define HDP_BASE__INST4_SEG4 0 604 605 #define HDP_BASE__INST5_SEG0 0 606 #define HDP_BASE__INST5_SEG1 0 607 #define HDP_BASE__INST5_SEG2 0 608 #define HDP_BASE__INST5_SEG3 0 609 #define HDP_BASE__INST5_SEG4 0 610 611 #define HDP_BASE__INST6_SEG0 0 612 #define HDP_BASE__INST6_SEG1 0 613 #define HDP_BASE__INST6_SEG2 0 614 #define HDP_BASE__INST6_SEG3 0 615 #define HDP_BASE__INST6_SEG4 0 616 617 #define MMHUB_BASE__INST0_SEG0 0x0001A000 618 #define MMHUB_BASE__INST0_SEG1 0x02408800 619 #define MMHUB_BASE__INST0_SEG2 0 620 #define MMHUB_BASE__INST0_SEG3 0 621 #define MMHUB_BASE__INST0_SEG4 0 622 623 #define MMHUB_BASE__INST1_SEG0 0 624 #define MMHUB_BASE__INST1_SEG1 0 625 #define MMHUB_BASE__INST1_SEG2 0 626 #define MMHUB_BASE__INST1_SEG3 0 627 #define MMHUB_BASE__INST1_SEG4 0 628 629 #define MMHUB_BASE__INST2_SEG0 0 630 #define MMHUB_BASE__INST2_SEG1 0 631 #define MMHUB_BASE__INST2_SEG2 0 632 #define MMHUB_BASE__INST2_SEG3 0 633 #define MMHUB_BASE__INST2_SEG4 0 634 635 #define MMHUB_BASE__INST3_SEG0 0 636 #define MMHUB_BASE__INST3_SEG1 0 637 #define MMHUB_BASE__INST3_SEG2 0 638 #define MMHUB_BASE__INST3_SEG3 0 639 #define MMHUB_BASE__INST3_SEG4 0 640 641 #define MMHUB_BASE__INST4_SEG0 0 642 #define MMHUB_BASE__INST4_SEG1 0 643 #define MMHUB_BASE__INST4_SEG2 0 644 #define MMHUB_BASE__INST4_SEG3 0 645 #define MMHUB_BASE__INST4_SEG4 0 646 647 #define MMHUB_BASE__INST5_SEG0 0 648 #define MMHUB_BASE__INST5_SEG1 0 649 #define MMHUB_BASE__INST5_SEG2 0 650 #define MMHUB_BASE__INST5_SEG3 0 651 #define MMHUB_BASE__INST5_SEG4 0 652 653 #define MMHUB_BASE__INST6_SEG0 0 654 #define MMHUB_BASE__INST6_SEG1 0 655 #define MMHUB_BASE__INST6_SEG2 0 656 #define MMHUB_BASE__INST6_SEG3 0 657 #define MMHUB_BASE__INST6_SEG4 0 658 659 #define MP0_BASE__INST0_SEG0 0x00016000 660 #define MP0_BASE__INST0_SEG1 0x00DC0000 661 #define MP0_BASE__INST0_SEG2 0x00E00000 662 #define MP0_BASE__INST0_SEG3 0x00E40000 663 #define MP0_BASE__INST0_SEG4 0x0243FC00 664 665 #define MP0_BASE__INST1_SEG0 0 666 #define MP0_BASE__INST1_SEG1 0 667 #define MP0_BASE__INST1_SEG2 0 668 #define MP0_BASE__INST1_SEG3 0 669 #define MP0_BASE__INST1_SEG4 0 670 671 #define MP0_BASE__INST2_SEG0 0 672 #define MP0_BASE__INST2_SEG1 0 673 #define MP0_BASE__INST2_SEG2 0 674 #define MP0_BASE__INST2_SEG3 0 675 #define MP0_BASE__INST2_SEG4 0 676 677 #define MP0_BASE__INST3_SEG0 0 678 #define MP0_BASE__INST3_SEG1 0 679 #define MP0_BASE__INST3_SEG2 0 680 #define MP0_BASE__INST3_SEG3 0 681 #define MP0_BASE__INST3_SEG4 0 682 683 #define MP0_BASE__INST4_SEG0 0 684 #define MP0_BASE__INST4_SEG1 0 685 #define MP0_BASE__INST4_SEG2 0 686 #define MP0_BASE__INST4_SEG3 0 687 #define MP0_BASE__INST4_SEG4 0 688 689 #define MP0_BASE__INST5_SEG0 0 690 #define MP0_BASE__INST5_SEG1 0 691 #define MP0_BASE__INST5_SEG2 0 692 #define MP0_BASE__INST5_SEG3 0 693 #define MP0_BASE__INST5_SEG4 0 694 695 #define MP0_BASE__INST6_SEG0 0 696 #define MP0_BASE__INST6_SEG1 0 697 #define MP0_BASE__INST6_SEG2 0 698 #define MP0_BASE__INST6_SEG3 0 699 #define MP0_BASE__INST6_SEG4 0 700 701 #define MP1_BASE__INST0_SEG0 0x00016000 702 #define MP1_BASE__INST0_SEG1 0x00DC0000 703 #define MP1_BASE__INST0_SEG2 0x00E00000 704 #define MP1_BASE__INST0_SEG3 0x00E40000 705 #define MP1_BASE__INST0_SEG4 0x0243FC00 706 707 #define MP1_BASE__INST1_SEG0 0 708 #define MP1_BASE__INST1_SEG1 0 709 #define MP1_BASE__INST1_SEG2 0 710 #define MP1_BASE__INST1_SEG3 0 711 #define MP1_BASE__INST1_SEG4 0 712 713 #define MP1_BASE__INST2_SEG0 0 714 #define MP1_BASE__INST2_SEG1 0 715 #define MP1_BASE__INST2_SEG2 0 716 #define MP1_BASE__INST2_SEG3 0 717 #define MP1_BASE__INST2_SEG4 0 718 719 #define MP1_BASE__INST3_SEG0 0 720 #define MP1_BASE__INST3_SEG1 0 721 #define MP1_BASE__INST3_SEG2 0 722 #define MP1_BASE__INST3_SEG3 0 723 #define MP1_BASE__INST3_SEG4 0 724 725 #define MP1_BASE__INST4_SEG0 0 726 #define MP1_BASE__INST4_SEG1 0 727 #define MP1_BASE__INST4_SEG2 0 728 #define MP1_BASE__INST4_SEG3 0 729 #define MP1_BASE__INST4_SEG4 0 730 731 #define MP1_BASE__INST5_SEG0 0 732 #define MP1_BASE__INST5_SEG1 0 733 #define MP1_BASE__INST5_SEG2 0 734 #define MP1_BASE__INST5_SEG3 0 735 #define MP1_BASE__INST5_SEG4 0 736 737 #define MP1_BASE__INST6_SEG0 0 738 #define MP1_BASE__INST6_SEG1 0 739 #define MP1_BASE__INST6_SEG2 0 740 #define MP1_BASE__INST6_SEG3 0 741 #define MP1_BASE__INST6_SEG4 0 742 743 #define NBIF0_BASE__INST0_SEG0 0x00000000 744 #define NBIF0_BASE__INST0_SEG1 0x00000014 745 #define NBIF0_BASE__INST0_SEG2 0x00000D20 746 #define NBIF0_BASE__INST0_SEG3 0x00010400 747 #define NBIF0_BASE__INST0_SEG4 0x0241B000 748 749 #define NBIF0_BASE__INST1_SEG0 0 750 #define NBIF0_BASE__INST1_SEG1 0 751 #define NBIF0_BASE__INST1_SEG2 0 752 #define NBIF0_BASE__INST1_SEG3 0 753 #define NBIF0_BASE__INST1_SEG4 0 754 755 #define NBIF0_BASE__INST2_SEG0 0 756 #define NBIF0_BASE__INST2_SEG1 0 757 #define NBIF0_BASE__INST2_SEG2 0 758 #define NBIF0_BASE__INST2_SEG3 0 759 #define NBIF0_BASE__INST2_SEG4 0 760 761 #define NBIF0_BASE__INST3_SEG0 0 762 #define NBIF0_BASE__INST3_SEG1 0 763 #define NBIF0_BASE__INST3_SEG2 0 764 #define NBIF0_BASE__INST3_SEG3 0 765 #define NBIF0_BASE__INST3_SEG4 0 766 767 #define NBIF0_BASE__INST4_SEG0 0 768 #define NBIF0_BASE__INST4_SEG1 0 769 #define NBIF0_BASE__INST4_SEG2 0 770 #define NBIF0_BASE__INST4_SEG3 0 771 #define NBIF0_BASE__INST4_SEG4 0 772 773 #define NBIF0_BASE__INST5_SEG0 0 774 #define NBIF0_BASE__INST5_SEG1 0 775 #define NBIF0_BASE__INST5_SEG2 0 776 #define NBIF0_BASE__INST5_SEG3 0 777 #define NBIF0_BASE__INST5_SEG4 0 778 779 #define NBIF0_BASE__INST6_SEG0 0 780 #define NBIF0_BASE__INST6_SEG1 0 781 #define NBIF0_BASE__INST6_SEG2 0 782 #define NBIF0_BASE__INST6_SEG3 0 783 #define NBIF0_BASE__INST6_SEG4 0 784 785 #define OSSSYS_BASE__INST0_SEG0 0x000010A0 786 #define OSSSYS_BASE__INST0_SEG1 0x0240A000 787 #define OSSSYS_BASE__INST0_SEG2 0 788 #define OSSSYS_BASE__INST0_SEG3 0 789 #define OSSSYS_BASE__INST0_SEG4 0 790 791 #define OSSSYS_BASE__INST1_SEG0 0 792 #define OSSSYS_BASE__INST1_SEG1 0 793 #define OSSSYS_BASE__INST1_SEG2 0 794 #define OSSSYS_BASE__INST1_SEG3 0 795 #define OSSSYS_BASE__INST1_SEG4 0 796 797 #define OSSSYS_BASE__INST2_SEG0 0 798 #define OSSSYS_BASE__INST2_SEG1 0 799 #define OSSSYS_BASE__INST2_SEG2 0 800 #define OSSSYS_BASE__INST2_SEG3 0 801 #define OSSSYS_BASE__INST2_SEG4 0 802 803 #define OSSSYS_BASE__INST3_SEG0 0 804 #define OSSSYS_BASE__INST3_SEG1 0 805 #define OSSSYS_BASE__INST3_SEG2 0 806 #define OSSSYS_BASE__INST3_SEG3 0 807 #define OSSSYS_BASE__INST3_SEG4 0 808 809 #define OSSSYS_BASE__INST4_SEG0 0 810 #define OSSSYS_BASE__INST4_SEG1 0 811 #define OSSSYS_BASE__INST4_SEG2 0 812 #define OSSSYS_BASE__INST4_SEG3 0 813 #define OSSSYS_BASE__INST4_SEG4 0 814 815 #define OSSSYS_BASE__INST5_SEG0 0 816 #define OSSSYS_BASE__INST5_SEG1 0 817 #define OSSSYS_BASE__INST5_SEG2 0 818 #define OSSSYS_BASE__INST5_SEG3 0 819 #define OSSSYS_BASE__INST5_SEG4 0 820 821 #define OSSSYS_BASE__INST6_SEG0 0 822 #define OSSSYS_BASE__INST6_SEG1 0 823 #define OSSSYS_BASE__INST6_SEG2 0 824 #define OSSSYS_BASE__INST6_SEG3 0 825 #define OSSSYS_BASE__INST6_SEG4 0 826 827 #define PCIE0_BASE__INST0_SEG0 0x00000000 828 #define PCIE0_BASE__INST0_SEG1 0x00000014 829 #define PCIE0_BASE__INST0_SEG2 0x00000D20 830 #define PCIE0_BASE__INST0_SEG3 0x00010400 831 #define PCIE0_BASE__INST0_SEG4 0x0241B000 832 833 #define PCIE0_BASE__INST1_SEG0 0 834 #define PCIE0_BASE__INST1_SEG1 0 835 #define PCIE0_BASE__INST1_SEG2 0 836 #define PCIE0_BASE__INST1_SEG3 0 837 #define PCIE0_BASE__INST1_SEG4 0 838 839 #define PCIE0_BASE__INST2_SEG0 0 840 #define PCIE0_BASE__INST2_SEG1 0 841 #define PCIE0_BASE__INST2_SEG2 0 842 #define PCIE0_BASE__INST2_SEG3 0 843 #define PCIE0_BASE__INST2_SEG4 0 844 845 #define PCIE0_BASE__INST3_SEG0 0 846 #define PCIE0_BASE__INST3_SEG1 0 847 #define PCIE0_BASE__INST3_SEG2 0 848 #define PCIE0_BASE__INST3_SEG3 0 849 #define PCIE0_BASE__INST3_SEG4 0 850 851 #define PCIE0_BASE__INST4_SEG0 0 852 #define PCIE0_BASE__INST4_SEG1 0 853 #define PCIE0_BASE__INST4_SEG2 0 854 #define PCIE0_BASE__INST4_SEG3 0 855 #define PCIE0_BASE__INST4_SEG4 0 856 857 #define PCIE0_BASE__INST5_SEG0 0 858 #define PCIE0_BASE__INST5_SEG1 0 859 #define PCIE0_BASE__INST5_SEG2 0 860 #define PCIE0_BASE__INST5_SEG3 0 861 #define PCIE0_BASE__INST5_SEG4 0 862 863 #define PCIE0_BASE__INST6_SEG0 0 864 #define PCIE0_BASE__INST6_SEG1 0 865 #define PCIE0_BASE__INST6_SEG2 0 866 #define PCIE0_BASE__INST6_SEG3 0 867 #define PCIE0_BASE__INST6_SEG4 0 868 869 #define SDMA_BASE__INST0_SEG0 0x00001260 870 #define SDMA_BASE__INST0_SEG1 0x0000A000 871 #define SDMA_BASE__INST0_SEG2 0x02402C00 872 #define SDMA_BASE__INST0_SEG3 0 873 #define SDMA_BASE__INST0_SEG4 0 874 875 #define SDMA_BASE__INST1_SEG0 0x00001260 876 #define SDMA_BASE__INST1_SEG1 0x0000A000 877 #define SDMA_BASE__INST1_SEG2 0x02402C00 878 #define SDMA_BASE__INST1_SEG3 0 879 #define SDMA_BASE__INST1_SEG4 0 880 881 #define SDMA_BASE__INST2_SEG0 0 882 #define SDMA_BASE__INST2_SEG1 0 883 #define SDMA_BASE__INST2_SEG2 0 884 #define SDMA_BASE__INST2_SEG3 0 885 #define SDMA_BASE__INST2_SEG4 0 886 887 #define SDMA_BASE__INST3_SEG0 0 888 #define SDMA_BASE__INST3_SEG1 0 889 #define SDMA_BASE__INST3_SEG2 0 890 #define SDMA_BASE__INST3_SEG3 0 891 #define SDMA_BASE__INST3_SEG4 0 892 893 #define SDMA_BASE__INST4_SEG0 0 894 #define SDMA_BASE__INST4_SEG1 0 895 #define SDMA_BASE__INST4_SEG2 0 896 #define SDMA_BASE__INST4_SEG3 0 897 #define SDMA_BASE__INST4_SEG4 0 898 899 #define SDMA_BASE__INST5_SEG0 0 900 #define SDMA_BASE__INST5_SEG1 0 901 #define SDMA_BASE__INST5_SEG2 0 902 #define SDMA_BASE__INST5_SEG3 0 903 #define SDMA_BASE__INST5_SEG4 0 904 905 #define SDMA_BASE__INST6_SEG0 0 906 #define SDMA_BASE__INST6_SEG1 0 907 #define SDMA_BASE__INST6_SEG2 0 908 #define SDMA_BASE__INST6_SEG3 0 909 #define SDMA_BASE__INST6_SEG4 0 910 911 #define SMUIO_BASE__INST0_SEG0 0x00016800 912 #define SMUIO_BASE__INST0_SEG1 0x00016A00 913 #define SMUIO_BASE__INST0_SEG2 0x00440000 914 #define SMUIO_BASE__INST0_SEG3 0x02401000 915 #define SMUIO_BASE__INST0_SEG4 0 916 917 #define SMUIO_BASE__INST1_SEG0 0 918 #define SMUIO_BASE__INST1_SEG1 0 919 #define SMUIO_BASE__INST1_SEG2 0 920 #define SMUIO_BASE__INST1_SEG3 0 921 #define SMUIO_BASE__INST1_SEG4 0 922 923 #define SMUIO_BASE__INST2_SEG0 0 924 #define SMUIO_BASE__INST2_SEG1 0 925 #define SMUIO_BASE__INST2_SEG2 0 926 #define SMUIO_BASE__INST2_SEG3 0 927 #define SMUIO_BASE__INST2_SEG4 0 928 929 #define SMUIO_BASE__INST3_SEG0 0 930 #define SMUIO_BASE__INST3_SEG1 0 931 #define SMUIO_BASE__INST3_SEG2 0 932 #define SMUIO_BASE__INST3_SEG3 0 933 #define SMUIO_BASE__INST3_SEG4 0 934 935 #define SMUIO_BASE__INST4_SEG0 0 936 #define SMUIO_BASE__INST4_SEG1 0 937 #define SMUIO_BASE__INST4_SEG2 0 938 #define SMUIO_BASE__INST4_SEG3 0 939 #define SMUIO_BASE__INST4_SEG4 0 940 941 #define SMUIO_BASE__INST5_SEG0 0 942 #define SMUIO_BASE__INST5_SEG1 0 943 #define SMUIO_BASE__INST5_SEG2 0 944 #define SMUIO_BASE__INST5_SEG3 0 945 #define SMUIO_BASE__INST5_SEG4 0 946 947 #define SMUIO_BASE__INST6_SEG0 0 948 #define SMUIO_BASE__INST6_SEG1 0 949 #define SMUIO_BASE__INST6_SEG2 0 950 #define SMUIO_BASE__INST6_SEG3 0 951 #define SMUIO_BASE__INST6_SEG4 0 952 953 #define THM_BASE__INST0_SEG0 0x00016600 954 #define THM_BASE__INST0_SEG1 0x02400C00 955 #define THM_BASE__INST0_SEG2 0 956 #define THM_BASE__INST0_SEG3 0 957 #define THM_BASE__INST0_SEG4 0 958 959 #define THM_BASE__INST1_SEG0 0 960 #define THM_BASE__INST1_SEG1 0 961 #define THM_BASE__INST1_SEG2 0 962 #define THM_BASE__INST1_SEG3 0 963 #define THM_BASE__INST1_SEG4 0 964 965 #define THM_BASE__INST2_SEG0 0 966 #define THM_BASE__INST2_SEG1 0 967 #define THM_BASE__INST2_SEG2 0 968 #define THM_BASE__INST2_SEG3 0 969 #define THM_BASE__INST2_SEG4 0 970 971 #define THM_BASE__INST3_SEG0 0 972 #define THM_BASE__INST3_SEG1 0 973 #define THM_BASE__INST3_SEG2 0 974 #define THM_BASE__INST3_SEG3 0 975 #define THM_BASE__INST3_SEG4 0 976 977 #define THM_BASE__INST4_SEG0 0 978 #define THM_BASE__INST4_SEG1 0 979 #define THM_BASE__INST4_SEG2 0 980 #define THM_BASE__INST4_SEG3 0 981 #define THM_BASE__INST4_SEG4 0 982 983 #define THM_BASE__INST5_SEG0 0 984 #define THM_BASE__INST5_SEG1 0 985 #define THM_BASE__INST5_SEG2 0 986 #define THM_BASE__INST5_SEG3 0 987 #define THM_BASE__INST5_SEG4 0 988 989 #define THM_BASE__INST6_SEG0 0 990 #define THM_BASE__INST6_SEG1 0 991 #define THM_BASE__INST6_SEG2 0 992 #define THM_BASE__INST6_SEG3 0 993 #define THM_BASE__INST6_SEG4 0 994 995 #define UMC_BASE__INST0_SEG0 0x00014000 996 #define UMC_BASE__INST0_SEG1 0x02425800 997 #define UMC_BASE__INST0_SEG2 0 998 #define UMC_BASE__INST0_SEG3 0 999 #define UMC_BASE__INST0_SEG4 0 1000 1001 #define UMC_BASE__INST1_SEG0 0x00054000 1002 #define UMC_BASE__INST1_SEG1 0x02425C00 1003 #define UMC_BASE__INST1_SEG2 0 1004 #define UMC_BASE__INST1_SEG3 0 1005 #define UMC_BASE__INST1_SEG4 0 1006 1007 #define UMC_BASE__INST2_SEG0 0x00094000 1008 #define UMC_BASE__INST2_SEG1 0x02426000 1009 #define UMC_BASE__INST2_SEG2 0 1010 #define UMC_BASE__INST2_SEG3 0 1011 #define UMC_BASE__INST2_SEG4 0 1012 1013 #define UMC_BASE__INST3_SEG0 0x000D4000 1014 #define UMC_BASE__INST3_SEG1 0x02426400 1015 #define UMC_BASE__INST3_SEG2 0 1016 #define UMC_BASE__INST3_SEG3 0 1017 #define UMC_BASE__INST3_SEG4 0 1018 1019 #define UMC_BASE__INST4_SEG0 0 1020 #define UMC_BASE__INST4_SEG1 0 1021 #define UMC_BASE__INST4_SEG2 0 1022 #define UMC_BASE__INST4_SEG3 0 1023 #define UMC_BASE__INST4_SEG4 0 1024 1025 #define UMC_BASE__INST5_SEG0 0 1026 #define UMC_BASE__INST5_SEG1 0 1027 #define UMC_BASE__INST5_SEG2 0 1028 #define UMC_BASE__INST5_SEG3 0 1029 #define UMC_BASE__INST5_SEG4 0 1030 1031 #define UMC_BASE__INST6_SEG0 0 1032 #define UMC_BASE__INST6_SEG1 0 1033 #define UMC_BASE__INST6_SEG2 0 1034 #define UMC_BASE__INST6_SEG3 0 1035 #define UMC_BASE__INST6_SEG4 0 1036 1037 #define USB0_BASE__INST0_SEG0 0x0242A800 1038 #define USB0_BASE__INST0_SEG1 0x05B00000 1039 #define USB0_BASE__INST0_SEG2 0 1040 #define USB0_BASE__INST0_SEG3 0 1041 #define USB0_BASE__INST0_SEG4 0 1042 1043 #define USB0_BASE__INST1_SEG0 0 1044 #define USB0_BASE__INST1_SEG1 0 1045 #define USB0_BASE__INST1_SEG2 0 1046 #define USB0_BASE__INST1_SEG3 0 1047 #define USB0_BASE__INST1_SEG4 0 1048 1049 #define USB0_BASE__INST2_SEG0 0 1050 #define USB0_BASE__INST2_SEG1 0 1051 #define USB0_BASE__INST2_SEG2 0 1052 #define USB0_BASE__INST2_SEG3 0 1053 #define USB0_BASE__INST2_SEG4 0 1054 1055 #define USB0_BASE__INST3_SEG0 0 1056 #define USB0_BASE__INST3_SEG1 0 1057 #define USB0_BASE__INST3_SEG2 0 1058 #define USB0_BASE__INST3_SEG3 0 1059 #define USB0_BASE__INST3_SEG4 0 1060 1061 #define USB0_BASE__INST4_SEG0 0 1062 #define USB0_BASE__INST4_SEG1 0 1063 #define USB0_BASE__INST4_SEG2 0 1064 #define USB0_BASE__INST4_SEG3 0 1065 #define USB0_BASE__INST4_SEG4 0 1066 1067 #define USB0_BASE__INST5_SEG0 0 1068 #define USB0_BASE__INST5_SEG1 0 1069 #define USB0_BASE__INST5_SEG2 0 1070 #define USB0_BASE__INST5_SEG3 0 1071 #define USB0_BASE__INST5_SEG4 0 1072 1073 #define USB0_BASE__INST6_SEG0 0 1074 #define USB0_BASE__INST6_SEG1 0 1075 #define USB0_BASE__INST6_SEG2 0 1076 #define USB0_BASE__INST6_SEG3 0 1077 #define USB0_BASE__INST6_SEG4 0 1078 1079 #define UVD0_BASE__INST0_SEG0 0x00007800 1080 #define UVD0_BASE__INST0_SEG1 0x00007E00 1081 #define UVD0_BASE__INST0_SEG2 0x02403000 1082 #define UVD0_BASE__INST0_SEG3 0 1083 #define UVD0_BASE__INST0_SEG4 0 1084 1085 #define UVD0_BASE__INST1_SEG0 0 1086 #define UVD0_BASE__INST1_SEG1 0 1087 #define UVD0_BASE__INST1_SEG2 0 1088 #define UVD0_BASE__INST1_SEG3 0 1089 #define UVD0_BASE__INST1_SEG4 0 1090 1091 #define UVD0_BASE__INST2_SEG0 0 1092 #define UVD0_BASE__INST2_SEG1 0 1093 #define UVD0_BASE__INST2_SEG2 0 1094 #define UVD0_BASE__INST2_SEG3 0 1095 #define UVD0_BASE__INST2_SEG4 0 1096 1097 #define UVD0_BASE__INST3_SEG0 0 1098 #define UVD0_BASE__INST3_SEG1 0 1099 #define UVD0_BASE__INST3_SEG2 0 1100 #define UVD0_BASE__INST3_SEG3 0 1101 #define UVD0_BASE__INST3_SEG4 0 1102 1103 #define UVD0_BASE__INST4_SEG0 0 1104 #define UVD0_BASE__INST4_SEG1 0 1105 #define UVD0_BASE__INST4_SEG2 0 1106 #define UVD0_BASE__INST4_SEG3 0 1107 #define UVD0_BASE__INST4_SEG4 0 1108 1109 #define UVD0_BASE__INST5_SEG0 0 1110 #define UVD0_BASE__INST5_SEG1 0 1111 #define UVD0_BASE__INST5_SEG2 0 1112 #define UVD0_BASE__INST5_SEG3 0 1113 #define UVD0_BASE__INST5_SEG4 0 1114 1115 #define UVD0_BASE__INST6_SEG0 0 1116 #define UVD0_BASE__INST6_SEG1 0 1117 #define UVD0_BASE__INST6_SEG2 0 1118 #define UVD0_BASE__INST6_SEG3 0 1119 #define UVD0_BASE__INST6_SEG4 0 1120 1121 #endif 1122
Indexes created Sat Sep 20 22:09:52 GMT 2025