pptable.h revision 1.1
1 /* $NetBSD: pptable.h,v 1.1 2018/08/27 01:34:47 riastradh Exp $ */ 2 3 /* 4 * Copyright 2013 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _PPTABLE_H 26 #define _PPTABLE_H 27 28 #pragma pack(1) 29 30 typedef struct _ATOM_PPLIB_THERMALCONTROLLER 31 32 { 33 UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* 34 UCHAR ucI2cLine; // as interpreted by DAL I2C 35 UCHAR ucI2cAddress; 36 UCHAR ucFanParameters; // Fan Control Parameters. 37 UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. 38 UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. 39 UCHAR ucReserved; // ---- 40 UCHAR ucFlags; // to be defined 41 } ATOM_PPLIB_THERMALCONTROLLER; 42 43 #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f 44 #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. 45 46 #define ATOM_PP_THERMALCONTROLLER_NONE 0 47 #define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib 48 #define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib 49 #define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib 50 #define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib 51 #define ATOM_PP_THERMALCONTROLLER_LM64 5 52 #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib 53 #define ATOM_PP_THERMALCONTROLLER_RV6xx 7 54 #define ATOM_PP_THERMALCONTROLLER_RV770 8 55 #define ATOM_PP_THERMALCONTROLLER_ADT7473 9 56 #define ATOM_PP_THERMALCONTROLLER_KONG 10 57 #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 58 #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 59 #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. 60 #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally 61 #define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 62 #define ATOM_PP_THERMALCONTROLLER_SISLANDS 16 63 #define ATOM_PP_THERMALCONTROLLER_LM96163 17 64 #define ATOM_PP_THERMALCONTROLLER_CISLANDS 18 65 #define ATOM_PP_THERMALCONTROLLER_KAVERI 19 66 67 68 // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. 69 // We probably should reserve the bit 0x80 for this use. 70 // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). 71 // The driver can pick the correct internal controller based on the ASIC. 72 73 #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller 74 #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller 75 76 typedef struct _ATOM_PPLIB_STATE 77 { 78 UCHAR ucNonClockStateIndex; 79 UCHAR ucClockStateIndices[1]; // variable-sized 80 } ATOM_PPLIB_STATE; 81 82 83 typedef struct _ATOM_PPLIB_FANTABLE 84 { 85 UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. 86 UCHAR ucTHyst; // Temperature hysteresis. Integer. 87 USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. 88 USHORT usTMed; // The middle temperature where we change slopes. 89 USHORT usTHigh; // The high point above TMed for adjusting the second slope. 90 USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). 91 USHORT usPWMMed; // The PWM value (in percent) at TMed. 92 USHORT usPWMHigh; // The PWM value at THigh. 93 } ATOM_PPLIB_FANTABLE; 94 95 typedef struct _ATOM_PPLIB_FANTABLE2 96 { 97 ATOM_PPLIB_FANTABLE basicTable; 98 USHORT usTMax; // The max temperature 99 } ATOM_PPLIB_FANTABLE2; 100 101 typedef struct _ATOM_PPLIB_FANTABLE3 102 { 103 ATOM_PPLIB_FANTABLE2 basicTable2; 104 UCHAR ucFanControlMode; 105 USHORT usFanPWMMax; 106 USHORT usFanOutputSensitivity; 107 } ATOM_PPLIB_FANTABLE3; 108 109 typedef struct _ATOM_PPLIB_EXTENDEDHEADER 110 { 111 USHORT usSize; 112 ULONG ulMaxEngineClock; // For Overdrive. 113 ULONG ulMaxMemoryClock; // For Overdrive. 114 // Add extra system parameters here, always adjust size to include all fields. 115 USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table 116 USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table 117 USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table 118 USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table 119 USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table 120 /* points to ATOM_PPLIB_POWERTUNE_Table */ 121 USHORT usPowerTuneTableOffset; 122 /* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */ 123 USHORT usSclkVddgfxTableOffset; 124 } ATOM_PPLIB_EXTENDEDHEADER; 125 126 //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps 127 #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 128 #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 129 #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 130 #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 131 #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 132 #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 133 #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 134 #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 135 #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 136 #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 137 #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 138 #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 139 #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 140 #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. 141 #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). 142 #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. 143 #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. 144 #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. 145 #define ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE 0x00040000 // Does the driver supports new CAC voltage table. 146 #define ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY 0x00080000 // Does the driver supports revert GPIO5 polarity. 147 #define ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17 0x00100000 // Does the driver supports thermal2GPIO17. 148 #define ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE 0x00200000 // Does the driver supports VR HOT GPIO Configurable. 149 #define ATOM_PP_PLATFORM_CAP_TEMP_INVERSION 0x00400000 // Does the driver supports Temp Inversion feature. 150 #define ATOM_PP_PLATFORM_CAP_EVV 0x00800000 151 #define ATOM_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL 0x01000000 152 #define ATOM_PP_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE 0x02000000 153 #define ATOM_PP_PLATFORM_CAP_DISABLE_USING_ACTUAL_TEMPERATURE_FOR_POWER_CALC 0x04000000 154 155 typedef struct _ATOM_PPLIB_POWERPLAYTABLE 156 { 157 ATOM_COMMON_TABLE_HEADER sHeader; 158 159 UCHAR ucDataRevision; 160 161 UCHAR ucNumStates; 162 UCHAR ucStateEntrySize; 163 UCHAR ucClockInfoSize; 164 UCHAR ucNonClockSize; 165 166 // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures 167 USHORT usStateArrayOffset; 168 169 // offset from start of this table to array of ASIC-specific structures, 170 // currently ATOM_PPLIB_CLOCK_INFO. 171 USHORT usClockInfoArrayOffset; 172 173 // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO 174 USHORT usNonClockInfoArrayOffset; 175 176 USHORT usBackbiasTime; // in microseconds 177 USHORT usVoltageTime; // in microseconds 178 USHORT usTableSize; //the size of this structure, or the extended structure 179 180 ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* 181 182 ATOM_PPLIB_THERMALCONTROLLER sThermalController; 183 184 USHORT usBootClockInfoOffset; 185 USHORT usBootNonClockInfoOffset; 186 187 } ATOM_PPLIB_POWERPLAYTABLE; 188 189 typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 190 { 191 ATOM_PPLIB_POWERPLAYTABLE basicTable; 192 UCHAR ucNumCustomThermalPolicy; 193 USHORT usCustomThermalPolicyArrayOffset; 194 }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; 195 196 typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 197 { 198 ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; 199 USHORT usFormatID; // To be used ONLY by PPGen. 200 USHORT usFanTableOffset; 201 USHORT usExtendendedHeaderOffset; 202 } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; 203 204 typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 205 { 206 ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; 207 ULONG ulGoldenPPID; // PPGen use only 208 ULONG ulGoldenRevision; // PPGen use only 209 USHORT usVddcDependencyOnSCLKOffset; 210 USHORT usVddciDependencyOnMCLKOffset; 211 USHORT usVddcDependencyOnMCLKOffset; 212 USHORT usMaxClockVoltageOnDCOffset; 213 USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table 214 USHORT usMvddDependencyOnMCLKOffset; 215 } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; 216 217 typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 218 { 219 ATOM_PPLIB_POWERPLAYTABLE4 basicTable4; 220 ULONG ulTDPLimit; 221 ULONG ulNearTDPLimit; 222 ULONG ulSQRampingThreshold; 223 USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table 224 ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table 225 USHORT usTDPODLimit; 226 USHORT usLoadLineSlope; // in milliOhms * 100 227 } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; 228 229 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification 230 #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 231 #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 232 #define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 233 #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 234 #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 235 #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 236 // 2, 4, 6, 7 are reserved 237 238 #define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 239 #define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 240 #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 241 #define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 242 #define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 243 #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 244 #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 245 #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 246 #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 247 #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 248 #define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 249 #define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 250 #define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 251 252 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 253 #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 254 #define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 255 #define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View Codec (BD-3D) 256 257 //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings 258 #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 259 #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 260 261 // 0 is 2.5Gb/s, 1 is 5Gb/s 262 #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 263 #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 264 265 // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec 266 #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 267 #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 268 269 // lookup into reduced refresh-rate table 270 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 271 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 272 273 #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 274 #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 275 // 2-15 TBD as needed. 276 277 #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 278 #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 279 280 #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 281 282 #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 283 284 //memory related flags 285 #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 286 287 //M3 Arb //2bits, current 3 sets of parameters in total 288 #define ATOM_PPLIB_M3ARB_MASK 0x00060000 289 #define ATOM_PPLIB_M3ARB_SHIFT 17 290 291 #define ATOM_PPLIB_ENABLE_DRR 0x00080000 292 293 // remaining 16 bits are reserved 294 typedef struct _ATOM_PPLIB_THERMAL_STATE 295 { 296 UCHAR ucMinTemperature; 297 UCHAR ucMaxTemperature; 298 UCHAR ucThermalAction; 299 }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE; 300 301 // Contained in an array starting at the offset 302 // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. 303 // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex 304 #define ATOM_PPLIB_NONCLOCKINFO_VER1 12 305 #define ATOM_PPLIB_NONCLOCKINFO_VER2 24 306 typedef struct _ATOM_PPLIB_NONCLOCK_INFO 307 { 308 USHORT usClassification; 309 UCHAR ucMinTemperature; 310 UCHAR ucMaxTemperature; 311 ULONG ulCapsAndSettings; 312 UCHAR ucRequiredPower; 313 USHORT usClassification2; 314 ULONG ulVCLK; 315 ULONG ulDCLK; 316 UCHAR ucUnused[5]; 317 } ATOM_PPLIB_NONCLOCK_INFO; 318 319 // Contained in an array starting at the offset 320 // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. 321 // referenced from ATOM_PPLIB_STATE::ucClockStateIndices 322 typedef struct _ATOM_PPLIB_R600_CLOCK_INFO 323 { 324 USHORT usEngineClockLow; 325 UCHAR ucEngineClockHigh; 326 327 USHORT usMemoryClockLow; 328 UCHAR ucMemoryClockHigh; 329 330 USHORT usVDDC; 331 USHORT usUnused1; 332 USHORT usUnused2; 333 334 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 335 336 } ATOM_PPLIB_R600_CLOCK_INFO; 337 338 // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO 339 #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 340 #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 341 #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 342 #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 343 #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 344 #define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). 345 346 typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO 347 348 { 349 USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). 350 UCHAR ucLowEngineClockHigh; 351 USHORT usHighEngineClockLow; // High Engine clock in MHz. 352 UCHAR ucHighEngineClockHigh; 353 USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. 354 UCHAR ucMemoryClockHigh; // Currentyl unused. 355 UCHAR ucPadding; // For proper alignment and size. 356 USHORT usVDDC; // For the 780, use: None, Low, High, Variable 357 UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} 358 UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could 359 USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). 360 ULONG ulFlags; 361 } ATOM_PPLIB_RS780_CLOCK_INFO; 362 363 #define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 364 #define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 365 #define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 366 #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 367 368 #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. 369 #define ATOM_PPLIB_RS780_SPMCLK_LOW 1 370 #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 371 372 #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 373 #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 374 #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 375 376 typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO 377 { 378 USHORT usEngineClockLow; 379 UCHAR ucEngineClockHigh; 380 381 USHORT usMemoryClockLow; 382 UCHAR ucMemoryClockHigh; 383 384 USHORT usVDDC; 385 USHORT usVDDCI; 386 USHORT usUnused; 387 388 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 389 390 } ATOM_PPLIB_EVERGREEN_CLOCK_INFO; 391 392 typedef struct _ATOM_PPLIB_SI_CLOCK_INFO 393 { 394 USHORT usEngineClockLow; 395 UCHAR ucEngineClockHigh; 396 397 USHORT usMemoryClockLow; 398 UCHAR ucMemoryClockHigh; 399 400 USHORT usVDDC; 401 USHORT usVDDCI; 402 UCHAR ucPCIEGen; 403 UCHAR ucUnused1; 404 405 ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now 406 407 } ATOM_PPLIB_SI_CLOCK_INFO; 408 409 typedef struct _ATOM_PPLIB_CI_CLOCK_INFO 410 { 411 USHORT usEngineClockLow; 412 UCHAR ucEngineClockHigh; 413 414 USHORT usMemoryClockLow; 415 UCHAR ucMemoryClockHigh; 416 417 UCHAR ucPCIEGen; 418 USHORT usPCIELane; 419 } ATOM_PPLIB_CI_CLOCK_INFO; 420 421 typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ 422 USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz 423 UCHAR ucEngineClockHigh; //clockfrequency >> 16. 424 UCHAR vddcIndex; //2-bit vddc index; 425 USHORT tdpLimit; 426 //please initalize to 0 427 USHORT rsv1; 428 //please initialize to 0s 429 ULONG rsv2[2]; 430 }ATOM_PPLIB_SUMO_CLOCK_INFO; 431 432 typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO { 433 UCHAR index; 434 UCHAR rsv[3]; 435 } ATOM_PPLIB_CZ_CLOCK_INFO; 436 437 typedef struct _ATOM_PPLIB_STATE_V2 438 { 439 //number of valid dpm levels in this state; Driver uses it to calculate the whole 440 //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) 441 UCHAR ucNumDPMLevels; 442 443 //a index to the array of nonClockInfos 444 UCHAR nonClockInfoIndex; 445 /** 446 * Driver will read the first ucNumDPMLevels in this array 447 */ 448 UCHAR clockInfoIndex[1]; 449 } ATOM_PPLIB_STATE_V2; 450 451 typedef struct _StateArray{ 452 //how many states we have 453 UCHAR ucNumEntries; 454 455 ATOM_PPLIB_STATE_V2 states[1]; 456 }StateArray; 457 458 459 typedef struct _ClockInfoArray{ 460 //how many clock levels we have 461 UCHAR ucNumEntries; 462 463 //sizeof(ATOM_PPLIB_CLOCK_INFO) 464 UCHAR ucEntrySize; 465 466 UCHAR clockInfo[1]; 467 }ClockInfoArray; 468 469 typedef struct _NonClockInfoArray{ 470 471 //how many non-clock levels we have. normally should be same as number of states 472 UCHAR ucNumEntries; 473 //sizeof(ATOM_PPLIB_NONCLOCK_INFO) 474 UCHAR ucEntrySize; 475 476 ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; 477 }NonClockInfoArray; 478 479 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record 480 { 481 USHORT usClockLow; 482 UCHAR ucClockHigh; 483 USHORT usVoltage; 484 }ATOM_PPLIB_Clock_Voltage_Dependency_Record; 485 486 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table 487 { 488 UCHAR ucNumEntries; // Number of entries. 489 ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries. 490 }ATOM_PPLIB_Clock_Voltage_Dependency_Table; 491 492 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record 493 { 494 USHORT usSclkLow; 495 UCHAR ucSclkHigh; 496 USHORT usMclkLow; 497 UCHAR ucMclkHigh; 498 USHORT usVddc; 499 USHORT usVddci; 500 }ATOM_PPLIB_Clock_Voltage_Limit_Record; 501 502 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table 503 { 504 UCHAR ucNumEntries; // Number of entries. 505 ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. 506 }ATOM_PPLIB_Clock_Voltage_Limit_Table; 507 508 union _ATOM_PPLIB_CAC_Leakage_Record 509 { 510 struct 511 { 512 USHORT usVddc; // We use this field for the "fake" standardized VDDC for power calculations; For CI and newer, we use this as the real VDDC value. in CI we read it as StdVoltageHiSidd 513 ULONG ulLeakageValue; // For CI and newer we use this as the "fake" standar VDDC value. in CI we read it as StdVoltageLoSidd 514 515 }; 516 struct 517 { 518 USHORT usVddc1; 519 USHORT usVddc2; 520 USHORT usVddc3; 521 }; 522 }; 523 524 typedef union _ATOM_PPLIB_CAC_Leakage_Record ATOM_PPLIB_CAC_Leakage_Record; 525 526 typedef struct _ATOM_PPLIB_CAC_Leakage_Table 527 { 528 UCHAR ucNumEntries; // Number of entries. 529 ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries. 530 }ATOM_PPLIB_CAC_Leakage_Table; 531 532 typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record 533 { 534 USHORT usVoltage; 535 USHORT usSclkLow; 536 UCHAR ucSclkHigh; 537 USHORT usMclkLow; 538 UCHAR ucMclkHigh; 539 }ATOM_PPLIB_PhaseSheddingLimits_Record; 540 541 typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table 542 { 543 UCHAR ucNumEntries; // Number of entries. 544 ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries. 545 }ATOM_PPLIB_PhaseSheddingLimits_Table; 546 547 typedef struct _VCEClockInfo{ 548 USHORT usEVClkLow; 549 UCHAR ucEVClkHigh; 550 USHORT usECClkLow; 551 UCHAR ucECClkHigh; 552 }VCEClockInfo; 553 554 typedef struct _VCEClockInfoArray{ 555 UCHAR ucNumEntries; 556 VCEClockInfo entries[1]; 557 }VCEClockInfoArray; 558 559 typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record 560 { 561 USHORT usVoltage; 562 UCHAR ucVCEClockInfoIndex; 563 }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record; 564 565 typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table 566 { 567 UCHAR numEntries; 568 ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1]; 569 }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table; 570 571 typedef struct _ATOM_PPLIB_VCE_State_Record 572 { 573 UCHAR ucVCEClockInfoIndex; 574 UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary 575 }ATOM_PPLIB_VCE_State_Record; 576 577 typedef struct _ATOM_PPLIB_VCE_State_Table 578 { 579 UCHAR numEntries; 580 ATOM_PPLIB_VCE_State_Record entries[1]; 581 }ATOM_PPLIB_VCE_State_Table; 582 583 584 typedef struct _ATOM_PPLIB_VCE_Table 585 { 586 UCHAR revid; 587 // VCEClockInfoArray array; 588 // ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits; 589 // ATOM_PPLIB_VCE_State_Table states; 590 }ATOM_PPLIB_VCE_Table; 591 592 593 typedef struct _UVDClockInfo{ 594 USHORT usVClkLow; 595 UCHAR ucVClkHigh; 596 USHORT usDClkLow; 597 UCHAR ucDClkHigh; 598 }UVDClockInfo; 599 600 typedef struct _UVDClockInfoArray{ 601 UCHAR ucNumEntries; 602 UVDClockInfo entries[1]; 603 }UVDClockInfoArray; 604 605 typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record 606 { 607 USHORT usVoltage; 608 UCHAR ucUVDClockInfoIndex; 609 }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record; 610 611 typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table 612 { 613 UCHAR numEntries; 614 ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1]; 615 }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table; 616 617 typedef struct _ATOM_PPLIB_UVD_Table 618 { 619 UCHAR revid; 620 // UVDClockInfoArray array; 621 // ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits; 622 }ATOM_PPLIB_UVD_Table; 623 624 typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Record 625 { 626 USHORT usVoltage; 627 USHORT usSAMClockLow; 628 UCHAR ucSAMClockHigh; 629 }ATOM_PPLIB_SAMClk_Voltage_Limit_Record; 630 631 typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Table{ 632 UCHAR numEntries; 633 ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[1]; 634 }ATOM_PPLIB_SAMClk_Voltage_Limit_Table; 635 636 typedef struct _ATOM_PPLIB_SAMU_Table 637 { 638 UCHAR revid; 639 ATOM_PPLIB_SAMClk_Voltage_Limit_Table limits; 640 }ATOM_PPLIB_SAMU_Table; 641 642 typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Record 643 { 644 USHORT usVoltage; 645 USHORT usACPClockLow; 646 UCHAR ucACPClockHigh; 647 }ATOM_PPLIB_ACPClk_Voltage_Limit_Record; 648 649 typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Table{ 650 UCHAR numEntries; 651 ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[1]; 652 }ATOM_PPLIB_ACPClk_Voltage_Limit_Table; 653 654 typedef struct _ATOM_PPLIB_ACP_Table 655 { 656 UCHAR revid; 657 ATOM_PPLIB_ACPClk_Voltage_Limit_Table limits; 658 }ATOM_PPLIB_ACP_Table; 659 660 typedef struct _ATOM_PowerTune_Table{ 661 USHORT usTDP; 662 USHORT usConfigurableTDP; 663 USHORT usTDC; 664 USHORT usBatteryPowerLimit; 665 USHORT usSmallPowerLimit; 666 USHORT usLowCACLeakage; 667 USHORT usHighCACLeakage; 668 }ATOM_PowerTune_Table; 669 670 typedef struct _ATOM_PPLIB_POWERTUNE_Table 671 { 672 UCHAR revid; 673 ATOM_PowerTune_Table power_tune_table; 674 }ATOM_PPLIB_POWERTUNE_Table; 675 676 typedef struct _ATOM_PPLIB_POWERTUNE_Table_V1 677 { 678 UCHAR revid; 679 ATOM_PowerTune_Table power_tune_table; 680 USHORT usMaximumPowerDeliveryLimit; 681 USHORT usTjMax; 682 USHORT usReserve[6]; 683 } ATOM_PPLIB_POWERTUNE_Table_V1; 684 685 #define ATOM_PPM_A_A 1 686 #define ATOM_PPM_A_I 2 687 typedef struct _ATOM_PPLIB_PPM_Table 688 { 689 UCHAR ucRevId; 690 UCHAR ucPpmDesign; //A+I or A+A 691 USHORT usCpuCoreNumber; 692 ULONG ulPlatformTDP; 693 ULONG ulSmallACPlatformTDP; 694 ULONG ulPlatformTDC; 695 ULONG ulSmallACPlatformTDC; 696 ULONG ulApuTDP; 697 ULONG ulDGpuTDP; 698 ULONG ulDGpuUlvPower; 699 ULONG ulTjmax; 700 } ATOM_PPLIB_PPM_Table; 701 702 #pragma pack() 703 704 #endif 705
Indexes created Fri Oct 03 17:10:05 GMT 2025