1 /* $NetBSD: renoir_ip_offset.h,v 1.2 2021/12/18 23:45:08 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _renoir_ip_offset_HEADER 24 #define _renoir_ip_offset_HEADER 25 26 #define MAX_INSTANCE 7 27 #define MAX_SEGMENT 5 28 29 30 struct IP_BASE_INSTANCE 31 { 32 unsigned int segment[MAX_SEGMENT]; 33 }; 34 35 struct IP_BASE 36 { 37 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 38 }; 39 40 41 static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0, 0, 0 } }, 42 { { 0, 0, 0, 0, 0 } }, 43 { { 0, 0, 0, 0, 0 } }, 44 { { 0, 0, 0, 0, 0 } }, 45 { { 0, 0, 0, 0, 0 } }, 46 { { 0, 0, 0, 0, 0 } }, 47 { { 0, 0, 0, 0, 0 } } } }; 48 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } }, 49 { { 0, 0, 0, 0, 0 } }, 50 { { 0, 0, 0, 0, 0 } }, 51 { { 0, 0, 0, 0, 0 } }, 52 { { 0, 0, 0, 0, 0 } }, 53 { { 0, 0, 0, 0, 0 } }, 54 { { 0, 0, 0, 0, 0 } } } }; 55 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } }, 56 { { 0, 0, 0, 0, 0 } }, 57 { { 0, 0, 0, 0, 0 } }, 58 { { 0, 0, 0, 0, 0 } }, 59 { { 0, 0, 0, 0, 0 } }, 60 { { 0, 0, 0, 0, 0 } }, 61 { { 0, 0, 0, 0, 0 } } } }; 62 static const struct IP_BASE DBGU_IO0_BASE ={ { { { 0x000001E0, 0x0240B400, 0, 0, 0 } }, 63 { { 0, 0, 0, 0, 0 } }, 64 { { 0, 0, 0, 0, 0 } }, 65 { { 0, 0, 0, 0, 0 } }, 66 { { 0, 0, 0, 0, 0 } }, 67 { { 0, 0, 0, 0, 0 } }, 68 { { 0, 0, 0, 0, 0 } } } }; 69 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, 70 { { 0, 0, 0, 0, 0 } }, 71 { { 0, 0, 0, 0, 0 } }, 72 { { 0, 0, 0, 0, 0 } }, 73 { { 0, 0, 0, 0, 0 } }, 74 { { 0, 0, 0, 0, 0 } }, 75 { { 0, 0, 0, 0, 0 } } } }; 76 static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } }, 77 { { 0, 0, 0, 0, 0 } }, 78 { { 0, 0, 0, 0, 0 } }, 79 { { 0, 0, 0, 0, 0 } }, 80 { { 0, 0, 0, 0, 0 } }, 81 { { 0, 0, 0, 0, 0 } }, 82 { { 0, 0, 0, 0, 0 } } } }; 83 static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, 84 { { 0, 0, 0, 0, 0 } }, 85 { { 0, 0, 0, 0, 0 } }, 86 { { 0, 0, 0, 0, 0 } }, 87 { { 0, 0, 0, 0, 0 } }, 88 { { 0, 0, 0, 0, 0 } }, 89 { { 0, 0, 0, 0, 0 } } } }; 90 static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, 91 { { 0, 0, 0, 0, 0 } }, 92 { { 0, 0, 0, 0, 0 } }, 93 { { 0, 0, 0, 0, 0 } }, 94 { { 0, 0, 0, 0, 0 } }, 95 { { 0, 0, 0, 0, 0 } }, 96 { { 0, 0, 0, 0, 0 } } } }; 97 static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } }, 98 { { 0, 0, 0, 0, 0 } }, 99 { { 0, 0, 0, 0, 0 } }, 100 { { 0, 0, 0, 0, 0 } }, 101 { { 0, 0, 0, 0, 0 } }, 102 { { 0, 0, 0, 0, 0 } }, 103 { { 0, 0, 0, 0, 0 } } } }; 104 static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0 } }, 105 { { 0, 0, 0, 0, 0 } }, 106 { { 0, 0, 0, 0, 0 } }, 107 { { 0, 0, 0, 0, 0 } }, 108 { { 0, 0, 0, 0, 0 } }, 109 { { 0, 0, 0, 0, 0 } }, 110 { { 0, 0, 0, 0, 0 } } } }; 111 static const struct IP_BASE HDA_BASE ={ { { { 0x02404800, 0x004C0000, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0 } }, 115 { { 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0 } } } }; 118 static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } }, 119 { { 0, 0, 0, 0, 0 } }, 120 { { 0, 0, 0, 0, 0 } }, 121 { { 0, 0, 0, 0, 0 } }, 122 { { 0, 0, 0, 0, 0 } }, 123 { { 0, 0, 0, 0, 0 } }, 124 { { 0, 0, 0, 0, 0 } } } }; 125 static const struct IP_BASE IOHC0_BASE ={ { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0 } }, 126 { { 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0 } } } }; 132 static const struct IP_BASE ISP_BASE ={ { { { 0x00018000, 0x0240B000, 0, 0, 0 } }, 133 { { 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0 } }, 135 { { 0, 0, 0, 0, 0 } }, 136 { { 0, 0, 0, 0, 0 } }, 137 { { 0, 0, 0, 0, 0 } }, 138 { { 0, 0, 0, 0, 0 } } } }; 139 static const struct IP_BASE L2IMU0_BASE ={ { { { 0x00007DC0, 0x02407000, 0x00900000, 0x04FC0000, 0x055C0000 } }, 140 { { 0, 0, 0, 0, 0 } }, 141 { { 0, 0, 0, 0, 0 } }, 142 { { 0, 0, 0, 0, 0 } }, 143 { { 0, 0, 0, 0, 0 } }, 144 { { 0, 0, 0, 0, 0 } }, 145 { { 0, 0, 0, 0, 0 } } } }; 146 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, 147 { { 0, 0, 0, 0, 0 } }, 148 { { 0, 0, 0, 0, 0 } }, 149 { { 0, 0, 0, 0, 0 } }, 150 { { 0, 0, 0, 0, 0 } }, 151 { { 0, 0, 0, 0, 0 } }, 152 { { 0, 0, 0, 0, 0 } } } }; 153 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000 } }, 154 { { 0, 0, 0, 0, 0 } }, 155 { { 0, 0, 0, 0, 0 } }, 156 { { 0, 0, 0, 0, 0 } }, 157 { { 0, 0, 0, 0, 0 } }, 158 { { 0, 0, 0, 0, 0 } }, 159 { { 0, 0, 0, 0, 0 } } } }; 160 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F00000 } }, 161 { { 0, 0, 0, 0, 0 } }, 162 { { 0, 0, 0, 0, 0 } }, 163 { { 0, 0, 0, 0, 0 } }, 164 { { 0, 0, 0, 0, 0 } }, 165 { { 0, 0, 0, 0, 0 } }, 166 { { 0, 0, 0, 0, 0 } } } }; 167 static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, 168 { { 0, 0, 0, 0, 0 } }, 169 { { 0, 0, 0, 0, 0 } }, 170 { { 0, 0, 0, 0, 0 } }, 171 { { 0, 0, 0, 0, 0 } }, 172 { { 0, 0, 0, 0, 0 } }, 173 { { 0, 0, 0, 0, 0 } } } }; 174 static const struct IP_BASE DCN_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, 175 { { 0, 0, 0, 0, 0 } }, 176 { { 0, 0, 0, 0, 0 } }, 177 { { 0, 0, 0, 0, 0 } }, 178 { { 0, 0, 0, 0, 0 } } } }; 179 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, 180 { { 0, 0, 0, 0, 0 } }, 181 { { 0, 0, 0, 0, 0 } }, 182 { { 0, 0, 0, 0, 0 } }, 183 { { 0, 0, 0, 0, 0 } }, 184 { { 0, 0, 0, 0, 0 } }, 185 { { 0, 0, 0, 0, 0 } } } }; 186 static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } }, 187 { { 0, 0, 0, 0, 0 } }, 188 { { 0, 0, 0, 0, 0 } }, 189 { { 0, 0, 0, 0, 0 } }, 190 { { 0, 0, 0, 0, 0 } }, 191 { { 0, 0, 0, 0, 0 } }, 192 { { 0, 0, 0, 0, 0 } } } }; 193 static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x0240A800, 0, 0, 0 } }, 194 { { 0, 0, 0, 0, 0 } }, 195 { { 0, 0, 0, 0, 0 } }, 196 { { 0, 0, 0, 0, 0 } }, 197 { { 0, 0, 0, 0, 0 } }, 198 { { 0, 0, 0, 0, 0 } }, 199 { { 0, 0, 0, 0, 0 } } } }; 200 static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0 } }, 201 { { 0, 0, 0, 0, 0 } }, 202 { { 0, 0, 0, 0, 0 } }, 203 { { 0, 0, 0, 0, 0 } }, 204 { { 0, 0, 0, 0, 0 } }, 205 { { 0, 0, 0, 0, 0 } }, 206 { { 0, 0, 0, 0, 0 } } } }; 207 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, 208 { { 0, 0, 0, 0, 0 } }, 209 { { 0, 0, 0, 0, 0 } }, 210 { { 0, 0, 0, 0, 0 } }, 211 { { 0, 0, 0, 0, 0 } }, 212 { { 0, 0, 0, 0, 0 } }, 213 { { 0, 0, 0, 0, 0 } } } }; 214 static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } }, 215 { { 0x00054000, 0x02425C00, 0, 0, 0 } }, 216 { { 0, 0, 0, 0, 0 } }, 217 { { 0, 0, 0, 0, 0 } }, 218 { { 0, 0, 0, 0, 0 } }, 219 { { 0, 0, 0, 0, 0 } }, 220 { { 0, 0, 0, 0, 0 } } } }; 221 static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, 222 { { 0, 0, 0, 0, 0 } }, 223 { { 0, 0, 0, 0, 0 } }, 224 { { 0, 0, 0, 0, 0 } }, 225 { { 0, 0, 0, 0, 0 } }, 226 { { 0, 0, 0, 0, 0 } }, 227 { { 0, 0, 0, 0, 0 } } } }; 228 static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } }, 229 { { 0, 0, 0, 0, 0 } }, 230 { { 0, 0, 0, 0, 0 } }, 231 { { 0, 0, 0, 0, 0 } }, 232 { { 0, 0, 0, 0, 0 } }, 233 { { 0, 0, 0, 0, 0 } }, 234 { { 0, 0, 0, 0, 0 } } } }; 235 236 237 #define ACP_BASE__INST0_SEG0 0x02403800 238 #define ACP_BASE__INST0_SEG1 0x00480000 239 #define ACP_BASE__INST0_SEG2 0 240 #define ACP_BASE__INST0_SEG3 0 241 #define ACP_BASE__INST0_SEG4 0 242 243 #define ACP_BASE__INST1_SEG0 0 244 #define ACP_BASE__INST1_SEG1 0 245 #define ACP_BASE__INST1_SEG2 0 246 #define ACP_BASE__INST1_SEG3 0 247 #define ACP_BASE__INST1_SEG4 0 248 249 #define ACP_BASE__INST2_SEG0 0 250 #define ACP_BASE__INST2_SEG1 0 251 #define ACP_BASE__INST2_SEG2 0 252 #define ACP_BASE__INST2_SEG3 0 253 #define ACP_BASE__INST2_SEG4 0 254 255 #define ACP_BASE__INST3_SEG0 0 256 #define ACP_BASE__INST3_SEG1 0 257 #define ACP_BASE__INST3_SEG2 0 258 #define ACP_BASE__INST3_SEG3 0 259 #define ACP_BASE__INST3_SEG4 0 260 261 #define ACP_BASE__INST4_SEG0 0 262 #define ACP_BASE__INST4_SEG1 0 263 #define ACP_BASE__INST4_SEG2 0 264 #define ACP_BASE__INST4_SEG3 0 265 #define ACP_BASE__INST4_SEG4 0 266 267 #define ACP_BASE__INST5_SEG0 0 268 #define ACP_BASE__INST5_SEG1 0 269 #define ACP_BASE__INST5_SEG2 0 270 #define ACP_BASE__INST5_SEG3 0 271 #define ACP_BASE__INST5_SEG4 0 272 273 #define ACP_BASE__INST6_SEG0 0 274 #define ACP_BASE__INST6_SEG1 0 275 #define ACP_BASE__INST6_SEG2 0 276 #define ACP_BASE__INST6_SEG3 0 277 #define ACP_BASE__INST6_SEG4 0 278 279 #define ATHUB_BASE__INST0_SEG0 0x00000C20 280 #define ATHUB_BASE__INST0_SEG1 0x02408C00 281 #define ATHUB_BASE__INST0_SEG2 0 282 #define ATHUB_BASE__INST0_SEG3 0 283 #define ATHUB_BASE__INST0_SEG4 0 284 285 #define ATHUB_BASE__INST1_SEG0 0 286 #define ATHUB_BASE__INST1_SEG1 0 287 #define ATHUB_BASE__INST1_SEG2 0 288 #define ATHUB_BASE__INST1_SEG3 0 289 #define ATHUB_BASE__INST1_SEG4 0 290 291 #define ATHUB_BASE__INST2_SEG0 0 292 #define ATHUB_BASE__INST2_SEG1 0 293 #define ATHUB_BASE__INST2_SEG2 0 294 #define ATHUB_BASE__INST2_SEG3 0 295 #define ATHUB_BASE__INST2_SEG4 0 296 297 #define ATHUB_BASE__INST3_SEG0 0 298 #define ATHUB_BASE__INST3_SEG1 0 299 #define ATHUB_BASE__INST3_SEG2 0 300 #define ATHUB_BASE__INST3_SEG3 0 301 #define ATHUB_BASE__INST3_SEG4 0 302 303 #define ATHUB_BASE__INST4_SEG0 0 304 #define ATHUB_BASE__INST4_SEG1 0 305 #define ATHUB_BASE__INST4_SEG2 0 306 #define ATHUB_BASE__INST4_SEG3 0 307 #define ATHUB_BASE__INST4_SEG4 0 308 309 #define ATHUB_BASE__INST5_SEG0 0 310 #define ATHUB_BASE__INST5_SEG1 0 311 #define ATHUB_BASE__INST5_SEG2 0 312 #define ATHUB_BASE__INST5_SEG3 0 313 #define ATHUB_BASE__INST5_SEG4 0 314 315 #define ATHUB_BASE__INST6_SEG0 0 316 #define ATHUB_BASE__INST6_SEG1 0 317 #define ATHUB_BASE__INST6_SEG2 0 318 #define ATHUB_BASE__INST6_SEG3 0 319 #define ATHUB_BASE__INST6_SEG4 0 320 321 #define CLK_BASE__INST0_SEG0 0x00016C00 322 #define CLK_BASE__INST0_SEG1 0x00016E00 323 #define CLK_BASE__INST0_SEG2 0x00017000 324 #define CLK_BASE__INST0_SEG3 0x00017E00 325 #define CLK_BASE__INST0_SEG4 0 326 327 #define CLK_BASE__INST1_SEG0 0 328 #define CLK_BASE__INST1_SEG1 0 329 #define CLK_BASE__INST1_SEG2 0 330 #define CLK_BASE__INST1_SEG3 0 331 #define CLK_BASE__INST1_SEG4 0 332 333 #define CLK_BASE__INST2_SEG0 0 334 #define CLK_BASE__INST2_SEG1 0 335 #define CLK_BASE__INST2_SEG2 0 336 #define CLK_BASE__INST2_SEG3 0 337 #define CLK_BASE__INST2_SEG4 0 338 339 #define CLK_BASE__INST3_SEG0 0 340 #define CLK_BASE__INST3_SEG1 0 341 #define CLK_BASE__INST3_SEG2 0 342 #define CLK_BASE__INST3_SEG3 0 343 #define CLK_BASE__INST3_SEG4 0 344 345 #define CLK_BASE__INST4_SEG0 0 346 #define CLK_BASE__INST4_SEG1 0 347 #define CLK_BASE__INST4_SEG2 0 348 #define CLK_BASE__INST4_SEG3 0 349 #define CLK_BASE__INST4_SEG4 0 350 351 #define CLK_BASE__INST5_SEG0 0 352 #define CLK_BASE__INST5_SEG1 0 353 #define CLK_BASE__INST5_SEG2 0 354 #define CLK_BASE__INST5_SEG3 0 355 #define CLK_BASE__INST5_SEG4 0 356 357 #define CLK_BASE__INST6_SEG0 0 358 #define CLK_BASE__INST6_SEG1 0 359 #define CLK_BASE__INST6_SEG2 0 360 #define CLK_BASE__INST6_SEG3 0 361 #define CLK_BASE__INST6_SEG4 0 362 363 #define DBGU_IO0_BASE__INST0_SEG0 0x000001E0 364 #define DBGU_IO0_BASE__INST0_SEG1 0x0240B400 365 #define DBGU_IO0_BASE__INST0_SEG2 0 366 #define DBGU_IO0_BASE__INST0_SEG3 0 367 #define DBGU_IO0_BASE__INST0_SEG4 0 368 369 #define DBGU_IO0_BASE__INST1_SEG0 0 370 #define DBGU_IO0_BASE__INST1_SEG1 0 371 #define DBGU_IO0_BASE__INST1_SEG2 0 372 #define DBGU_IO0_BASE__INST1_SEG3 0 373 #define DBGU_IO0_BASE__INST1_SEG4 0 374 375 #define DBGU_IO0_BASE__INST2_SEG0 0 376 #define DBGU_IO0_BASE__INST2_SEG1 0 377 #define DBGU_IO0_BASE__INST2_SEG2 0 378 #define DBGU_IO0_BASE__INST2_SEG3 0 379 #define DBGU_IO0_BASE__INST2_SEG4 0 380 381 #define DBGU_IO0_BASE__INST3_SEG0 0 382 #define DBGU_IO0_BASE__INST3_SEG1 0 383 #define DBGU_IO0_BASE__INST3_SEG2 0 384 #define DBGU_IO0_BASE__INST3_SEG3 0 385 #define DBGU_IO0_BASE__INST3_SEG4 0 386 387 #define DBGU_IO0_BASE__INST4_SEG0 0 388 #define DBGU_IO0_BASE__INST4_SEG1 0 389 #define DBGU_IO0_BASE__INST4_SEG2 0 390 #define DBGU_IO0_BASE__INST4_SEG3 0 391 #define DBGU_IO0_BASE__INST4_SEG4 0 392 393 #define DBGU_IO0_BASE__INST5_SEG0 0 394 #define DBGU_IO0_BASE__INST5_SEG1 0 395 #define DBGU_IO0_BASE__INST5_SEG2 0 396 #define DBGU_IO0_BASE__INST5_SEG3 0 397 #define DBGU_IO0_BASE__INST5_SEG4 0 398 399 #define DBGU_IO0_BASE__INST6_SEG0 0 400 #define DBGU_IO0_BASE__INST6_SEG1 0 401 #define DBGU_IO0_BASE__INST6_SEG2 0 402 #define DBGU_IO0_BASE__INST6_SEG3 0 403 #define DBGU_IO0_BASE__INST6_SEG4 0 404 405 #define DF_BASE__INST0_SEG0 0x00007000 406 #define DF_BASE__INST0_SEG1 0x0240B800 407 #define DF_BASE__INST0_SEG2 0 408 #define DF_BASE__INST0_SEG3 0 409 #define DF_BASE__INST0_SEG4 0 410 411 #define DF_BASE__INST1_SEG0 0 412 #define DF_BASE__INST1_SEG1 0 413 #define DF_BASE__INST1_SEG2 0 414 #define DF_BASE__INST1_SEG3 0 415 #define DF_BASE__INST1_SEG4 0 416 417 #define DF_BASE__INST2_SEG0 0 418 #define DF_BASE__INST2_SEG1 0 419 #define DF_BASE__INST2_SEG2 0 420 #define DF_BASE__INST2_SEG3 0 421 #define DF_BASE__INST2_SEG4 0 422 423 #define DF_BASE__INST3_SEG0 0 424 #define DF_BASE__INST3_SEG1 0 425 #define DF_BASE__INST3_SEG2 0 426 #define DF_BASE__INST3_SEG3 0 427 #define DF_BASE__INST3_SEG4 0 428 429 #define DF_BASE__INST4_SEG0 0 430 #define DF_BASE__INST4_SEG1 0 431 #define DF_BASE__INST4_SEG2 0 432 #define DF_BASE__INST4_SEG3 0 433 #define DF_BASE__INST4_SEG4 0 434 435 #define DF_BASE__INST5_SEG0 0 436 #define DF_BASE__INST5_SEG1 0 437 #define DF_BASE__INST5_SEG2 0 438 #define DF_BASE__INST5_SEG3 0 439 #define DF_BASE__INST5_SEG4 0 440 441 #define DF_BASE__INST6_SEG0 0 442 #define DF_BASE__INST6_SEG1 0 443 #define DF_BASE__INST6_SEG2 0 444 #define DF_BASE__INST6_SEG3 0 445 #define DF_BASE__INST6_SEG4 0 446 447 #define DIO_BASE__INST0_SEG0 0x02404000 448 #define DIO_BASE__INST0_SEG1 0 449 #define DIO_BASE__INST0_SEG2 0 450 #define DIO_BASE__INST0_SEG3 0 451 #define DIO_BASE__INST0_SEG4 0 452 453 #define DIO_BASE__INST1_SEG0 0 454 #define DIO_BASE__INST1_SEG1 0 455 #define DIO_BASE__INST1_SEG2 0 456 #define DIO_BASE__INST1_SEG3 0 457 #define DIO_BASE__INST1_SEG4 0 458 459 #define DIO_BASE__INST2_SEG0 0 460 #define DIO_BASE__INST2_SEG1 0 461 #define DIO_BASE__INST2_SEG2 0 462 #define DIO_BASE__INST2_SEG3 0 463 #define DIO_BASE__INST2_SEG4 0 464 465 #define DIO_BASE__INST3_SEG0 0 466 #define DIO_BASE__INST3_SEG1 0 467 #define DIO_BASE__INST3_SEG2 0 468 #define DIO_BASE__INST3_SEG3 0 469 #define DIO_BASE__INST3_SEG4 0 470 471 #define DIO_BASE__INST4_SEG0 0 472 #define DIO_BASE__INST4_SEG1 0 473 #define DIO_BASE__INST4_SEG2 0 474 #define DIO_BASE__INST4_SEG3 0 475 #define DIO_BASE__INST4_SEG4 0 476 477 #define DIO_BASE__INST5_SEG0 0 478 #define DIO_BASE__INST5_SEG1 0 479 #define DIO_BASE__INST5_SEG2 0 480 #define DIO_BASE__INST5_SEG3 0 481 #define DIO_BASE__INST5_SEG4 0 482 483 #define DIO_BASE__INST6_SEG0 0 484 #define DIO_BASE__INST6_SEG1 0 485 #define DIO_BASE__INST6_SEG2 0 486 #define DIO_BASE__INST6_SEG3 0 487 #define DIO_BASE__INST6_SEG4 0 488 489 #define DMU_BASE__INST0_SEG0 0x00000012 490 #define DMU_BASE__INST0_SEG1 0x000000C0 491 #define DMU_BASE__INST0_SEG2 0x000034C0 492 #define DMU_BASE__INST0_SEG3 0x00009000 493 #define DMU_BASE__INST0_SEG4 0x02403C00 494 495 #define DMU_BASE__INST1_SEG0 0 496 #define DMU_BASE__INST1_SEG1 0 497 #define DMU_BASE__INST1_SEG2 0 498 #define DMU_BASE__INST1_SEG3 0 499 #define DMU_BASE__INST1_SEG4 0 500 501 #define DMU_BASE__INST2_SEG0 0 502 #define DMU_BASE__INST2_SEG1 0 503 #define DMU_BASE__INST2_SEG2 0 504 #define DMU_BASE__INST2_SEG3 0 505 #define DMU_BASE__INST2_SEG4 0 506 507 #define DMU_BASE__INST3_SEG0 0 508 #define DMU_BASE__INST3_SEG1 0 509 #define DMU_BASE__INST3_SEG2 0 510 #define DMU_BASE__INST3_SEG3 0 511 #define DMU_BASE__INST3_SEG4 0 512 513 #define DMU_BASE__INST4_SEG0 0 514 #define DMU_BASE__INST4_SEG1 0 515 #define DMU_BASE__INST4_SEG2 0 516 #define DMU_BASE__INST4_SEG3 0 517 #define DMU_BASE__INST4_SEG4 0 518 519 #define DMU_BASE__INST5_SEG0 0 520 #define DMU_BASE__INST5_SEG1 0 521 #define DMU_BASE__INST5_SEG2 0 522 #define DMU_BASE__INST5_SEG3 0 523 #define DMU_BASE__INST5_SEG4 0 524 525 #define DMU_BASE__INST6_SEG0 0 526 #define DMU_BASE__INST6_SEG1 0 527 #define DMU_BASE__INST6_SEG2 0 528 #define DMU_BASE__INST6_SEG3 0 529 #define DMU_BASE__INST6_SEG4 0 530 531 #define DPCS_BASE__INST0_SEG0 0x00000012 532 #define DPCS_BASE__INST0_SEG1 0x000000C0 533 #define DPCS_BASE__INST0_SEG2 0x000034C0 534 #define DPCS_BASE__INST0_SEG3 0x00009000 535 #define DPCS_BASE__INST0_SEG4 0x02403C00 536 537 #define DPCS_BASE__INST1_SEG0 0 538 #define DPCS_BASE__INST1_SEG1 0 539 #define DPCS_BASE__INST1_SEG2 0 540 #define DPCS_BASE__INST1_SEG3 0 541 #define DPCS_BASE__INST1_SEG4 0 542 543 #define DPCS_BASE__INST2_SEG0 0 544 #define DPCS_BASE__INST2_SEG1 0 545 #define DPCS_BASE__INST2_SEG2 0 546 #define DPCS_BASE__INST2_SEG3 0 547 #define DPCS_BASE__INST2_SEG4 0 548 549 #define DPCS_BASE__INST3_SEG0 0 550 #define DPCS_BASE__INST3_SEG1 0 551 #define DPCS_BASE__INST3_SEG2 0 552 #define DPCS_BASE__INST3_SEG3 0 553 #define DPCS_BASE__INST3_SEG4 0 554 555 #define DPCS_BASE__INST4_SEG0 0 556 #define DPCS_BASE__INST4_SEG1 0 557 #define DPCS_BASE__INST4_SEG2 0 558 #define DPCS_BASE__INST4_SEG3 0 559 #define DPCS_BASE__INST4_SEG4 0 560 561 #define DPCS_BASE__INST5_SEG0 0 562 #define DPCS_BASE__INST5_SEG1 0 563 #define DPCS_BASE__INST5_SEG2 0 564 #define DPCS_BASE__INST5_SEG3 0 565 #define DPCS_BASE__INST5_SEG4 0 566 567 #define DPCS_BASE__INST6_SEG0 0 568 #define DPCS_BASE__INST6_SEG1 0 569 #define DPCS_BASE__INST6_SEG2 0 570 #define DPCS_BASE__INST6_SEG3 0 571 #define DPCS_BASE__INST6_SEG4 0 572 573 #define FUSE_BASE__INST0_SEG0 0x00017400 574 #define FUSE_BASE__INST0_SEG1 0x02401400 575 #define FUSE_BASE__INST0_SEG2 0 576 #define FUSE_BASE__INST0_SEG3 0 577 #define FUSE_BASE__INST0_SEG4 0 578 579 #define FUSE_BASE__INST1_SEG0 0 580 #define FUSE_BASE__INST1_SEG1 0 581 #define FUSE_BASE__INST1_SEG2 0 582 #define FUSE_BASE__INST1_SEG3 0 583 #define FUSE_BASE__INST1_SEG4 0 584 585 #define FUSE_BASE__INST2_SEG0 0 586 #define FUSE_BASE__INST2_SEG1 0 587 #define FUSE_BASE__INST2_SEG2 0 588 #define FUSE_BASE__INST2_SEG3 0 589 #define FUSE_BASE__INST2_SEG4 0 590 591 #define FUSE_BASE__INST3_SEG0 0 592 #define FUSE_BASE__INST3_SEG1 0 593 #define FUSE_BASE__INST3_SEG2 0 594 #define FUSE_BASE__INST3_SEG3 0 595 #define FUSE_BASE__INST3_SEG4 0 596 597 #define FUSE_BASE__INST4_SEG0 0 598 #define FUSE_BASE__INST4_SEG1 0 599 #define FUSE_BASE__INST4_SEG2 0 600 #define FUSE_BASE__INST4_SEG3 0 601 #define FUSE_BASE__INST4_SEG4 0 602 603 #define FUSE_BASE__INST5_SEG0 0 604 #define FUSE_BASE__INST5_SEG1 0 605 #define FUSE_BASE__INST5_SEG2 0 606 #define FUSE_BASE__INST5_SEG3 0 607 #define FUSE_BASE__INST5_SEG4 0 608 609 #define FUSE_BASE__INST6_SEG0 0 610 #define FUSE_BASE__INST6_SEG1 0 611 #define FUSE_BASE__INST6_SEG2 0 612 #define FUSE_BASE__INST6_SEG3 0 613 #define FUSE_BASE__INST6_SEG4 0 614 615 #define GC_BASE__INST0_SEG0 0x00002000 616 #define GC_BASE__INST0_SEG1 0x0000A000 617 #define GC_BASE__INST0_SEG2 0x02402C00 618 #define GC_BASE__INST0_SEG3 0 619 #define GC_BASE__INST0_SEG4 0 620 621 #define GC_BASE__INST1_SEG0 0 622 #define GC_BASE__INST1_SEG1 0 623 #define GC_BASE__INST1_SEG2 0 624 #define GC_BASE__INST1_SEG3 0 625 #define GC_BASE__INST1_SEG4 0 626 627 #define GC_BASE__INST2_SEG0 0 628 #define GC_BASE__INST2_SEG1 0 629 #define GC_BASE__INST2_SEG2 0 630 #define GC_BASE__INST2_SEG3 0 631 #define GC_BASE__INST2_SEG4 0 632 633 #define GC_BASE__INST3_SEG0 0 634 #define GC_BASE__INST3_SEG1 0 635 #define GC_BASE__INST3_SEG2 0 636 #define GC_BASE__INST3_SEG3 0 637 #define GC_BASE__INST3_SEG4 0 638 639 #define GC_BASE__INST4_SEG0 0 640 #define GC_BASE__INST4_SEG1 0 641 #define GC_BASE__INST4_SEG2 0 642 #define GC_BASE__INST4_SEG3 0 643 #define GC_BASE__INST4_SEG4 0 644 645 #define GC_BASE__INST5_SEG0 0 646 #define GC_BASE__INST5_SEG1 0 647 #define GC_BASE__INST5_SEG2 0 648 #define GC_BASE__INST5_SEG3 0 649 #define GC_BASE__INST5_SEG4 0 650 651 #define GC_BASE__INST6_SEG0 0 652 #define GC_BASE__INST6_SEG1 0 653 #define GC_BASE__INST6_SEG2 0 654 #define GC_BASE__INST6_SEG3 0 655 #define GC_BASE__INST6_SEG4 0 656 657 #define HDA_BASE__INST0_SEG0 0x02404800 658 #define HDA_BASE__INST0_SEG1 0x004C0000 659 #define HDA_BASE__INST0_SEG2 0 660 #define HDA_BASE__INST0_SEG3 0 661 #define HDA_BASE__INST0_SEG4 0 662 663 #define HDA_BASE__INST1_SEG0 0 664 #define HDA_BASE__INST1_SEG1 0 665 #define HDA_BASE__INST1_SEG2 0 666 #define HDA_BASE__INST1_SEG3 0 667 #define HDA_BASE__INST1_SEG4 0 668 669 #define HDA_BASE__INST2_SEG0 0 670 #define HDA_BASE__INST2_SEG1 0 671 #define HDA_BASE__INST2_SEG2 0 672 #define HDA_BASE__INST2_SEG3 0 673 #define HDA_BASE__INST2_SEG4 0 674 675 #define HDA_BASE__INST3_SEG0 0 676 #define HDA_BASE__INST3_SEG1 0 677 #define HDA_BASE__INST3_SEG2 0 678 #define HDA_BASE__INST3_SEG3 0 679 #define HDA_BASE__INST3_SEG4 0 680 681 #define HDA_BASE__INST4_SEG0 0 682 #define HDA_BASE__INST4_SEG1 0 683 #define HDA_BASE__INST4_SEG2 0 684 #define HDA_BASE__INST4_SEG3 0 685 #define HDA_BASE__INST4_SEG4 0 686 687 #define HDA_BASE__INST5_SEG0 0 688 #define HDA_BASE__INST5_SEG1 0 689 #define HDA_BASE__INST5_SEG2 0 690 #define HDA_BASE__INST5_SEG3 0 691 #define HDA_BASE__INST5_SEG4 0 692 693 #define HDA_BASE__INST6_SEG0 0 694 #define HDA_BASE__INST6_SEG1 0 695 #define HDA_BASE__INST6_SEG2 0 696 #define HDA_BASE__INST6_SEG3 0 697 #define HDA_BASE__INST6_SEG4 0 698 699 #define HDP_BASE__INST0_SEG0 0x00000F20 700 #define HDP_BASE__INST0_SEG1 0x0240A400 701 #define HDP_BASE__INST0_SEG2 0 702 #define HDP_BASE__INST0_SEG3 0 703 #define HDP_BASE__INST0_SEG4 0 704 705 #define HDP_BASE__INST1_SEG0 0 706 #define HDP_BASE__INST1_SEG1 0 707 #define HDP_BASE__INST1_SEG2 0 708 #define HDP_BASE__INST1_SEG3 0 709 #define HDP_BASE__INST1_SEG4 0 710 711 #define HDP_BASE__INST2_SEG0 0 712 #define HDP_BASE__INST2_SEG1 0 713 #define HDP_BASE__INST2_SEG2 0 714 #define HDP_BASE__INST2_SEG3 0 715 #define HDP_BASE__INST2_SEG4 0 716 717 #define HDP_BASE__INST3_SEG0 0 718 #define HDP_BASE__INST3_SEG1 0 719 #define HDP_BASE__INST3_SEG2 0 720 #define HDP_BASE__INST3_SEG3 0 721 #define HDP_BASE__INST3_SEG4 0 722 723 #define HDP_BASE__INST4_SEG0 0 724 #define HDP_BASE__INST4_SEG1 0 725 #define HDP_BASE__INST4_SEG2 0 726 #define HDP_BASE__INST4_SEG3 0 727 #define HDP_BASE__INST4_SEG4 0 728 729 #define HDP_BASE__INST5_SEG0 0 730 #define HDP_BASE__INST5_SEG1 0 731 #define HDP_BASE__INST5_SEG2 0 732 #define HDP_BASE__INST5_SEG3 0 733 #define HDP_BASE__INST5_SEG4 0 734 735 #define HDP_BASE__INST6_SEG0 0 736 #define HDP_BASE__INST6_SEG1 0 737 #define HDP_BASE__INST6_SEG2 0 738 #define HDP_BASE__INST6_SEG3 0 739 #define HDP_BASE__INST6_SEG4 0 740 741 #define IOHC0_BASE__INST0_SEG0 0x00010000 742 #define IOHC0_BASE__INST0_SEG1 0x02406000 743 #define IOHC0_BASE__INST0_SEG2 0x04EC0000 744 #define IOHC0_BASE__INST0_SEG3 0 745 #define IOHC0_BASE__INST0_SEG4 0 746 747 #define IOHC0_BASE__INST1_SEG0 0 748 #define IOHC0_BASE__INST1_SEG1 0 749 #define IOHC0_BASE__INST1_SEG2 0 750 #define IOHC0_BASE__INST1_SEG3 0 751 #define IOHC0_BASE__INST1_SEG4 0 752 753 #define IOHC0_BASE__INST2_SEG0 0 754 #define IOHC0_BASE__INST2_SEG1 0 755 #define IOHC0_BASE__INST2_SEG2 0 756 #define IOHC0_BASE__INST2_SEG3 0 757 #define IOHC0_BASE__INST2_SEG4 0 758 759 #define IOHC0_BASE__INST3_SEG0 0 760 #define IOHC0_BASE__INST3_SEG1 0 761 #define IOHC0_BASE__INST3_SEG2 0 762 #define IOHC0_BASE__INST3_SEG3 0 763 #define IOHC0_BASE__INST3_SEG4 0 764 765 #define IOHC0_BASE__INST4_SEG0 0 766 #define IOHC0_BASE__INST4_SEG1 0 767 #define IOHC0_BASE__INST4_SEG2 0 768 #define IOHC0_BASE__INST4_SEG3 0 769 #define IOHC0_BASE__INST4_SEG4 0 770 771 #define IOHC0_BASE__INST5_SEG0 0 772 #define IOHC0_BASE__INST5_SEG1 0 773 #define IOHC0_BASE__INST5_SEG2 0 774 #define IOHC0_BASE__INST5_SEG3 0 775 #define IOHC0_BASE__INST5_SEG4 0 776 777 #define IOHC0_BASE__INST6_SEG0 0 778 #define IOHC0_BASE__INST6_SEG1 0 779 #define IOHC0_BASE__INST6_SEG2 0 780 #define IOHC0_BASE__INST6_SEG3 0 781 #define IOHC0_BASE__INST6_SEG4 0 782 783 #define ISP_BASE__INST0_SEG0 0x00018000 784 #define ISP_BASE__INST0_SEG1 0x0240B000 785 #define ISP_BASE__INST0_SEG2 0 786 #define ISP_BASE__INST0_SEG3 0 787 #define ISP_BASE__INST0_SEG4 0 788 789 #define ISP_BASE__INST1_SEG0 0 790 #define ISP_BASE__INST1_SEG1 0 791 #define ISP_BASE__INST1_SEG2 0 792 #define ISP_BASE__INST1_SEG3 0 793 #define ISP_BASE__INST1_SEG4 0 794 795 #define ISP_BASE__INST2_SEG0 0 796 #define ISP_BASE__INST2_SEG1 0 797 #define ISP_BASE__INST2_SEG2 0 798 #define ISP_BASE__INST2_SEG3 0 799 #define ISP_BASE__INST2_SEG4 0 800 801 #define ISP_BASE__INST3_SEG0 0 802 #define ISP_BASE__INST3_SEG1 0 803 #define ISP_BASE__INST3_SEG2 0 804 #define ISP_BASE__INST3_SEG3 0 805 #define ISP_BASE__INST3_SEG4 0 806 807 #define ISP_BASE__INST4_SEG0 0 808 #define ISP_BASE__INST4_SEG1 0 809 #define ISP_BASE__INST4_SEG2 0 810 #define ISP_BASE__INST4_SEG3 0 811 #define ISP_BASE__INST4_SEG4 0 812 813 #define ISP_BASE__INST5_SEG0 0 814 #define ISP_BASE__INST5_SEG1 0 815 #define ISP_BASE__INST5_SEG2 0 816 #define ISP_BASE__INST5_SEG3 0 817 #define ISP_BASE__INST5_SEG4 0 818 819 #define ISP_BASE__INST6_SEG0 0 820 #define ISP_BASE__INST6_SEG1 0 821 #define ISP_BASE__INST6_SEG2 0 822 #define ISP_BASE__INST6_SEG3 0 823 #define ISP_BASE__INST6_SEG4 0 824 825 #define L2IMU0_BASE__INST0_SEG0 0x00007DC0 826 #define L2IMU0_BASE__INST0_SEG1 0x02407000 827 #define L2IMU0_BASE__INST0_SEG2 0x00900000 828 #define L2IMU0_BASE__INST0_SEG3 0x04FC0000 829 #define L2IMU0_BASE__INST0_SEG4 0x055C0000 830 831 #define L2IMU0_BASE__INST1_SEG0 0 832 #define L2IMU0_BASE__INST1_SEG1 0 833 #define L2IMU0_BASE__INST1_SEG2 0 834 #define L2IMU0_BASE__INST1_SEG3 0 835 #define L2IMU0_BASE__INST1_SEG4 0 836 837 #define L2IMU0_BASE__INST2_SEG0 0 838 #define L2IMU0_BASE__INST2_SEG1 0 839 #define L2IMU0_BASE__INST2_SEG2 0 840 #define L2IMU0_BASE__INST2_SEG3 0 841 #define L2IMU0_BASE__INST2_SEG4 0 842 843 #define L2IMU0_BASE__INST3_SEG0 0 844 #define L2IMU0_BASE__INST3_SEG1 0 845 #define L2IMU0_BASE__INST3_SEG2 0 846 #define L2IMU0_BASE__INST3_SEG3 0 847 #define L2IMU0_BASE__INST3_SEG4 0 848 849 #define L2IMU0_BASE__INST4_SEG0 0 850 #define L2IMU0_BASE__INST4_SEG1 0 851 #define L2IMU0_BASE__INST4_SEG2 0 852 #define L2IMU0_BASE__INST4_SEG3 0 853 #define L2IMU0_BASE__INST4_SEG4 0 854 855 #define L2IMU0_BASE__INST5_SEG0 0 856 #define L2IMU0_BASE__INST5_SEG1 0 857 #define L2IMU0_BASE__INST5_SEG2 0 858 #define L2IMU0_BASE__INST5_SEG3 0 859 #define L2IMU0_BASE__INST5_SEG4 0 860 861 #define L2IMU0_BASE__INST6_SEG0 0 862 #define L2IMU0_BASE__INST6_SEG1 0 863 #define L2IMU0_BASE__INST6_SEG2 0 864 #define L2IMU0_BASE__INST6_SEG3 0 865 #define L2IMU0_BASE__INST6_SEG4 0 866 867 #define MMHUB_BASE__INST0_SEG0 0x0001A000 868 #define MMHUB_BASE__INST0_SEG1 0x02408800 869 #define MMHUB_BASE__INST0_SEG2 0 870 #define MMHUB_BASE__INST0_SEG3 0 871 #define MMHUB_BASE__INST0_SEG4 0 872 873 #define MMHUB_BASE__INST1_SEG0 0 874 #define MMHUB_BASE__INST1_SEG1 0 875 #define MMHUB_BASE__INST1_SEG2 0 876 #define MMHUB_BASE__INST1_SEG3 0 877 #define MMHUB_BASE__INST1_SEG4 0 878 879 #define MMHUB_BASE__INST2_SEG0 0 880 #define MMHUB_BASE__INST2_SEG1 0 881 #define MMHUB_BASE__INST2_SEG2 0 882 #define MMHUB_BASE__INST2_SEG3 0 883 #define MMHUB_BASE__INST2_SEG4 0 884 885 #define MMHUB_BASE__INST3_SEG0 0 886 #define MMHUB_BASE__INST3_SEG1 0 887 #define MMHUB_BASE__INST3_SEG2 0 888 #define MMHUB_BASE__INST3_SEG3 0 889 #define MMHUB_BASE__INST3_SEG4 0 890 891 #define MMHUB_BASE__INST4_SEG0 0 892 #define MMHUB_BASE__INST4_SEG1 0 893 #define MMHUB_BASE__INST4_SEG2 0 894 #define MMHUB_BASE__INST4_SEG3 0 895 #define MMHUB_BASE__INST4_SEG4 0 896 897 #define MMHUB_BASE__INST5_SEG0 0 898 #define MMHUB_BASE__INST5_SEG1 0 899 #define MMHUB_BASE__INST5_SEG2 0 900 #define MMHUB_BASE__INST5_SEG3 0 901 #define MMHUB_BASE__INST5_SEG4 0 902 903 #define MMHUB_BASE__INST6_SEG0 0 904 #define MMHUB_BASE__INST6_SEG1 0 905 #define MMHUB_BASE__INST6_SEG2 0 906 #define MMHUB_BASE__INST6_SEG3 0 907 #define MMHUB_BASE__INST6_SEG4 0 908 909 #define MP0_BASE__INST0_SEG0 0x00016000 910 #define MP0_BASE__INST0_SEG1 0x0243FC00 911 #define MP0_BASE__INST0_SEG2 0x00DC0000 912 #define MP0_BASE__INST0_SEG3 0x00E00000 913 #define MP0_BASE__INST0_SEG4 0x00E40000 914 915 #define MP0_BASE__INST1_SEG0 0 916 #define MP0_BASE__INST1_SEG1 0 917 #define MP0_BASE__INST1_SEG2 0 918 #define MP0_BASE__INST1_SEG3 0 919 #define MP0_BASE__INST1_SEG4 0 920 921 #define MP0_BASE__INST2_SEG0 0 922 #define MP0_BASE__INST2_SEG1 0 923 #define MP0_BASE__INST2_SEG2 0 924 #define MP0_BASE__INST2_SEG3 0 925 #define MP0_BASE__INST2_SEG4 0 926 927 #define MP0_BASE__INST3_SEG0 0 928 #define MP0_BASE__INST3_SEG1 0 929 #define MP0_BASE__INST3_SEG2 0 930 #define MP0_BASE__INST3_SEG3 0 931 #define MP0_BASE__INST3_SEG4 0 932 933 #define MP0_BASE__INST4_SEG0 0 934 #define MP0_BASE__INST4_SEG1 0 935 #define MP0_BASE__INST4_SEG2 0 936 #define MP0_BASE__INST4_SEG3 0 937 #define MP0_BASE__INST4_SEG4 0 938 939 #define MP0_BASE__INST5_SEG0 0 940 #define MP0_BASE__INST5_SEG1 0 941 #define MP0_BASE__INST5_SEG2 0 942 #define MP0_BASE__INST5_SEG3 0 943 #define MP0_BASE__INST5_SEG4 0 944 945 #define MP0_BASE__INST6_SEG0 0 946 #define MP0_BASE__INST6_SEG1 0 947 #define MP0_BASE__INST6_SEG2 0 948 #define MP0_BASE__INST6_SEG3 0 949 #define MP0_BASE__INST6_SEG4 0 950 951 #define MP1_BASE__INST0_SEG0 0x00016200 952 #define MP1_BASE__INST0_SEG1 0x02400400 953 #define MP1_BASE__INST0_SEG2 0x00E80000 954 #define MP1_BASE__INST0_SEG3 0x00EC0000 955 #define MP1_BASE__INST0_SEG4 0x00F00000 956 957 #define MP1_BASE__INST1_SEG0 0 958 #define MP1_BASE__INST1_SEG1 0 959 #define MP1_BASE__INST1_SEG2 0 960 #define MP1_BASE__INST1_SEG3 0 961 #define MP1_BASE__INST1_SEG4 0 962 963 #define MP1_BASE__INST2_SEG0 0 964 #define MP1_BASE__INST2_SEG1 0 965 #define MP1_BASE__INST2_SEG2 0 966 #define MP1_BASE__INST2_SEG3 0 967 #define MP1_BASE__INST2_SEG4 0 968 969 #define MP1_BASE__INST3_SEG0 0 970 #define MP1_BASE__INST3_SEG1 0 971 #define MP1_BASE__INST3_SEG2 0 972 #define MP1_BASE__INST3_SEG3 0 973 #define MP1_BASE__INST3_SEG4 0 974 975 #define MP1_BASE__INST4_SEG0 0 976 #define MP1_BASE__INST4_SEG1 0 977 #define MP1_BASE__INST4_SEG2 0 978 #define MP1_BASE__INST4_SEG3 0 979 #define MP1_BASE__INST4_SEG4 0 980 981 #define MP1_BASE__INST5_SEG0 0 982 #define MP1_BASE__INST5_SEG1 0 983 #define MP1_BASE__INST5_SEG2 0 984 #define MP1_BASE__INST5_SEG3 0 985 #define MP1_BASE__INST5_SEG4 0 986 987 #define MP1_BASE__INST6_SEG0 0 988 #define MP1_BASE__INST6_SEG1 0 989 #define MP1_BASE__INST6_SEG2 0 990 #define MP1_BASE__INST6_SEG3 0 991 #define MP1_BASE__INST6_SEG4 0 992 993 #define NBIF0_BASE__INST0_SEG0 0x00000000 994 #define NBIF0_BASE__INST0_SEG1 0x00000014 995 #define NBIF0_BASE__INST0_SEG2 0x00000D20 996 #define NBIF0_BASE__INST0_SEG3 0x00010400 997 #define NBIF0_BASE__INST0_SEG4 0x0241B000 998 999 #define NBIF0_BASE__INST1_SEG0 0 1000 #define NBIF0_BASE__INST1_SEG1 0 1001 #define NBIF0_BASE__INST1_SEG2 0 1002 #define NBIF0_BASE__INST1_SEG3 0 1003 #define NBIF0_BASE__INST1_SEG4 0 1004 1005 #define NBIF0_BASE__INST2_SEG0 0 1006 #define NBIF0_BASE__INST2_SEG1 0 1007 #define NBIF0_BASE__INST2_SEG2 0 1008 #define NBIF0_BASE__INST2_SEG3 0 1009 #define NBIF0_BASE__INST2_SEG4 0 1010 1011 #define NBIF0_BASE__INST3_SEG0 0 1012 #define NBIF0_BASE__INST3_SEG1 0 1013 #define NBIF0_BASE__INST3_SEG2 0 1014 #define NBIF0_BASE__INST3_SEG3 0 1015 #define NBIF0_BASE__INST3_SEG4 0 1016 1017 #define NBIF0_BASE__INST4_SEG0 0 1018 #define NBIF0_BASE__INST4_SEG1 0 1019 #define NBIF0_BASE__INST4_SEG2 0 1020 #define NBIF0_BASE__INST4_SEG3 0 1021 #define NBIF0_BASE__INST4_SEG4 0 1022 1023 #define NBIF0_BASE__INST5_SEG0 0 1024 #define NBIF0_BASE__INST5_SEG1 0 1025 #define NBIF0_BASE__INST5_SEG2 0 1026 #define NBIF0_BASE__INST5_SEG3 0 1027 #define NBIF0_BASE__INST5_SEG4 0 1028 1029 #define NBIF0_BASE__INST6_SEG0 0 1030 #define NBIF0_BASE__INST6_SEG1 0 1031 #define NBIF0_BASE__INST6_SEG2 0 1032 #define NBIF0_BASE__INST6_SEG3 0 1033 #define NBIF0_BASE__INST6_SEG4 0 1034 1035 #define OSSSYS_BASE__INST0_SEG0 0x000010A0 1036 #define OSSSYS_BASE__INST0_SEG1 0x0240A000 1037 #define OSSSYS_BASE__INST0_SEG2 0 1038 #define OSSSYS_BASE__INST0_SEG3 0 1039 #define OSSSYS_BASE__INST0_SEG4 0 1040 1041 #define OSSSYS_BASE__INST1_SEG0 0 1042 #define OSSSYS_BASE__INST1_SEG1 0 1043 #define OSSSYS_BASE__INST1_SEG2 0 1044 #define OSSSYS_BASE__INST1_SEG3 0 1045 #define OSSSYS_BASE__INST1_SEG4 0 1046 1047 #define OSSSYS_BASE__INST2_SEG0 0 1048 #define OSSSYS_BASE__INST2_SEG1 0 1049 #define OSSSYS_BASE__INST2_SEG2 0 1050 #define OSSSYS_BASE__INST2_SEG3 0 1051 #define OSSSYS_BASE__INST2_SEG4 0 1052 1053 #define OSSSYS_BASE__INST3_SEG0 0 1054 #define OSSSYS_BASE__INST3_SEG1 0 1055 #define OSSSYS_BASE__INST3_SEG2 0 1056 #define OSSSYS_BASE__INST3_SEG3 0 1057 #define OSSSYS_BASE__INST3_SEG4 0 1058 1059 #define OSSSYS_BASE__INST4_SEG0 0 1060 #define OSSSYS_BASE__INST4_SEG1 0 1061 #define OSSSYS_BASE__INST4_SEG2 0 1062 #define OSSSYS_BASE__INST4_SEG3 0 1063 #define OSSSYS_BASE__INST4_SEG4 0 1064 1065 #define OSSSYS_BASE__INST5_SEG0 0 1066 #define OSSSYS_BASE__INST5_SEG1 0 1067 #define OSSSYS_BASE__INST5_SEG2 0 1068 #define OSSSYS_BASE__INST5_SEG3 0 1069 #define OSSSYS_BASE__INST5_SEG4 0 1070 1071 #define OSSSYS_BASE__INST6_SEG0 0 1072 #define OSSSYS_BASE__INST6_SEG1 0 1073 #define OSSSYS_BASE__INST6_SEG2 0 1074 #define OSSSYS_BASE__INST6_SEG3 0 1075 #define OSSSYS_BASE__INST6_SEG4 0 1076 1077 #define PCIE0_BASE__INST0_SEG0 0x02411800 1078 #define PCIE0_BASE__INST0_SEG1 0x04440000 1079 #define PCIE0_BASE__INST0_SEG2 0 1080 #define PCIE0_BASE__INST0_SEG3 0 1081 #define PCIE0_BASE__INST0_SEG4 0 1082 1083 #define PCIE0_BASE__INST1_SEG0 0 1084 #define PCIE0_BASE__INST1_SEG1 0 1085 #define PCIE0_BASE__INST1_SEG2 0 1086 #define PCIE0_BASE__INST1_SEG3 0 1087 #define PCIE0_BASE__INST1_SEG4 0 1088 1089 #define PCIE0_BASE__INST2_SEG0 0 1090 #define PCIE0_BASE__INST2_SEG1 0 1091 #define PCIE0_BASE__INST2_SEG2 0 1092 #define PCIE0_BASE__INST2_SEG3 0 1093 #define PCIE0_BASE__INST2_SEG4 0 1094 1095 #define PCIE0_BASE__INST3_SEG0 0 1096 #define PCIE0_BASE__INST3_SEG1 0 1097 #define PCIE0_BASE__INST3_SEG2 0 1098 #define PCIE0_BASE__INST3_SEG3 0 1099 #define PCIE0_BASE__INST3_SEG4 0 1100 1101 #define PCIE0_BASE__INST4_SEG0 0 1102 #define PCIE0_BASE__INST4_SEG1 0 1103 #define PCIE0_BASE__INST4_SEG2 0 1104 #define PCIE0_BASE__INST4_SEG3 0 1105 #define PCIE0_BASE__INST4_SEG4 0 1106 1107 #define PCIE0_BASE__INST5_SEG0 0 1108 #define PCIE0_BASE__INST5_SEG1 0 1109 #define PCIE0_BASE__INST5_SEG2 0 1110 #define PCIE0_BASE__INST5_SEG3 0 1111 #define PCIE0_BASE__INST5_SEG4 0 1112 1113 #define PCIE0_BASE__INST6_SEG0 0 1114 #define PCIE0_BASE__INST6_SEG1 0 1115 #define PCIE0_BASE__INST6_SEG2 0 1116 #define PCIE0_BASE__INST6_SEG3 0 1117 #define PCIE0_BASE__INST6_SEG4 0 1118 1119 #define SDMA0_BASE__INST0_SEG0 0x00001260 1120 #define SDMA0_BASE__INST0_SEG1 0x0240A800 1121 #define SDMA0_BASE__INST0_SEG2 0 1122 #define SDMA0_BASE__INST0_SEG3 0 1123 #define SDMA0_BASE__INST0_SEG4 0 1124 1125 #define SDMA0_BASE__INST1_SEG0 0 1126 #define SDMA0_BASE__INST1_SEG1 0 1127 #define SDMA0_BASE__INST1_SEG2 0 1128 #define SDMA0_BASE__INST1_SEG3 0 1129 #define SDMA0_BASE__INST1_SEG4 0 1130 1131 #define SDMA0_BASE__INST2_SEG0 0 1132 #define SDMA0_BASE__INST2_SEG1 0 1133 #define SDMA0_BASE__INST2_SEG2 0 1134 #define SDMA0_BASE__INST2_SEG3 0 1135 #define SDMA0_BASE__INST2_SEG4 0 1136 1137 #define SDMA0_BASE__INST3_SEG0 0 1138 #define SDMA0_BASE__INST3_SEG1 0 1139 #define SDMA0_BASE__INST3_SEG2 0 1140 #define SDMA0_BASE__INST3_SEG3 0 1141 #define SDMA0_BASE__INST3_SEG4 0 1142 1143 #define SDMA0_BASE__INST4_SEG0 0 1144 #define SDMA0_BASE__INST4_SEG1 0 1145 #define SDMA0_BASE__INST4_SEG2 0 1146 #define SDMA0_BASE__INST4_SEG3 0 1147 #define SDMA0_BASE__INST4_SEG4 0 1148 1149 #define SDMA0_BASE__INST5_SEG0 0 1150 #define SDMA0_BASE__INST5_SEG1 0 1151 #define SDMA0_BASE__INST5_SEG2 0 1152 #define SDMA0_BASE__INST5_SEG3 0 1153 #define SDMA0_BASE__INST5_SEG4 0 1154 1155 #define SDMA0_BASE__INST6_SEG0 0 1156 #define SDMA0_BASE__INST6_SEG1 0 1157 #define SDMA0_BASE__INST6_SEG2 0 1158 #define SDMA0_BASE__INST6_SEG3 0 1159 #define SDMA0_BASE__INST6_SEG4 0 1160 1161 #define SMUIO_BASE__INST0_SEG0 0x00016800 1162 #define SMUIO_BASE__INST0_SEG1 0x00016A00 1163 #define SMUIO_BASE__INST0_SEG2 0x02401000 1164 #define SMUIO_BASE__INST0_SEG3 0x00440000 1165 #define SMUIO_BASE__INST0_SEG4 0 1166 1167 #define SMUIO_BASE__INST1_SEG0 0 1168 #define SMUIO_BASE__INST1_SEG1 0 1169 #define SMUIO_BASE__INST1_SEG2 0 1170 #define SMUIO_BASE__INST1_SEG3 0 1171 #define SMUIO_BASE__INST1_SEG4 0 1172 1173 #define SMUIO_BASE__INST2_SEG0 0 1174 #define SMUIO_BASE__INST2_SEG1 0 1175 #define SMUIO_BASE__INST2_SEG2 0 1176 #define SMUIO_BASE__INST2_SEG3 0 1177 #define SMUIO_BASE__INST2_SEG4 0 1178 1179 #define SMUIO_BASE__INST3_SEG0 0 1180 #define SMUIO_BASE__INST3_SEG1 0 1181 #define SMUIO_BASE__INST3_SEG2 0 1182 #define SMUIO_BASE__INST3_SEG3 0 1183 #define SMUIO_BASE__INST3_SEG4 0 1184 1185 #define SMUIO_BASE__INST4_SEG0 0 1186 #define SMUIO_BASE__INST4_SEG1 0 1187 #define SMUIO_BASE__INST4_SEG2 0 1188 #define SMUIO_BASE__INST4_SEG3 0 1189 #define SMUIO_BASE__INST4_SEG4 0 1190 1191 #define SMUIO_BASE__INST5_SEG0 0 1192 #define SMUIO_BASE__INST5_SEG1 0 1193 #define SMUIO_BASE__INST5_SEG2 0 1194 #define SMUIO_BASE__INST5_SEG3 0 1195 #define SMUIO_BASE__INST5_SEG4 0 1196 1197 #define SMUIO_BASE__INST6_SEG0 0 1198 #define SMUIO_BASE__INST6_SEG1 0 1199 #define SMUIO_BASE__INST6_SEG2 0 1200 #define SMUIO_BASE__INST6_SEG3 0 1201 #define SMUIO_BASE__INST6_SEG4 0 1202 1203 #define THM_BASE__INST0_SEG0 0x00016600 1204 #define THM_BASE__INST0_SEG1 0x02400C00 1205 #define THM_BASE__INST0_SEG2 0 1206 #define THM_BASE__INST0_SEG3 0 1207 #define THM_BASE__INST0_SEG4 0 1208 1209 #define THM_BASE__INST1_SEG0 0 1210 #define THM_BASE__INST1_SEG1 0 1211 #define THM_BASE__INST1_SEG2 0 1212 #define THM_BASE__INST1_SEG3 0 1213 #define THM_BASE__INST1_SEG4 0 1214 1215 #define THM_BASE__INST2_SEG0 0 1216 #define THM_BASE__INST2_SEG1 0 1217 #define THM_BASE__INST2_SEG2 0 1218 #define THM_BASE__INST2_SEG3 0 1219 #define THM_BASE__INST2_SEG4 0 1220 1221 #define THM_BASE__INST3_SEG0 0 1222 #define THM_BASE__INST3_SEG1 0 1223 #define THM_BASE__INST3_SEG2 0 1224 #define THM_BASE__INST3_SEG3 0 1225 #define THM_BASE__INST3_SEG4 0 1226 1227 #define THM_BASE__INST4_SEG0 0 1228 #define THM_BASE__INST4_SEG1 0 1229 #define THM_BASE__INST4_SEG2 0 1230 #define THM_BASE__INST4_SEG3 0 1231 #define THM_BASE__INST4_SEG4 0 1232 1233 #define THM_BASE__INST5_SEG0 0 1234 #define THM_BASE__INST5_SEG1 0 1235 #define THM_BASE__INST5_SEG2 0 1236 #define THM_BASE__INST5_SEG3 0 1237 #define THM_BASE__INST5_SEG4 0 1238 1239 #define THM_BASE__INST6_SEG0 0 1240 #define THM_BASE__INST6_SEG1 0 1241 #define THM_BASE__INST6_SEG2 0 1242 #define THM_BASE__INST6_SEG3 0 1243 #define THM_BASE__INST6_SEG4 0 1244 1245 #define UMC_BASE__INST0_SEG0 0x00014000 1246 #define UMC_BASE__INST0_SEG1 0x02425800 1247 #define UMC_BASE__INST0_SEG2 0 1248 #define UMC_BASE__INST0_SEG3 0 1249 #define UMC_BASE__INST0_SEG4 0 1250 1251 #define UMC_BASE__INST1_SEG0 0x00054000 1252 #define UMC_BASE__INST1_SEG1 0x02425C00 1253 #define UMC_BASE__INST1_SEG2 0 1254 #define UMC_BASE__INST1_SEG3 0 1255 #define UMC_BASE__INST1_SEG4 0 1256 1257 #define UMC_BASE__INST2_SEG0 0 1258 #define UMC_BASE__INST2_SEG1 0 1259 #define UMC_BASE__INST2_SEG2 0 1260 #define UMC_BASE__INST2_SEG3 0 1261 #define UMC_BASE__INST2_SEG4 0 1262 1263 #define UMC_BASE__INST3_SEG0 0 1264 #define UMC_BASE__INST3_SEG1 0 1265 #define UMC_BASE__INST3_SEG2 0 1266 #define UMC_BASE__INST3_SEG3 0 1267 #define UMC_BASE__INST3_SEG4 0 1268 1269 #define UMC_BASE__INST4_SEG0 0 1270 #define UMC_BASE__INST4_SEG1 0 1271 #define UMC_BASE__INST4_SEG2 0 1272 #define UMC_BASE__INST4_SEG3 0 1273 #define UMC_BASE__INST4_SEG4 0 1274 1275 #define UMC_BASE__INST5_SEG0 0 1276 #define UMC_BASE__INST5_SEG1 0 1277 #define UMC_BASE__INST5_SEG2 0 1278 #define UMC_BASE__INST5_SEG3 0 1279 #define UMC_BASE__INST5_SEG4 0 1280 1281 #define UMC_BASE__INST6_SEG0 0 1282 #define UMC_BASE__INST6_SEG1 0 1283 #define UMC_BASE__INST6_SEG2 0 1284 #define UMC_BASE__INST6_SEG3 0 1285 #define UMC_BASE__INST6_SEG4 0 1286 1287 #define USB0_BASE__INST0_SEG0 0x0242A800 1288 #define USB0_BASE__INST0_SEG1 0x05B00000 1289 #define USB0_BASE__INST0_SEG2 0 1290 #define USB0_BASE__INST0_SEG3 0 1291 #define USB0_BASE__INST0_SEG4 0 1292 1293 #define USB0_BASE__INST1_SEG0 0 1294 #define USB0_BASE__INST1_SEG1 0 1295 #define USB0_BASE__INST1_SEG2 0 1296 #define USB0_BASE__INST1_SEG3 0 1297 #define USB0_BASE__INST1_SEG4 0 1298 1299 #define USB0_BASE__INST2_SEG0 0 1300 #define USB0_BASE__INST2_SEG1 0 1301 #define USB0_BASE__INST2_SEG2 0 1302 #define USB0_BASE__INST2_SEG3 0 1303 #define USB0_BASE__INST2_SEG4 0 1304 1305 #define USB0_BASE__INST3_SEG0 0 1306 #define USB0_BASE__INST3_SEG1 0 1307 #define USB0_BASE__INST3_SEG2 0 1308 #define USB0_BASE__INST3_SEG3 0 1309 #define USB0_BASE__INST3_SEG4 0 1310 1311 #define USB0_BASE__INST4_SEG0 0 1312 #define USB0_BASE__INST4_SEG1 0 1313 #define USB0_BASE__INST4_SEG2 0 1314 #define USB0_BASE__INST4_SEG3 0 1315 #define USB0_BASE__INST4_SEG4 0 1316 1317 #define USB0_BASE__INST5_SEG0 0 1318 #define USB0_BASE__INST5_SEG1 0 1319 #define USB0_BASE__INST5_SEG2 0 1320 #define USB0_BASE__INST5_SEG3 0 1321 #define USB0_BASE__INST5_SEG4 0 1322 1323 #define USB0_BASE__INST6_SEG0 0 1324 #define USB0_BASE__INST6_SEG1 0 1325 #define USB0_BASE__INST6_SEG2 0 1326 #define USB0_BASE__INST6_SEG3 0 1327 #define USB0_BASE__INST6_SEG4 0 1328 1329 #define UVD0_BASE__INST0_SEG0 0x00007800 1330 #define UVD0_BASE__INST0_SEG1 0x00007E00 1331 #define UVD0_BASE__INST0_SEG2 0x02403000 1332 #define UVD0_BASE__INST0_SEG3 0 1333 #define UVD0_BASE__INST0_SEG4 0 1334 1335 #define UVD0_BASE__INST1_SEG0 0 1336 #define UVD0_BASE__INST1_SEG1 0 1337 #define UVD0_BASE__INST1_SEG2 0 1338 #define UVD0_BASE__INST1_SEG3 0 1339 #define UVD0_BASE__INST1_SEG4 0 1340 1341 #define UVD0_BASE__INST2_SEG0 0 1342 #define UVD0_BASE__INST2_SEG1 0 1343 #define UVD0_BASE__INST2_SEG2 0 1344 #define UVD0_BASE__INST2_SEG3 0 1345 #define UVD0_BASE__INST2_SEG4 0 1346 1347 #define UVD0_BASE__INST3_SEG0 0 1348 #define UVD0_BASE__INST3_SEG1 0 1349 #define UVD0_BASE__INST3_SEG2 0 1350 #define UVD0_BASE__INST3_SEG3 0 1351 #define UVD0_BASE__INST3_SEG4 0 1352 1353 #define UVD0_BASE__INST4_SEG0 0 1354 #define UVD0_BASE__INST4_SEG1 0 1355 #define UVD0_BASE__INST4_SEG2 0 1356 #define UVD0_BASE__INST4_SEG3 0 1357 #define UVD0_BASE__INST4_SEG4 0 1358 1359 #define UVD0_BASE__INST5_SEG0 0 1360 #define UVD0_BASE__INST5_SEG1 0 1361 #define UVD0_BASE__INST5_SEG2 0 1362 #define UVD0_BASE__INST5_SEG3 0 1363 #define UVD0_BASE__INST5_SEG4 0 1364 1365 #define UVD0_BASE__INST6_SEG0 0 1366 #define UVD0_BASE__INST6_SEG1 0 1367 #define UVD0_BASE__INST6_SEG2 0 1368 #define UVD0_BASE__INST6_SEG3 0 1369 #define UVD0_BASE__INST6_SEG4 0 1370 1371 #define DCN_BASE__INST0_SEG0 0x00000012 1372 #define DCN_BASE__INST0_SEG1 0x000000C0 1373 #define DCN_BASE__INST0_SEG2 0x000034C0 1374 #define DCN_BASE__INST0_SEG3 0 1375 #define DCN_BASE__INST0_SEG4 0 1376 1377 #define DCN_BASE__INST1_SEG0 0 1378 #define DCN_BASE__INST1_SEG1 0 1379 #define DCN_BASE__INST1_SEG2 0 1380 #define DCN_BASE__INST1_SEG3 0 1381 #define DCN_BASE__INST1_SEG4 0 1382 1383 #define DCN_BASE__INST2_SEG0 0 1384 #define DCN_BASE__INST2_SEG1 0 1385 #define DCN_BASE__INST2_SEG2 0 1386 #define DCN_BASE__INST2_SEG3 0 1387 #define DCN_BASE__INST2_SEG4 0 1388 1389 #define DCN_BASE__INST3_SEG0 0 1390 #define DCN_BASE__INST3_SEG1 0 1391 #define DCN_BASE__INST3_SEG2 0 1392 #define DCN_BASE__INST3_SEG3 0 1393 #define DCN_BASE__INST3_SEG4 0 1394 1395 #define DCN_BASE__INST4_SEG0 0 1396 #define DCN_BASE__INST4_SEG1 0 1397 #define DCN_BASE__INST4_SEG2 0 1398 #define DCN_BASE__INST4_SEG3 0 1399 #define DCN_BASE__INST4_SEG4 0 1400 #endif 1401
Indexes created Sat Sep 20 22:09:52 GMT 2025