1 /* $NetBSD: vega10_ip_offset.h,v 1.2 2021/12/18 23:45:08 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _vega10_ip_offset_HEADER 24 #define _vega10_ip_offset_HEADER 25 26 #define MAX_INSTANCE 5 27 #define MAX_SEGMENT 5 28 29 struct IP_BASE_INSTANCE 30 { 31 unsigned int segment[MAX_SEGMENT]; 32 }; 33 34 struct IP_BASE 35 { 36 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 37 }; 38 39 40 static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, 41 { { 0, 0, 0, 0, 0 } }, 42 { { 0, 0, 0, 0, 0 } }, 43 { { 0, 0, 0, 0, 0 } }, 44 { { 0, 0, 0, 0, 0 } } } }; 45 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, 46 { { 0, 0, 0, 0, 0 } }, 47 { { 0, 0, 0, 0, 0 } }, 48 { { 0, 0, 0, 0, 0 } }, 49 { { 0, 0, 0, 0, 0 } } } }; 50 static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, 51 { { 0, 0, 0, 0, 0 } }, 52 { { 0, 0, 0, 0, 0 } }, 53 { { 0, 0, 0, 0, 0 } }, 54 { { 0, 0, 0, 0, 0 } } } }; 55 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, 56 { { 0, 0, 0, 0, 0 } }, 57 { { 0, 0, 0, 0, 0 } }, 58 { { 0, 0, 0, 0, 0 } }, 59 { { 0, 0, 0, 0, 0 } } } }; 60 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, 61 { { 0, 0, 0, 0, 0 } }, 62 { { 0, 0, 0, 0, 0 } }, 63 { { 0, 0, 0, 0, 0 } }, 64 { { 0, 0, 0, 0, 0 } } } }; 65 static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, 66 { { 0, 0, 0, 0, 0 } }, 67 { { 0, 0, 0, 0, 0 } }, 68 { { 0, 0, 0, 0, 0 } }, 69 { { 0, 0, 0, 0, 0 } } } }; 70 static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, 71 { { 0, 0, 0, 0, 0 } }, 72 { { 0, 0, 0, 0, 0 } }, 73 { { 0, 0, 0, 0, 0 } }, 74 { { 0, 0, 0, 0, 0 } } } }; 75 static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } }, 76 { { 0, 0, 0, 0, 0 } }, 77 { { 0, 0, 0, 0, 0 } }, 78 { { 0, 0, 0, 0, 0 } }, 79 { { 0, 0, 0, 0, 0 } } } }; 80 static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, 81 { { 0, 0, 0, 0, 0 } }, 82 { { 0, 0, 0, 0, 0 } }, 83 { { 0, 0, 0, 0, 0 } }, 84 { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment 85 static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, 86 { { 0, 0, 0, 0, 0 } }, 87 { { 0, 0, 0, 0, 0 } }, 88 { { 0, 0, 0, 0, 0 } }, 89 { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment 90 static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } }, 91 { { 0, 0, 0, 0, 0 } }, 92 { { 0, 0, 0, 0, 0 } }, 93 { { 0, 0, 0, 0, 0 } }, 94 { { 0, 0, 0, 0, 0 } } } }; // not exist 95 static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } }, 96 { { 0, 0, 0, 0, 0 } }, 97 { { 0, 0, 0, 0, 0 } }, 98 { { 0, 0, 0, 0, 0 } }, 99 { { 0, 0, 0, 0, 0 } } } }; // not exist 100 static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } }, 101 { { 0, 0, 0, 0, 0 } }, 102 { { 0, 0, 0, 0, 0 } }, 103 { { 0, 0, 0, 0, 0 } }, 104 { { 0, 0, 0, 0, 0 } } } }; // not exist 105 static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } }, 106 { { 0, 0, 0, 0, 0 } }, 107 { { 0, 0, 0, 0, 0 } }, 108 { { 0, 0, 0, 0, 0 } }, 109 { { 0, 0, 0, 0, 0 } } } }; // not exist 110 static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } }, 111 { { 0, 0, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers 115 static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0 } }, 118 { { 0, 0, 0, 0, 0 } }, 119 { { 0, 0, 0, 0, 0 } } } }; // not exist 120 static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } }, 121 { { 0, 0, 0, 0, 0 } }, 122 { { 0, 0, 0, 0, 0 } }, 123 { { 0, 0, 0, 0, 0 } }, 124 { { 0, 0, 0, 0, 0 } } } }; // not exist 125 static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0 } } } }; 130 static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0 } }, 132 { { 0, 0, 0, 0, 0 } }, 133 { { 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0 } } } }; 135 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } }, 136 { { 0, 0, 0, 0, 0 } }, 137 { { 0, 0, 0, 0, 0 } }, 138 { { 0, 0, 0, 0, 0 } }, 139 { { 0, 0, 0, 0, 0 } } } }; 140 static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } }, 141 { { 0, 0, 0, 0, 0 } }, 142 { { 0, 0, 0, 0, 0 } }, 143 { { 0, 0, 0, 0, 0 } }, 144 { { 0, 0, 0, 0, 0 } } } }; 145 static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } }, 146 { { 0, 0, 0, 0, 0 } }, 147 { { 0, 0, 0, 0, 0 } }, 148 { { 0, 0, 0, 0, 0 } }, 149 { { 0, 0, 0, 0, 0 } } } }; 150 static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } }, 151 { { 0, 0, 0, 0, 0 } }, 152 { { 0, 0, 0, 0, 0 } }, 153 { { 0, 0, 0, 0, 0 } }, 154 { { 0, 0, 0, 0, 0 } } } }; 155 static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } }, 156 { { 0, 0, 0, 0, 0 } }, 157 { { 0, 0, 0, 0, 0 } }, 158 { { 0, 0, 0, 0, 0 } }, 159 { { 0, 0, 0, 0, 0 } } } }; 160 static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } }, 161 { { 0, 0, 0, 0, 0 } }, 162 { { 0, 0, 0, 0, 0 } }, 163 { { 0, 0, 0, 0, 0 } }, 164 { { 0, 0, 0, 0, 0 } } } }; 165 static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } }, 166 { { 0, 0, 0, 0, 0 } }, 167 { { 0, 0, 0, 0, 0 } }, 168 { { 0, 0, 0, 0, 0 } }, 169 { { 0, 0, 0, 0, 0 } } } }; 170 static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } }, 171 { { 0, 0, 0, 0, 0 } }, 172 { { 0, 0, 0, 0, 0 } }, 173 { { 0, 0, 0, 0, 0 } }, 174 { { 0, 0, 0, 0, 0 } } } }; 175 static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } }, 176 { { 0, 0, 0, 0, 0 } }, 177 { { 0, 0, 0, 0, 0 } }, 178 { { 0, 0, 0, 0, 0 } }, 179 { { 0, 0, 0, 0, 0 } } } }; 180 static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } }, 181 { { 0, 0, 0, 0, 0 } }, 182 { { 0, 0, 0, 0, 0 } }, 183 { { 0, 0, 0, 0, 0 } }, 184 { { 0, 0, 0, 0, 0 } } } }; 185 static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } }, 186 { { 0, 0, 0, 0, 0 } }, 187 { { 0, 0, 0, 0, 0 } }, 188 { { 0, 0, 0, 0, 0 } }, 189 { { 0, 0, 0, 0, 0 } } } }; 190 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } }, 191 { { 0, 0, 0, 0, 0 } }, 192 { { 0, 0, 0, 0, 0 } }, 193 { { 0, 0, 0, 0, 0 } }, 194 { { 0, 0, 0, 0, 0 } } } }; 195 static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } }, 196 { { 0, 0, 0, 0, 0 } }, 197 { { 0, 0, 0, 0, 0 } }, 198 { { 0, 0, 0, 0, 0 } }, 199 { { 0, 0, 0, 0, 0 } } } }; 200 static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } }, 201 { { 0, 0, 0, 0, 0 } }, 202 { { 0, 0, 0, 0, 0 } }, 203 { { 0, 0, 0, 0, 0 } }, 204 { { 0, 0, 0, 0, 0 } } } }; 205 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } }, 206 { { 0x00016E00, 0, 0, 0, 0 } }, 207 { { 0x00017000, 0, 0, 0, 0 } }, 208 { { 0x00017200, 0, 0, 0, 0 } }, 209 { { 0x00017E00, 0, 0, 0, 0 } } } }; 210 static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } }, 211 { { 0, 0, 0, 0, 0 } }, 212 { { 0, 0, 0, 0, 0 } }, 213 { { 0, 0, 0, 0, 0 } }, 214 { { 0, 0, 0, 0, 0 } } } }; 215 216 217 #define NBIF_BASE__INST0_SEG0 0x00000000 218 #define NBIF_BASE__INST0_SEG1 0x00000014 219 #define NBIF_BASE__INST0_SEG2 0x00000D20 220 #define NBIF_BASE__INST0_SEG3 0x00010400 221 #define NBIF_BASE__INST0_SEG4 0 222 223 #define NBIF_BASE__INST1_SEG0 0 224 #define NBIF_BASE__INST1_SEG1 0 225 #define NBIF_BASE__INST1_SEG2 0 226 #define NBIF_BASE__INST1_SEG3 0 227 #define NBIF_BASE__INST1_SEG4 0 228 229 #define NBIF_BASE__INST2_SEG0 0 230 #define NBIF_BASE__INST2_SEG1 0 231 #define NBIF_BASE__INST2_SEG2 0 232 #define NBIF_BASE__INST2_SEG3 0 233 #define NBIF_BASE__INST2_SEG4 0 234 235 #define NBIF_BASE__INST3_SEG0 0 236 #define NBIF_BASE__INST3_SEG1 0 237 #define NBIF_BASE__INST3_SEG2 0 238 #define NBIF_BASE__INST3_SEG3 0 239 #define NBIF_BASE__INST3_SEG4 0 240 241 #define NBIF_BASE__INST4_SEG0 0 242 #define NBIF_BASE__INST4_SEG1 0 243 #define NBIF_BASE__INST4_SEG2 0 244 #define NBIF_BASE__INST4_SEG3 0 245 #define NBIF_BASE__INST4_SEG4 0 246 247 #define NBIO_BASE__INST0_SEG0 0x00000000 248 #define NBIO_BASE__INST0_SEG1 0x00000014 249 #define NBIO_BASE__INST0_SEG2 0x00000D20 250 #define NBIO_BASE__INST0_SEG3 0x00010400 251 #define NBIO_BASE__INST0_SEG4 0 252 253 #define NBIO_BASE__INST1_SEG0 0 254 #define NBIO_BASE__INST1_SEG1 0 255 #define NBIO_BASE__INST1_SEG2 0 256 #define NBIO_BASE__INST1_SEG3 0 257 #define NBIO_BASE__INST1_SEG4 0 258 259 #define NBIO_BASE__INST2_SEG0 0 260 #define NBIO_BASE__INST2_SEG1 0 261 #define NBIO_BASE__INST2_SEG2 0 262 #define NBIO_BASE__INST2_SEG3 0 263 #define NBIO_BASE__INST2_SEG4 0 264 265 #define NBIO_BASE__INST3_SEG0 0 266 #define NBIO_BASE__INST3_SEG1 0 267 #define NBIO_BASE__INST3_SEG2 0 268 #define NBIO_BASE__INST3_SEG3 0 269 #define NBIO_BASE__INST3_SEG4 0 270 271 #define NBIO_BASE__INST4_SEG0 0 272 #define NBIO_BASE__INST4_SEG1 0 273 #define NBIO_BASE__INST4_SEG2 0 274 #define NBIO_BASE__INST4_SEG3 0 275 #define NBIO_BASE__INST4_SEG4 0 276 277 #define DCE_BASE__INST0_SEG0 0x00000012 278 #define DCE_BASE__INST0_SEG1 0x000000C0 279 #define DCE_BASE__INST0_SEG2 0x000034C0 280 #define DCE_BASE__INST0_SEG3 0 281 #define DCE_BASE__INST0_SEG4 0 282 283 #define DCE_BASE__INST1_SEG0 0 284 #define DCE_BASE__INST1_SEG1 0 285 #define DCE_BASE__INST1_SEG2 0 286 #define DCE_BASE__INST1_SEG3 0 287 #define DCE_BASE__INST1_SEG4 0 288 289 #define DCE_BASE__INST2_SEG0 0 290 #define DCE_BASE__INST2_SEG1 0 291 #define DCE_BASE__INST2_SEG2 0 292 #define DCE_BASE__INST2_SEG3 0 293 #define DCE_BASE__INST2_SEG4 0 294 295 #define DCE_BASE__INST3_SEG0 0 296 #define DCE_BASE__INST3_SEG1 0 297 #define DCE_BASE__INST3_SEG2 0 298 #define DCE_BASE__INST3_SEG3 0 299 #define DCE_BASE__INST3_SEG4 0 300 301 #define DCE_BASE__INST4_SEG0 0 302 #define DCE_BASE__INST4_SEG1 0 303 #define DCE_BASE__INST4_SEG2 0 304 #define DCE_BASE__INST4_SEG3 0 305 #define DCE_BASE__INST4_SEG4 0 306 307 #define DCN_BASE__INST0_SEG0 0x00000012 308 #define DCN_BASE__INST0_SEG1 0x000000C0 309 #define DCN_BASE__INST0_SEG2 0x000034C0 310 #define DCN_BASE__INST0_SEG3 0 311 #define DCN_BASE__INST0_SEG4 0 312 313 #define DCN_BASE__INST1_SEG0 0 314 #define DCN_BASE__INST1_SEG1 0 315 #define DCN_BASE__INST1_SEG2 0 316 #define DCN_BASE__INST1_SEG3 0 317 #define DCN_BASE__INST1_SEG4 0 318 319 #define DCN_BASE__INST2_SEG0 0 320 #define DCN_BASE__INST2_SEG1 0 321 #define DCN_BASE__INST2_SEG2 0 322 #define DCN_BASE__INST2_SEG3 0 323 #define DCN_BASE__INST2_SEG4 0 324 325 #define DCN_BASE__INST3_SEG0 0 326 #define DCN_BASE__INST3_SEG1 0 327 #define DCN_BASE__INST3_SEG2 0 328 #define DCN_BASE__INST3_SEG3 0 329 #define DCN_BASE__INST3_SEG4 0 330 331 #define DCN_BASE__INST4_SEG0 0 332 #define DCN_BASE__INST4_SEG1 0 333 #define DCN_BASE__INST4_SEG2 0 334 #define DCN_BASE__INST4_SEG3 0 335 #define DCN_BASE__INST4_SEG4 0 336 337 #define MP0_BASE__INST0_SEG0 0x00016000 338 #define MP0_BASE__INST0_SEG1 0 339 #define MP0_BASE__INST0_SEG2 0 340 #define MP0_BASE__INST0_SEG3 0 341 #define MP0_BASE__INST0_SEG4 0 342 343 #define MP0_BASE__INST1_SEG0 0 344 #define MP0_BASE__INST1_SEG1 0 345 #define MP0_BASE__INST1_SEG2 0 346 #define MP0_BASE__INST1_SEG3 0 347 #define MP0_BASE__INST1_SEG4 0 348 349 #define MP0_BASE__INST2_SEG0 0 350 #define MP0_BASE__INST2_SEG1 0 351 #define MP0_BASE__INST2_SEG2 0 352 #define MP0_BASE__INST2_SEG3 0 353 #define MP0_BASE__INST2_SEG4 0 354 355 #define MP0_BASE__INST3_SEG0 0 356 #define MP0_BASE__INST3_SEG1 0 357 #define MP0_BASE__INST3_SEG2 0 358 #define MP0_BASE__INST3_SEG3 0 359 #define MP0_BASE__INST3_SEG4 0 360 361 #define MP0_BASE__INST4_SEG0 0 362 #define MP0_BASE__INST4_SEG1 0 363 #define MP0_BASE__INST4_SEG2 0 364 #define MP0_BASE__INST4_SEG3 0 365 #define MP0_BASE__INST4_SEG4 0 366 367 #define MP1_BASE__INST0_SEG0 0x00016200 368 #define MP1_BASE__INST0_SEG1 0 369 #define MP1_BASE__INST0_SEG2 0 370 #define MP1_BASE__INST0_SEG3 0 371 #define MP1_BASE__INST0_SEG4 0 372 373 #define MP1_BASE__INST1_SEG0 0 374 #define MP1_BASE__INST1_SEG1 0 375 #define MP1_BASE__INST1_SEG2 0 376 #define MP1_BASE__INST1_SEG3 0 377 #define MP1_BASE__INST1_SEG4 0 378 379 #define MP1_BASE__INST2_SEG0 0 380 #define MP1_BASE__INST2_SEG1 0 381 #define MP1_BASE__INST2_SEG2 0 382 #define MP1_BASE__INST2_SEG3 0 383 #define MP1_BASE__INST2_SEG4 0 384 385 #define MP1_BASE__INST3_SEG0 0 386 #define MP1_BASE__INST3_SEG1 0 387 #define MP1_BASE__INST3_SEG2 0 388 #define MP1_BASE__INST3_SEG3 0 389 #define MP1_BASE__INST3_SEG4 0 390 391 #define MP1_BASE__INST4_SEG0 0 392 #define MP1_BASE__INST4_SEG1 0 393 #define MP1_BASE__INST4_SEG2 0 394 #define MP1_BASE__INST4_SEG3 0 395 #define MP1_BASE__INST4_SEG4 0 396 397 #define MP2_BASE__INST0_SEG0 0x00016400 398 #define MP2_BASE__INST0_SEG1 0 399 #define MP2_BASE__INST0_SEG2 0 400 #define MP2_BASE__INST0_SEG3 0 401 #define MP2_BASE__INST0_SEG4 0 402 403 #define MP2_BASE__INST1_SEG0 0 404 #define MP2_BASE__INST1_SEG1 0 405 #define MP2_BASE__INST1_SEG2 0 406 #define MP2_BASE__INST1_SEG3 0 407 #define MP2_BASE__INST1_SEG4 0 408 409 #define MP2_BASE__INST2_SEG0 0 410 #define MP2_BASE__INST2_SEG1 0 411 #define MP2_BASE__INST2_SEG2 0 412 #define MP2_BASE__INST2_SEG3 0 413 #define MP2_BASE__INST2_SEG4 0 414 415 #define MP2_BASE__INST3_SEG0 0 416 #define MP2_BASE__INST3_SEG1 0 417 #define MP2_BASE__INST3_SEG2 0 418 #define MP2_BASE__INST3_SEG3 0 419 #define MP2_BASE__INST3_SEG4 0 420 421 #define MP2_BASE__INST4_SEG0 0 422 #define MP2_BASE__INST4_SEG1 0 423 #define MP2_BASE__INST4_SEG2 0 424 #define MP2_BASE__INST4_SEG3 0 425 #define MP2_BASE__INST4_SEG4 0 426 427 #define DF_BASE__INST0_SEG0 0x00007000 428 #define DF_BASE__INST0_SEG1 0 429 #define DF_BASE__INST0_SEG2 0 430 #define DF_BASE__INST0_SEG3 0 431 #define DF_BASE__INST0_SEG4 0 432 433 #define DF_BASE__INST1_SEG0 0 434 #define DF_BASE__INST1_SEG1 0 435 #define DF_BASE__INST1_SEG2 0 436 #define DF_BASE__INST1_SEG3 0 437 #define DF_BASE__INST1_SEG4 0 438 439 #define DF_BASE__INST2_SEG0 0 440 #define DF_BASE__INST2_SEG1 0 441 #define DF_BASE__INST2_SEG2 0 442 #define DF_BASE__INST2_SEG3 0 443 #define DF_BASE__INST2_SEG4 0 444 445 #define DF_BASE__INST3_SEG0 0 446 #define DF_BASE__INST3_SEG1 0 447 #define DF_BASE__INST3_SEG2 0 448 #define DF_BASE__INST3_SEG3 0 449 #define DF_BASE__INST3_SEG4 0 450 451 #define DF_BASE__INST4_SEG0 0 452 #define DF_BASE__INST4_SEG1 0 453 #define DF_BASE__INST4_SEG2 0 454 #define DF_BASE__INST4_SEG3 0 455 #define DF_BASE__INST4_SEG4 0 456 457 #define UVD_BASE__INST0_SEG0 0x00007800 458 #define UVD_BASE__INST0_SEG1 0x00007E00 459 #define UVD_BASE__INST0_SEG2 0 460 #define UVD_BASE__INST0_SEG3 0 461 #define UVD_BASE__INST0_SEG4 0 462 463 #define UVD_BASE__INST1_SEG0 0 464 #define UVD_BASE__INST1_SEG1 0 465 #define UVD_BASE__INST1_SEG2 0 466 #define UVD_BASE__INST1_SEG3 0 467 #define UVD_BASE__INST1_SEG4 0 468 469 #define UVD_BASE__INST2_SEG0 0 470 #define UVD_BASE__INST2_SEG1 0 471 #define UVD_BASE__INST2_SEG2 0 472 #define UVD_BASE__INST2_SEG3 0 473 #define UVD_BASE__INST2_SEG4 0 474 475 #define UVD_BASE__INST3_SEG0 0 476 #define UVD_BASE__INST3_SEG1 0 477 #define UVD_BASE__INST3_SEG2 0 478 #define UVD_BASE__INST3_SEG3 0 479 #define UVD_BASE__INST3_SEG4 0 480 481 #define UVD_BASE__INST4_SEG0 0 482 #define UVD_BASE__INST4_SEG1 0 483 #define UVD_BASE__INST4_SEG2 0 484 #define UVD_BASE__INST4_SEG3 0 485 #define UVD_BASE__INST4_SEG4 0 486 487 #define VCN_BASE__INST0_SEG0 0x00007800 488 #define VCN_BASE__INST0_SEG1 0x00007E00 489 #define VCN_BASE__INST0_SEG2 0 490 #define VCN_BASE__INST0_SEG3 0 491 #define VCN_BASE__INST0_SEG4 0 492 493 #define VCN_BASE__INST1_SEG0 0 494 #define VCN_BASE__INST1_SEG1 0 495 #define VCN_BASE__INST1_SEG2 0 496 #define VCN_BASE__INST1_SEG3 0 497 #define VCN_BASE__INST1_SEG4 0 498 499 #define VCN_BASE__INST2_SEG0 0 500 #define VCN_BASE__INST2_SEG1 0 501 #define VCN_BASE__INST2_SEG2 0 502 #define VCN_BASE__INST2_SEG3 0 503 #define VCN_BASE__INST2_SEG4 0 504 505 #define VCN_BASE__INST3_SEG0 0 506 #define VCN_BASE__INST3_SEG1 0 507 #define VCN_BASE__INST3_SEG2 0 508 #define VCN_BASE__INST3_SEG3 0 509 #define VCN_BASE__INST3_SEG4 0 510 511 #define VCN_BASE__INST4_SEG0 0 512 #define VCN_BASE__INST4_SEG1 0 513 #define VCN_BASE__INST4_SEG2 0 514 #define VCN_BASE__INST4_SEG3 0 515 #define VCN_BASE__INST4_SEG4 0 516 517 #define DBGU_BASE__INST0_SEG0 0x00000180 518 #define DBGU_BASE__INST0_SEG1 0x000001A0 519 #define DBGU_BASE__INST0_SEG2 0 520 #define DBGU_BASE__INST0_SEG3 0 521 #define DBGU_BASE__INST0_SEG4 0 522 523 #define DBGU_BASE__INST1_SEG0 0 524 #define DBGU_BASE__INST1_SEG1 0 525 #define DBGU_BASE__INST1_SEG2 0 526 #define DBGU_BASE__INST1_SEG3 0 527 #define DBGU_BASE__INST1_SEG4 0 528 529 #define DBGU_BASE__INST2_SEG0 0 530 #define DBGU_BASE__INST2_SEG1 0 531 #define DBGU_BASE__INST2_SEG2 0 532 #define DBGU_BASE__INST2_SEG3 0 533 #define DBGU_BASE__INST2_SEG4 0 534 535 #define DBGU_BASE__INST3_SEG0 0 536 #define DBGU_BASE__INST3_SEG1 0 537 #define DBGU_BASE__INST3_SEG2 0 538 #define DBGU_BASE__INST3_SEG3 0 539 #define DBGU_BASE__INST3_SEG4 0 540 541 #define DBGU_BASE__INST4_SEG0 0 542 #define DBGU_BASE__INST4_SEG1 0 543 #define DBGU_BASE__INST4_SEG2 0 544 #define DBGU_BASE__INST4_SEG3 0 545 #define DBGU_BASE__INST4_SEG4 0 546 547 #define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0 548 #define DBGU_NBIO_BASE__INST0_SEG1 0 549 #define DBGU_NBIO_BASE__INST0_SEG2 0 550 #define DBGU_NBIO_BASE__INST0_SEG3 0 551 #define DBGU_NBIO_BASE__INST0_SEG4 0 552 553 #define DBGU_NBIO_BASE__INST1_SEG0 0 554 #define DBGU_NBIO_BASE__INST1_SEG1 0 555 #define DBGU_NBIO_BASE__INST1_SEG2 0 556 #define DBGU_NBIO_BASE__INST1_SEG3 0 557 #define DBGU_NBIO_BASE__INST1_SEG4 0 558 559 #define DBGU_NBIO_BASE__INST2_SEG0 0 560 #define DBGU_NBIO_BASE__INST2_SEG1 0 561 #define DBGU_NBIO_BASE__INST2_SEG2 0 562 #define DBGU_NBIO_BASE__INST2_SEG3 0 563 #define DBGU_NBIO_BASE__INST2_SEG4 0 564 565 #define DBGU_NBIO_BASE__INST3_SEG0 0 566 #define DBGU_NBIO_BASE__INST3_SEG1 0 567 #define DBGU_NBIO_BASE__INST3_SEG2 0 568 #define DBGU_NBIO_BASE__INST3_SEG3 0 569 #define DBGU_NBIO_BASE__INST3_SEG4 0 570 571 #define DBGU_NBIO_BASE__INST4_SEG0 0 572 #define DBGU_NBIO_BASE__INST4_SEG1 0 573 #define DBGU_NBIO_BASE__INST4_SEG2 0 574 #define DBGU_NBIO_BASE__INST4_SEG3 0 575 #define DBGU_NBIO_BASE__INST4_SEG4 0 576 577 #define DBGU_IO_BASE__INST0_SEG0 0x000001E0 578 #define DBGU_IO_BASE__INST0_SEG1 0 579 #define DBGU_IO_BASE__INST0_SEG2 0 580 #define DBGU_IO_BASE__INST0_SEG3 0 581 #define DBGU_IO_BASE__INST0_SEG4 0 582 583 #define DBGU_IO_BASE__INST1_SEG0 0 584 #define DBGU_IO_BASE__INST1_SEG1 0 585 #define DBGU_IO_BASE__INST1_SEG2 0 586 #define DBGU_IO_BASE__INST1_SEG3 0 587 #define DBGU_IO_BASE__INST1_SEG4 0 588 589 #define DBGU_IO_BASE__INST2_SEG0 0 590 #define DBGU_IO_BASE__INST2_SEG1 0 591 #define DBGU_IO_BASE__INST2_SEG2 0 592 #define DBGU_IO_BASE__INST2_SEG3 0 593 #define DBGU_IO_BASE__INST2_SEG4 0 594 595 #define DBGU_IO_BASE__INST3_SEG0 0 596 #define DBGU_IO_BASE__INST3_SEG1 0 597 #define DBGU_IO_BASE__INST3_SEG2 0 598 #define DBGU_IO_BASE__INST3_SEG3 0 599 #define DBGU_IO_BASE__INST3_SEG4 0 600 601 #define DBGU_IO_BASE__INST4_SEG0 0 602 #define DBGU_IO_BASE__INST4_SEG1 0 603 #define DBGU_IO_BASE__INST4_SEG2 0 604 #define DBGU_IO_BASE__INST4_SEG3 0 605 #define DBGU_IO_BASE__INST4_SEG4 0 606 607 #define DFX_DAP_BASE__INST0_SEG0 0x000005A0 608 #define DFX_DAP_BASE__INST0_SEG1 0 609 #define DFX_DAP_BASE__INST0_SEG2 0 610 #define DFX_DAP_BASE__INST0_SEG3 0 611 #define DFX_DAP_BASE__INST0_SEG4 0 612 613 #define DFX_DAP_BASE__INST1_SEG0 0 614 #define DFX_DAP_BASE__INST1_SEG1 0 615 #define DFX_DAP_BASE__INST1_SEG2 0 616 #define DFX_DAP_BASE__INST1_SEG3 0 617 #define DFX_DAP_BASE__INST1_SEG4 0 618 619 #define DFX_DAP_BASE__INST2_SEG0 0 620 #define DFX_DAP_BASE__INST2_SEG1 0 621 #define DFX_DAP_BASE__INST2_SEG2 0 622 #define DFX_DAP_BASE__INST2_SEG3 0 623 #define DFX_DAP_BASE__INST2_SEG4 0 624 625 #define DFX_DAP_BASE__INST3_SEG0 0 626 #define DFX_DAP_BASE__INST3_SEG1 0 627 #define DFX_DAP_BASE__INST3_SEG2 0 628 #define DFX_DAP_BASE__INST3_SEG3 0 629 #define DFX_DAP_BASE__INST3_SEG4 0 630 631 #define DFX_DAP_BASE__INST4_SEG0 0 632 #define DFX_DAP_BASE__INST4_SEG1 0 633 #define DFX_DAP_BASE__INST4_SEG2 0 634 #define DFX_DAP_BASE__INST4_SEG3 0 635 #define DFX_DAP_BASE__INST4_SEG4 0 636 637 #define DFX_BASE__INST0_SEG0 0x00000580 638 #define DFX_BASE__INST0_SEG1 0 639 #define DFX_BASE__INST0_SEG2 0 640 #define DFX_BASE__INST0_SEG3 0 641 #define DFX_BASE__INST0_SEG4 0 642 643 #define DFX_BASE__INST1_SEG0 0 644 #define DFX_BASE__INST1_SEG1 0 645 #define DFX_BASE__INST1_SEG2 0 646 #define DFX_BASE__INST1_SEG3 0 647 #define DFX_BASE__INST1_SEG4 0 648 649 #define DFX_BASE__INST2_SEG0 0 650 #define DFX_BASE__INST2_SEG1 0 651 #define DFX_BASE__INST2_SEG2 0 652 #define DFX_BASE__INST2_SEG3 0 653 #define DFX_BASE__INST2_SEG4 0 654 655 #define DFX_BASE__INST3_SEG0 0 656 #define DFX_BASE__INST3_SEG1 0 657 #define DFX_BASE__INST3_SEG2 0 658 #define DFX_BASE__INST3_SEG3 0 659 #define DFX_BASE__INST3_SEG4 0 660 661 #define DFX_BASE__INST4_SEG0 0 662 #define DFX_BASE__INST4_SEG1 0 663 #define DFX_BASE__INST4_SEG2 0 664 #define DFX_BASE__INST4_SEG3 0 665 #define DFX_BASE__INST4_SEG4 0 666 667 #define ISP_BASE__INST0_SEG0 0x00018000 668 #define ISP_BASE__INST0_SEG1 0 669 #define ISP_BASE__INST0_SEG2 0 670 #define ISP_BASE__INST0_SEG3 0 671 #define ISP_BASE__INST0_SEG4 0 672 673 #define ISP_BASE__INST1_SEG0 0 674 #define ISP_BASE__INST1_SEG1 0 675 #define ISP_BASE__INST1_SEG2 0 676 #define ISP_BASE__INST1_SEG3 0 677 #define ISP_BASE__INST1_SEG4 0 678 679 #define ISP_BASE__INST2_SEG0 0 680 #define ISP_BASE__INST2_SEG1 0 681 #define ISP_BASE__INST2_SEG2 0 682 #define ISP_BASE__INST2_SEG3 0 683 #define ISP_BASE__INST2_SEG4 0 684 685 #define ISP_BASE__INST3_SEG0 0 686 #define ISP_BASE__INST3_SEG1 0 687 #define ISP_BASE__INST3_SEG2 0 688 #define ISP_BASE__INST3_SEG3 0 689 #define ISP_BASE__INST3_SEG4 0 690 691 #define ISP_BASE__INST4_SEG0 0 692 #define ISP_BASE__INST4_SEG1 0 693 #define ISP_BASE__INST4_SEG2 0 694 #define ISP_BASE__INST4_SEG3 0 695 #define ISP_BASE__INST4_SEG4 0 696 697 #define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0 698 #define SYSTEMHUB_BASE__INST0_SEG1 0 699 #define SYSTEMHUB_BASE__INST0_SEG2 0 700 #define SYSTEMHUB_BASE__INST0_SEG3 0 701 #define SYSTEMHUB_BASE__INST0_SEG4 0 702 703 #define SYSTEMHUB_BASE__INST1_SEG0 0 704 #define SYSTEMHUB_BASE__INST1_SEG1 0 705 #define SYSTEMHUB_BASE__INST1_SEG2 0 706 #define SYSTEMHUB_BASE__INST1_SEG3 0 707 #define SYSTEMHUB_BASE__INST1_SEG4 0 708 709 #define SYSTEMHUB_BASE__INST2_SEG0 0 710 #define SYSTEMHUB_BASE__INST2_SEG1 0 711 #define SYSTEMHUB_BASE__INST2_SEG2 0 712 #define SYSTEMHUB_BASE__INST2_SEG3 0 713 #define SYSTEMHUB_BASE__INST2_SEG4 0 714 715 #define SYSTEMHUB_BASE__INST3_SEG0 0 716 #define SYSTEMHUB_BASE__INST3_SEG1 0 717 #define SYSTEMHUB_BASE__INST3_SEG2 0 718 #define SYSTEMHUB_BASE__INST3_SEG3 0 719 #define SYSTEMHUB_BASE__INST3_SEG4 0 720 721 #define SYSTEMHUB_BASE__INST4_SEG0 0 722 #define SYSTEMHUB_BASE__INST4_SEG1 0 723 #define SYSTEMHUB_BASE__INST4_SEG2 0 724 #define SYSTEMHUB_BASE__INST4_SEG3 0 725 #define SYSTEMHUB_BASE__INST4_SEG4 0 726 727 #define L2IMU_BASE__INST0_SEG0 0x00007DC0 728 #define L2IMU_BASE__INST0_SEG1 0 729 #define L2IMU_BASE__INST0_SEG2 0 730 #define L2IMU_BASE__INST0_SEG3 0 731 #define L2IMU_BASE__INST0_SEG4 0 732 733 #define L2IMU_BASE__INST1_SEG0 0 734 #define L2IMU_BASE__INST1_SEG1 0 735 #define L2IMU_BASE__INST1_SEG2 0 736 #define L2IMU_BASE__INST1_SEG3 0 737 #define L2IMU_BASE__INST1_SEG4 0 738 739 #define L2IMU_BASE__INST2_SEG0 0 740 #define L2IMU_BASE__INST2_SEG1 0 741 #define L2IMU_BASE__INST2_SEG2 0 742 #define L2IMU_BASE__INST2_SEG3 0 743 #define L2IMU_BASE__INST2_SEG4 0 744 745 #define L2IMU_BASE__INST3_SEG0 0 746 #define L2IMU_BASE__INST3_SEG1 0 747 #define L2IMU_BASE__INST3_SEG2 0 748 #define L2IMU_BASE__INST3_SEG3 0 749 #define L2IMU_BASE__INST3_SEG4 0 750 751 #define L2IMU_BASE__INST4_SEG0 0 752 #define L2IMU_BASE__INST4_SEG1 0 753 #define L2IMU_BASE__INST4_SEG2 0 754 #define L2IMU_BASE__INST4_SEG3 0 755 #define L2IMU_BASE__INST4_SEG4 0 756 757 #define IOHC_BASE__INST0_SEG0 0x00010000 758 #define IOHC_BASE__INST0_SEG1 0 759 #define IOHC_BASE__INST0_SEG2 0 760 #define IOHC_BASE__INST0_SEG3 0 761 #define IOHC_BASE__INST0_SEG4 0 762 763 #define IOHC_BASE__INST1_SEG0 0 764 #define IOHC_BASE__INST1_SEG1 0 765 #define IOHC_BASE__INST1_SEG2 0 766 #define IOHC_BASE__INST1_SEG3 0 767 #define IOHC_BASE__INST1_SEG4 0 768 769 #define IOHC_BASE__INST2_SEG0 0 770 #define IOHC_BASE__INST2_SEG1 0 771 #define IOHC_BASE__INST2_SEG2 0 772 #define IOHC_BASE__INST2_SEG3 0 773 #define IOHC_BASE__INST2_SEG4 0 774 775 #define IOHC_BASE__INST3_SEG0 0 776 #define IOHC_BASE__INST3_SEG1 0 777 #define IOHC_BASE__INST3_SEG2 0 778 #define IOHC_BASE__INST3_SEG3 0 779 #define IOHC_BASE__INST3_SEG4 0 780 781 #define IOHC_BASE__INST4_SEG0 0 782 #define IOHC_BASE__INST4_SEG1 0 783 #define IOHC_BASE__INST4_SEG2 0 784 #define IOHC_BASE__INST4_SEG3 0 785 #define IOHC_BASE__INST4_SEG4 0 786 787 #define ATHUB_BASE__INST0_SEG0 0x00000C20 788 #define ATHUB_BASE__INST0_SEG1 0 789 #define ATHUB_BASE__INST0_SEG2 0 790 #define ATHUB_BASE__INST0_SEG3 0 791 #define ATHUB_BASE__INST0_SEG4 0 792 793 #define ATHUB_BASE__INST1_SEG0 0 794 #define ATHUB_BASE__INST1_SEG1 0 795 #define ATHUB_BASE__INST1_SEG2 0 796 #define ATHUB_BASE__INST1_SEG3 0 797 #define ATHUB_BASE__INST1_SEG4 0 798 799 #define ATHUB_BASE__INST2_SEG0 0 800 #define ATHUB_BASE__INST2_SEG1 0 801 #define ATHUB_BASE__INST2_SEG2 0 802 #define ATHUB_BASE__INST2_SEG3 0 803 #define ATHUB_BASE__INST2_SEG4 0 804 805 #define ATHUB_BASE__INST3_SEG0 0 806 #define ATHUB_BASE__INST3_SEG1 0 807 #define ATHUB_BASE__INST3_SEG2 0 808 #define ATHUB_BASE__INST3_SEG3 0 809 #define ATHUB_BASE__INST3_SEG4 0 810 811 #define ATHUB_BASE__INST4_SEG0 0 812 #define ATHUB_BASE__INST4_SEG1 0 813 #define ATHUB_BASE__INST4_SEG2 0 814 #define ATHUB_BASE__INST4_SEG3 0 815 #define ATHUB_BASE__INST4_SEG4 0 816 817 #define VCE_BASE__INST0_SEG0 0x00007E00 818 #define VCE_BASE__INST0_SEG1 0x00048800 819 #define VCE_BASE__INST0_SEG2 0 820 #define VCE_BASE__INST0_SEG3 0 821 #define VCE_BASE__INST0_SEG4 0 822 823 #define VCE_BASE__INST1_SEG0 0 824 #define VCE_BASE__INST1_SEG1 0 825 #define VCE_BASE__INST1_SEG2 0 826 #define VCE_BASE__INST1_SEG3 0 827 #define VCE_BASE__INST1_SEG4 0 828 829 #define VCE_BASE__INST2_SEG0 0 830 #define VCE_BASE__INST2_SEG1 0 831 #define VCE_BASE__INST2_SEG2 0 832 #define VCE_BASE__INST2_SEG3 0 833 #define VCE_BASE__INST2_SEG4 0 834 835 #define VCE_BASE__INST3_SEG0 0 836 #define VCE_BASE__INST3_SEG1 0 837 #define VCE_BASE__INST3_SEG2 0 838 #define VCE_BASE__INST3_SEG3 0 839 #define VCE_BASE__INST3_SEG4 0 840 841 #define VCE_BASE__INST4_SEG0 0 842 #define VCE_BASE__INST4_SEG1 0 843 #define VCE_BASE__INST4_SEG2 0 844 #define VCE_BASE__INST4_SEG3 0 845 #define VCE_BASE__INST4_SEG4 0 846 847 #define GC_BASE__INST0_SEG0 0x00002000 848 #define GC_BASE__INST0_SEG1 0x0000A000 849 #define GC_BASE__INST0_SEG2 0 850 #define GC_BASE__INST0_SEG3 0 851 #define GC_BASE__INST0_SEG4 0 852 853 #define GC_BASE__INST1_SEG0 0 854 #define GC_BASE__INST1_SEG1 0 855 #define GC_BASE__INST1_SEG2 0 856 #define GC_BASE__INST1_SEG3 0 857 #define GC_BASE__INST1_SEG4 0 858 859 #define GC_BASE__INST2_SEG0 0 860 #define GC_BASE__INST2_SEG1 0 861 #define GC_BASE__INST2_SEG2 0 862 #define GC_BASE__INST2_SEG3 0 863 #define GC_BASE__INST2_SEG4 0 864 865 #define GC_BASE__INST3_SEG0 0 866 #define GC_BASE__INST3_SEG1 0 867 #define GC_BASE__INST3_SEG2 0 868 #define GC_BASE__INST3_SEG3 0 869 #define GC_BASE__INST3_SEG4 0 870 871 #define GC_BASE__INST4_SEG0 0 872 #define GC_BASE__INST4_SEG1 0 873 #define GC_BASE__INST4_SEG2 0 874 #define GC_BASE__INST4_SEG3 0 875 #define GC_BASE__INST4_SEG4 0 876 877 #define MMHUB_BASE__INST0_SEG0 0x0001A000 878 #define MMHUB_BASE__INST0_SEG1 0 879 #define MMHUB_BASE__INST0_SEG2 0 880 #define MMHUB_BASE__INST0_SEG3 0 881 #define MMHUB_BASE__INST0_SEG4 0 882 883 #define MMHUB_BASE__INST1_SEG0 0 884 #define MMHUB_BASE__INST1_SEG1 0 885 #define MMHUB_BASE__INST1_SEG2 0 886 #define MMHUB_BASE__INST1_SEG3 0 887 #define MMHUB_BASE__INST1_SEG4 0 888 889 #define MMHUB_BASE__INST2_SEG0 0 890 #define MMHUB_BASE__INST2_SEG1 0 891 #define MMHUB_BASE__INST2_SEG2 0 892 #define MMHUB_BASE__INST2_SEG3 0 893 #define MMHUB_BASE__INST2_SEG4 0 894 895 #define MMHUB_BASE__INST3_SEG0 0 896 #define MMHUB_BASE__INST3_SEG1 0 897 #define MMHUB_BASE__INST3_SEG2 0 898 #define MMHUB_BASE__INST3_SEG3 0 899 #define MMHUB_BASE__INST3_SEG4 0 900 901 #define MMHUB_BASE__INST4_SEG0 0 902 #define MMHUB_BASE__INST4_SEG1 0 903 #define MMHUB_BASE__INST4_SEG2 0 904 #define MMHUB_BASE__INST4_SEG3 0 905 #define MMHUB_BASE__INST4_SEG4 0 906 907 #define RSMU_BASE__INST0_SEG0 0x00012000 908 #define RSMU_BASE__INST0_SEG1 0 909 #define RSMU_BASE__INST0_SEG2 0 910 #define RSMU_BASE__INST0_SEG3 0 911 #define RSMU_BASE__INST0_SEG4 0 912 913 #define RSMU_BASE__INST1_SEG0 0 914 #define RSMU_BASE__INST1_SEG1 0 915 #define RSMU_BASE__INST1_SEG2 0 916 #define RSMU_BASE__INST1_SEG3 0 917 #define RSMU_BASE__INST1_SEG4 0 918 919 #define RSMU_BASE__INST2_SEG0 0 920 #define RSMU_BASE__INST2_SEG1 0 921 #define RSMU_BASE__INST2_SEG2 0 922 #define RSMU_BASE__INST2_SEG3 0 923 #define RSMU_BASE__INST2_SEG4 0 924 925 #define RSMU_BASE__INST3_SEG0 0 926 #define RSMU_BASE__INST3_SEG1 0 927 #define RSMU_BASE__INST3_SEG2 0 928 #define RSMU_BASE__INST3_SEG3 0 929 #define RSMU_BASE__INST3_SEG4 0 930 931 #define RSMU_BASE__INST4_SEG0 0 932 #define RSMU_BASE__INST4_SEG1 0 933 #define RSMU_BASE__INST4_SEG2 0 934 #define RSMU_BASE__INST4_SEG3 0 935 #define RSMU_BASE__INST4_SEG4 0 936 937 #define HDP_BASE__INST0_SEG0 0x00000F20 938 #define HDP_BASE__INST0_SEG1 0 939 #define HDP_BASE__INST0_SEG2 0 940 #define HDP_BASE__INST0_SEG3 0 941 #define HDP_BASE__INST0_SEG4 0 942 943 #define HDP_BASE__INST1_SEG0 0 944 #define HDP_BASE__INST1_SEG1 0 945 #define HDP_BASE__INST1_SEG2 0 946 #define HDP_BASE__INST1_SEG3 0 947 #define HDP_BASE__INST1_SEG4 0 948 949 #define HDP_BASE__INST2_SEG0 0 950 #define HDP_BASE__INST2_SEG1 0 951 #define HDP_BASE__INST2_SEG2 0 952 #define HDP_BASE__INST2_SEG3 0 953 #define HDP_BASE__INST2_SEG4 0 954 955 #define HDP_BASE__INST3_SEG0 0 956 #define HDP_BASE__INST3_SEG1 0 957 #define HDP_BASE__INST3_SEG2 0 958 #define HDP_BASE__INST3_SEG3 0 959 #define HDP_BASE__INST3_SEG4 0 960 961 #define HDP_BASE__INST4_SEG0 0 962 #define HDP_BASE__INST4_SEG1 0 963 #define HDP_BASE__INST4_SEG2 0 964 #define HDP_BASE__INST4_SEG3 0 965 #define HDP_BASE__INST4_SEG4 0 966 967 #define OSSSYS_BASE__INST0_SEG0 0x000010A0 968 #define OSSSYS_BASE__INST0_SEG1 0 969 #define OSSSYS_BASE__INST0_SEG2 0 970 #define OSSSYS_BASE__INST0_SEG3 0 971 #define OSSSYS_BASE__INST0_SEG4 0 972 973 #define OSSSYS_BASE__INST1_SEG0 0 974 #define OSSSYS_BASE__INST1_SEG1 0 975 #define OSSSYS_BASE__INST1_SEG2 0 976 #define OSSSYS_BASE__INST1_SEG3 0 977 #define OSSSYS_BASE__INST1_SEG4 0 978 979 #define OSSSYS_BASE__INST2_SEG0 0 980 #define OSSSYS_BASE__INST2_SEG1 0 981 #define OSSSYS_BASE__INST2_SEG2 0 982 #define OSSSYS_BASE__INST2_SEG3 0 983 #define OSSSYS_BASE__INST2_SEG4 0 984 985 #define OSSSYS_BASE__INST3_SEG0 0 986 #define OSSSYS_BASE__INST3_SEG1 0 987 #define OSSSYS_BASE__INST3_SEG2 0 988 #define OSSSYS_BASE__INST3_SEG3 0 989 #define OSSSYS_BASE__INST3_SEG4 0 990 991 #define OSSSYS_BASE__INST4_SEG0 0 992 #define OSSSYS_BASE__INST4_SEG1 0 993 #define OSSSYS_BASE__INST4_SEG2 0 994 #define OSSSYS_BASE__INST4_SEG3 0 995 #define OSSSYS_BASE__INST4_SEG4 0 996 997 #define SDMA0_BASE__INST0_SEG0 0x00001260 998 #define SDMA0_BASE__INST0_SEG1 0 999 #define SDMA0_BASE__INST0_SEG2 0 1000 #define SDMA0_BASE__INST0_SEG3 0 1001 #define SDMA0_BASE__INST0_SEG4 0 1002 1003 #define SDMA0_BASE__INST1_SEG0 0 1004 #define SDMA0_BASE__INST1_SEG1 0 1005 #define SDMA0_BASE__INST1_SEG2 0 1006 #define SDMA0_BASE__INST1_SEG3 0 1007 #define SDMA0_BASE__INST1_SEG4 0 1008 1009 #define SDMA0_BASE__INST2_SEG0 0 1010 #define SDMA0_BASE__INST2_SEG1 0 1011 #define SDMA0_BASE__INST2_SEG2 0 1012 #define SDMA0_BASE__INST2_SEG3 0 1013 #define SDMA0_BASE__INST2_SEG4 0 1014 1015 #define SDMA0_BASE__INST3_SEG0 0 1016 #define SDMA0_BASE__INST3_SEG1 0 1017 #define SDMA0_BASE__INST3_SEG2 0 1018 #define SDMA0_BASE__INST3_SEG3 0 1019 #define SDMA0_BASE__INST3_SEG4 0 1020 1021 #define SDMA0_BASE__INST4_SEG0 0 1022 #define SDMA0_BASE__INST4_SEG1 0 1023 #define SDMA0_BASE__INST4_SEG2 0 1024 #define SDMA0_BASE__INST4_SEG3 0 1025 #define SDMA0_BASE__INST4_SEG4 0 1026 1027 #define SDMA1_BASE__INST0_SEG0 0x00001460 1028 #define SDMA1_BASE__INST0_SEG1 0 1029 #define SDMA1_BASE__INST0_SEG2 0 1030 #define SDMA1_BASE__INST0_SEG3 0 1031 #define SDMA1_BASE__INST0_SEG4 0 1032 1033 #define SDMA1_BASE__INST1_SEG0 0 1034 #define SDMA1_BASE__INST1_SEG1 0 1035 #define SDMA1_BASE__INST1_SEG2 0 1036 #define SDMA1_BASE__INST1_SEG3 0 1037 #define SDMA1_BASE__INST1_SEG4 0 1038 1039 #define SDMA1_BASE__INST2_SEG0 0 1040 #define SDMA1_BASE__INST2_SEG1 0 1041 #define SDMA1_BASE__INST2_SEG2 0 1042 #define SDMA1_BASE__INST2_SEG3 0 1043 #define SDMA1_BASE__INST2_SEG4 0 1044 1045 #define SDMA1_BASE__INST3_SEG0 0 1046 #define SDMA1_BASE__INST3_SEG1 0 1047 #define SDMA1_BASE__INST3_SEG2 0 1048 #define SDMA1_BASE__INST3_SEG3 0 1049 #define SDMA1_BASE__INST3_SEG4 0 1050 1051 #define SDMA1_BASE__INST4_SEG0 0 1052 #define SDMA1_BASE__INST4_SEG1 0 1053 #define SDMA1_BASE__INST4_SEG2 0 1054 #define SDMA1_BASE__INST4_SEG3 0 1055 #define SDMA1_BASE__INST4_SEG4 0 1056 1057 #define XDMA_BASE__INST0_SEG0 0x00003400 1058 #define XDMA_BASE__INST0_SEG1 0 1059 #define XDMA_BASE__INST0_SEG2 0 1060 #define XDMA_BASE__INST0_SEG3 0 1061 #define XDMA_BASE__INST0_SEG4 0 1062 1063 #define XDMA_BASE__INST1_SEG0 0 1064 #define XDMA_BASE__INST1_SEG1 0 1065 #define XDMA_BASE__INST1_SEG2 0 1066 #define XDMA_BASE__INST1_SEG3 0 1067 #define XDMA_BASE__INST1_SEG4 0 1068 1069 #define XDMA_BASE__INST2_SEG0 0 1070 #define XDMA_BASE__INST2_SEG1 0 1071 #define XDMA_BASE__INST2_SEG2 0 1072 #define XDMA_BASE__INST2_SEG3 0 1073 #define XDMA_BASE__INST2_SEG4 0 1074 1075 #define XDMA_BASE__INST3_SEG0 0 1076 #define XDMA_BASE__INST3_SEG1 0 1077 #define XDMA_BASE__INST3_SEG2 0 1078 #define XDMA_BASE__INST3_SEG3 0 1079 #define XDMA_BASE__INST3_SEG4 0 1080 1081 #define XDMA_BASE__INST4_SEG0 0 1082 #define XDMA_BASE__INST4_SEG1 0 1083 #define XDMA_BASE__INST4_SEG2 0 1084 #define XDMA_BASE__INST4_SEG3 0 1085 #define XDMA_BASE__INST4_SEG4 0 1086 1087 #define UMC_BASE__INST0_SEG0 0x00014000 1088 #define UMC_BASE__INST0_SEG1 0 1089 #define UMC_BASE__INST0_SEG2 0 1090 #define UMC_BASE__INST0_SEG3 0 1091 #define UMC_BASE__INST0_SEG4 0 1092 1093 #define UMC_BASE__INST1_SEG0 0 1094 #define UMC_BASE__INST1_SEG1 0 1095 #define UMC_BASE__INST1_SEG2 0 1096 #define UMC_BASE__INST1_SEG3 0 1097 #define UMC_BASE__INST1_SEG4 0 1098 1099 #define UMC_BASE__INST2_SEG0 0 1100 #define UMC_BASE__INST2_SEG1 0 1101 #define UMC_BASE__INST2_SEG2 0 1102 #define UMC_BASE__INST2_SEG3 0 1103 #define UMC_BASE__INST2_SEG4 0 1104 1105 #define UMC_BASE__INST3_SEG0 0 1106 #define UMC_BASE__INST3_SEG1 0 1107 #define UMC_BASE__INST3_SEG2 0 1108 #define UMC_BASE__INST3_SEG3 0 1109 #define UMC_BASE__INST3_SEG4 0 1110 1111 #define UMC_BASE__INST4_SEG0 0 1112 #define UMC_BASE__INST4_SEG1 0 1113 #define UMC_BASE__INST4_SEG2 0 1114 #define UMC_BASE__INST4_SEG3 0 1115 #define UMC_BASE__INST4_SEG4 0 1116 1117 #define THM_BASE__INST0_SEG0 0x00016600 1118 #define THM_BASE__INST0_SEG1 0 1119 #define THM_BASE__INST0_SEG2 0 1120 #define THM_BASE__INST0_SEG3 0 1121 #define THM_BASE__INST0_SEG4 0 1122 1123 #define THM_BASE__INST1_SEG0 0 1124 #define THM_BASE__INST1_SEG1 0 1125 #define THM_BASE__INST1_SEG2 0 1126 #define THM_BASE__INST1_SEG3 0 1127 #define THM_BASE__INST1_SEG4 0 1128 1129 #define THM_BASE__INST2_SEG0 0 1130 #define THM_BASE__INST2_SEG1 0 1131 #define THM_BASE__INST2_SEG2 0 1132 #define THM_BASE__INST2_SEG3 0 1133 #define THM_BASE__INST2_SEG4 0 1134 1135 #define THM_BASE__INST3_SEG0 0 1136 #define THM_BASE__INST3_SEG1 0 1137 #define THM_BASE__INST3_SEG2 0 1138 #define THM_BASE__INST3_SEG3 0 1139 #define THM_BASE__INST3_SEG4 0 1140 1141 #define THM_BASE__INST4_SEG0 0 1142 #define THM_BASE__INST4_SEG1 0 1143 #define THM_BASE__INST4_SEG2 0 1144 #define THM_BASE__INST4_SEG3 0 1145 #define THM_BASE__INST4_SEG4 0 1146 1147 #define SMUIO_BASE__INST0_SEG0 0x00016800 1148 #define SMUIO_BASE__INST0_SEG1 0 1149 #define SMUIO_BASE__INST0_SEG2 0 1150 #define SMUIO_BASE__INST0_SEG3 0 1151 #define SMUIO_BASE__INST0_SEG4 0 1152 1153 #define SMUIO_BASE__INST1_SEG0 0 1154 #define SMUIO_BASE__INST1_SEG1 0 1155 #define SMUIO_BASE__INST1_SEG2 0 1156 #define SMUIO_BASE__INST1_SEG3 0 1157 #define SMUIO_BASE__INST1_SEG4 0 1158 1159 #define SMUIO_BASE__INST2_SEG0 0 1160 #define SMUIO_BASE__INST2_SEG1 0 1161 #define SMUIO_BASE__INST2_SEG2 0 1162 #define SMUIO_BASE__INST2_SEG3 0 1163 #define SMUIO_BASE__INST2_SEG4 0 1164 1165 #define SMUIO_BASE__INST3_SEG0 0 1166 #define SMUIO_BASE__INST3_SEG1 0 1167 #define SMUIO_BASE__INST3_SEG2 0 1168 #define SMUIO_BASE__INST3_SEG3 0 1169 #define SMUIO_BASE__INST3_SEG4 0 1170 1171 #define SMUIO_BASE__INST4_SEG0 0 1172 #define SMUIO_BASE__INST4_SEG1 0 1173 #define SMUIO_BASE__INST4_SEG2 0 1174 #define SMUIO_BASE__INST4_SEG3 0 1175 #define SMUIO_BASE__INST4_SEG4 0 1176 1177 #define PWR_BASE__INST0_SEG0 0x00016A00 1178 #define PWR_BASE__INST0_SEG1 0 1179 #define PWR_BASE__INST0_SEG2 0 1180 #define PWR_BASE__INST0_SEG3 0 1181 #define PWR_BASE__INST0_SEG4 0 1182 1183 #define PWR_BASE__INST1_SEG0 0 1184 #define PWR_BASE__INST1_SEG1 0 1185 #define PWR_BASE__INST1_SEG2 0 1186 #define PWR_BASE__INST1_SEG3 0 1187 #define PWR_BASE__INST1_SEG4 0 1188 1189 #define PWR_BASE__INST2_SEG0 0 1190 #define PWR_BASE__INST2_SEG1 0 1191 #define PWR_BASE__INST2_SEG2 0 1192 #define PWR_BASE__INST2_SEG3 0 1193 #define PWR_BASE__INST2_SEG4 0 1194 1195 #define PWR_BASE__INST3_SEG0 0 1196 #define PWR_BASE__INST3_SEG1 0 1197 #define PWR_BASE__INST3_SEG2 0 1198 #define PWR_BASE__INST3_SEG3 0 1199 #define PWR_BASE__INST3_SEG4 0 1200 1201 #define PWR_BASE__INST4_SEG0 0 1202 #define PWR_BASE__INST4_SEG1 0 1203 #define PWR_BASE__INST4_SEG2 0 1204 #define PWR_BASE__INST4_SEG3 0 1205 #define PWR_BASE__INST4_SEG4 0 1206 1207 #define CLK_BASE__INST0_SEG0 0x00016C00 1208 #define CLK_BASE__INST0_SEG1 0 1209 #define CLK_BASE__INST0_SEG2 0 1210 #define CLK_BASE__INST0_SEG3 0 1211 #define CLK_BASE__INST0_SEG4 0 1212 1213 #define CLK_BASE__INST1_SEG0 0x00016E00 1214 #define CLK_BASE__INST1_SEG1 0 1215 #define CLK_BASE__INST1_SEG2 0 1216 #define CLK_BASE__INST1_SEG3 0 1217 #define CLK_BASE__INST1_SEG4 0 1218 1219 #define CLK_BASE__INST2_SEG0 0x00017000 1220 #define CLK_BASE__INST2_SEG1 0 1221 #define CLK_BASE__INST2_SEG2 0 1222 #define CLK_BASE__INST2_SEG3 0 1223 #define CLK_BASE__INST2_SEG4 0 1224 1225 #define CLK_BASE__INST3_SEG0 0x00017200 1226 #define CLK_BASE__INST3_SEG1 0 1227 #define CLK_BASE__INST3_SEG2 0 1228 #define CLK_BASE__INST3_SEG3 0 1229 #define CLK_BASE__INST3_SEG4 0 1230 1231 #define CLK_BASE__INST4_SEG0 0x00017E00 1232 #define CLK_BASE__INST4_SEG1 0 1233 #define CLK_BASE__INST4_SEG2 0 1234 #define CLK_BASE__INST4_SEG3 0 1235 #define CLK_BASE__INST4_SEG4 0 1236 1237 #define FUSE_BASE__INST0_SEG0 0x00017400 1238 #define FUSE_BASE__INST0_SEG1 0 1239 #define FUSE_BASE__INST0_SEG2 0 1240 #define FUSE_BASE__INST0_SEG3 0 1241 #define FUSE_BASE__INST0_SEG4 0 1242 1243 #define FUSE_BASE__INST1_SEG0 0 1244 #define FUSE_BASE__INST1_SEG1 0 1245 #define FUSE_BASE__INST1_SEG2 0 1246 #define FUSE_BASE__INST1_SEG3 0 1247 #define FUSE_BASE__INST1_SEG4 0 1248 1249 #define FUSE_BASE__INST2_SEG0 0 1250 #define FUSE_BASE__INST2_SEG1 0 1251 #define FUSE_BASE__INST2_SEG2 0 1252 #define FUSE_BASE__INST2_SEG3 0 1253 #define FUSE_BASE__INST2_SEG4 0 1254 1255 #define FUSE_BASE__INST3_SEG0 0 1256 #define FUSE_BASE__INST3_SEG1 0 1257 #define FUSE_BASE__INST3_SEG2 0 1258 #define FUSE_BASE__INST3_SEG3 0 1259 #define FUSE_BASE__INST3_SEG4 0 1260 1261 #define FUSE_BASE__INST4_SEG0 0 1262 #define FUSE_BASE__INST4_SEG1 0 1263 #define FUSE_BASE__INST4_SEG2 0 1264 #define FUSE_BASE__INST4_SEG3 0 1265 #define FUSE_BASE__INST4_SEG4 0 1266 #endif 1267 1268
Indexes created Sat Sep 20 22:09:52 GMT 2025