1 /* $NetBSD: smu71_discrete.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef SMU71_DISCRETE_H 26 #define SMU71_DISCRETE_H 27 28 #include "smu71.h" 29 30 #if !defined(SMC_MICROCODE) 31 #pragma pack(push, 1) 32 #endif 33 34 #define VDDC_ON_SVI2 0x1 35 #define VDDCI_ON_SVI2 0x2 36 #define MVDD_ON_SVI2 0x4 37 38 struct SMU71_Discrete_VoltageLevel 39 { 40 uint16_t Voltage; 41 uint16_t StdVoltageHiSidd; 42 uint16_t StdVoltageLoSidd; 43 uint8_t Smio; 44 uint8_t padding; 45 }; 46 47 typedef struct SMU71_Discrete_VoltageLevel SMU71_Discrete_VoltageLevel; 48 49 struct SMU71_Discrete_GraphicsLevel 50 { 51 uint32_t MinVddc; 52 uint32_t MinVddcPhases; 53 54 uint32_t SclkFrequency; 55 56 uint8_t pcieDpmLevel; 57 uint8_t DeepSleepDivId; 58 uint16_t ActivityLevel; 59 60 uint32_t CgSpllFuncCntl3; 61 uint32_t CgSpllFuncCntl4; 62 uint32_t SpllSpreadSpectrum; 63 uint32_t SpllSpreadSpectrum2; 64 uint32_t CcPwrDynRm; 65 uint32_t CcPwrDynRm1; 66 uint8_t SclkDid; 67 uint8_t DisplayWatermark; 68 uint8_t EnabledForActivity; 69 uint8_t EnabledForThrottle; 70 uint8_t UpHyst; 71 uint8_t DownHyst; 72 uint8_t VoltageDownHyst; 73 uint8_t PowerThrottle; 74 }; 75 76 typedef struct SMU71_Discrete_GraphicsLevel SMU71_Discrete_GraphicsLevel; 77 78 struct SMU71_Discrete_ACPILevel 79 { 80 uint32_t Flags; 81 uint32_t MinVddc; 82 uint32_t MinVddcPhases; 83 uint32_t SclkFrequency; 84 uint8_t SclkDid; 85 uint8_t DisplayWatermark; 86 uint8_t DeepSleepDivId; 87 uint8_t padding; 88 uint32_t CgSpllFuncCntl; 89 uint32_t CgSpllFuncCntl2; 90 uint32_t CgSpllFuncCntl3; 91 uint32_t CgSpllFuncCntl4; 92 uint32_t SpllSpreadSpectrum; 93 uint32_t SpllSpreadSpectrum2; 94 uint32_t CcPwrDynRm; 95 uint32_t CcPwrDynRm1; 96 }; 97 98 typedef struct SMU71_Discrete_ACPILevel SMU71_Discrete_ACPILevel; 99 100 struct SMU71_Discrete_Ulv 101 { 102 uint32_t CcPwrDynRm; 103 uint32_t CcPwrDynRm1; 104 uint16_t VddcOffset; 105 uint8_t VddcOffsetVid; 106 uint8_t VddcPhase; 107 uint32_t Reserved; 108 }; 109 110 typedef struct SMU71_Discrete_Ulv SMU71_Discrete_Ulv; 111 112 struct SMU71_Discrete_MemoryLevel 113 { 114 uint32_t MinVddc; 115 uint32_t MinVddcPhases; 116 uint32_t MinVddci; 117 uint32_t MinMvdd; 118 119 uint32_t MclkFrequency; 120 121 uint8_t EdcReadEnable; 122 uint8_t EdcWriteEnable; 123 uint8_t RttEnable; 124 uint8_t StutterEnable; 125 126 uint8_t StrobeEnable; 127 uint8_t StrobeRatio; 128 uint8_t EnabledForThrottle; 129 uint8_t EnabledForActivity; 130 131 uint8_t UpHyst; 132 uint8_t DownHyst; 133 uint8_t VoltageDownHyst; 134 uint8_t padding; 135 136 uint16_t ActivityLevel; 137 uint8_t DisplayWatermark; 138 uint8_t padding1; 139 140 uint32_t MpllFuncCntl; 141 uint32_t MpllFuncCntl_1; 142 uint32_t MpllFuncCntl_2; 143 uint32_t MpllAdFuncCntl; 144 uint32_t MpllDqFuncCntl; 145 uint32_t MclkPwrmgtCntl; 146 uint32_t DllCntl; 147 uint32_t MpllSs1; 148 uint32_t MpllSs2; 149 }; 150 151 typedef struct SMU71_Discrete_MemoryLevel SMU71_Discrete_MemoryLevel; 152 153 struct SMU71_Discrete_LinkLevel 154 { 155 uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 156 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 157 uint8_t EnabledForActivity; 158 uint8_t SPC; 159 uint32_t DownThreshold; 160 uint32_t UpThreshold; 161 uint32_t Reserved; 162 }; 163 164 typedef struct SMU71_Discrete_LinkLevel SMU71_Discrete_LinkLevel; 165 166 167 #ifdef SMU__DYNAMIC_MCARB_SETTINGS 168 // MC ARB DRAM Timing registers. 169 struct SMU71_Discrete_MCArbDramTimingTableEntry 170 { 171 uint32_t McArbDramTiming; 172 uint32_t McArbDramTiming2; 173 uint8_t McArbBurstTime; 174 uint8_t padding[3]; 175 }; 176 177 typedef struct SMU71_Discrete_MCArbDramTimingTableEntry SMU71_Discrete_MCArbDramTimingTableEntry; 178 179 struct SMU71_Discrete_MCArbDramTimingTable 180 { 181 SMU71_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 182 }; 183 184 typedef struct SMU71_Discrete_MCArbDramTimingTable SMU71_Discrete_MCArbDramTimingTable; 185 #endif 186 187 // UVD VCLK/DCLK state (level) definition. 188 struct SMU71_Discrete_UvdLevel 189 { 190 uint32_t VclkFrequency; 191 uint32_t DclkFrequency; 192 uint16_t MinVddc; 193 uint8_t MinVddcPhases; 194 uint8_t VclkDivider; 195 uint8_t DclkDivider; 196 uint8_t padding[3]; 197 }; 198 199 typedef struct SMU71_Discrete_UvdLevel SMU71_Discrete_UvdLevel; 200 201 // Clocks for other external blocks (VCE, ACP, SAMU). 202 struct SMU71_Discrete_ExtClkLevel 203 { 204 uint32_t Frequency; 205 uint16_t MinVoltage; 206 uint8_t MinPhases; 207 uint8_t Divider; 208 }; 209 210 typedef struct SMU71_Discrete_ExtClkLevel SMU71_Discrete_ExtClkLevel; 211 212 // Everything that we need to keep track of about the current state. 213 // Use this instead of copies of the GraphicsLevel and MemoryLevel structures to keep track of state parameters 214 // that need to be checked later. 215 // We don't need to cache everything about a state, just a few parameters. 216 struct SMU71_Discrete_StateInfo 217 { 218 uint32_t SclkFrequency; 219 uint32_t MclkFrequency; 220 uint32_t VclkFrequency; 221 uint32_t DclkFrequency; 222 uint32_t SamclkFrequency; 223 uint32_t AclkFrequency; 224 uint32_t EclkFrequency; 225 uint16_t MvddVoltage; 226 uint16_t padding16; 227 uint8_t DisplayWatermark; 228 uint8_t McArbIndex; 229 uint8_t McRegIndex; 230 uint8_t SeqIndex; 231 uint8_t SclkDid; 232 int8_t SclkIndex; 233 int8_t MclkIndex; 234 uint8_t PCIeGen; 235 236 }; 237 238 typedef struct SMU71_Discrete_StateInfo SMU71_Discrete_StateInfo; 239 240 241 struct SMU71_Discrete_DpmTable 242 { 243 // Multi-DPM controller settings 244 SMU71_PIDController GraphicsPIDController; 245 SMU71_PIDController MemoryPIDController; 246 SMU71_PIDController LinkPIDController; 247 248 uint32_t SystemFlags; 249 250 // SMIO masks for voltage and phase controls 251 uint32_t SmioMaskVddcVid; 252 uint32_t SmioMaskVddcPhase; 253 uint32_t SmioMaskVddciVid; 254 uint32_t SmioMaskMvddVid; 255 256 uint32_t VddcLevelCount; 257 uint32_t VddciLevelCount; 258 uint32_t MvddLevelCount; 259 260 SMU71_Discrete_VoltageLevel VddcLevel [SMU71_MAX_LEVELS_VDDC]; 261 SMU71_Discrete_VoltageLevel VddciLevel [SMU71_MAX_LEVELS_VDDCI]; 262 SMU71_Discrete_VoltageLevel MvddLevel [SMU71_MAX_LEVELS_MVDD]; 263 264 uint8_t GraphicsDpmLevelCount; 265 uint8_t MemoryDpmLevelCount; 266 uint8_t LinkLevelCount; 267 uint8_t MasterDeepSleepControl; 268 269 uint32_t Reserved[5]; 270 271 // State table entries for each DPM state 272 SMU71_Discrete_GraphicsLevel GraphicsLevel [SMU71_MAX_LEVELS_GRAPHICS]; 273 SMU71_Discrete_MemoryLevel MemoryACPILevel; 274 SMU71_Discrete_MemoryLevel MemoryLevel [SMU71_MAX_LEVELS_MEMORY]; 275 SMU71_Discrete_LinkLevel LinkLevel [SMU71_MAX_LEVELS_LINK]; 276 SMU71_Discrete_ACPILevel ACPILevel; 277 278 uint32_t SclkStepSize; 279 uint32_t Smio [SMU71_MAX_ENTRIES_SMIO]; 280 281 uint8_t GraphicsBootLevel; 282 uint8_t GraphicsVoltageChangeEnable; 283 uint8_t GraphicsThermThrottleEnable; 284 uint8_t GraphicsInterval; 285 286 uint8_t VoltageInterval; 287 uint8_t ThermalInterval; 288 uint16_t TemperatureLimitHigh; 289 290 uint16_t TemperatureLimitLow; 291 uint8_t MemoryBootLevel; 292 uint8_t MemoryVoltageChangeEnable; 293 294 uint8_t MemoryInterval; 295 uint8_t MemoryThermThrottleEnable; 296 uint8_t MergedVddci; 297 uint8_t padding2; 298 299 uint16_t VoltageResponseTime; 300 uint16_t PhaseResponseTime; 301 302 uint8_t PCIeBootLinkLevel; 303 uint8_t PCIeGenInterval; 304 uint8_t DTEInterval; 305 uint8_t DTEMode; 306 307 uint8_t SVI2Enable; 308 uint8_t VRHotGpio; 309 uint8_t AcDcGpio; 310 uint8_t ThermGpio; 311 312 uint32_t DisplayCac; 313 314 uint16_t MaxPwr; 315 uint16_t NomPwr; 316 317 uint16_t FpsHighThreshold; 318 uint16_t FpsLowThreshold; 319 320 uint16_t BAPMTI_R [SMU71_DTE_ITERATIONS][SMU71_DTE_SOURCES][SMU71_DTE_SINKS]; 321 uint16_t BAPMTI_RC [SMU71_DTE_ITERATIONS][SMU71_DTE_SOURCES][SMU71_DTE_SINKS]; 322 323 uint8_t DTEAmbientTempBase; 324 uint8_t DTETjOffset; 325 uint8_t GpuTjMax; 326 uint8_t GpuTjHyst; 327 328 uint16_t BootVddc; 329 uint16_t BootVddci; 330 331 uint16_t BootMVdd; 332 uint16_t padding; 333 334 uint32_t BAPM_TEMP_GRADIENT; 335 336 uint32_t LowSclkInterruptThreshold; 337 uint32_t VddGfxReChkWait; 338 339 uint16_t PPM_PkgPwrLimit; 340 uint16_t PPM_TemperatureLimit; 341 342 uint16_t DefaultTdp; 343 uint16_t TargetTdp; 344 }; 345 346 typedef struct SMU71_Discrete_DpmTable SMU71_Discrete_DpmTable; 347 348 // --------------------------------------------------- AC Timing Parameters ------------------------------------------------ 349 #define SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 350 #define SMU71_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU71_MAX_LEVELS_MEMORY 351 352 struct SMU71_Discrete_MCRegisterAddress 353 { 354 uint16_t s0; 355 uint16_t s1; 356 }; 357 358 typedef struct SMU71_Discrete_MCRegisterAddress SMU71_Discrete_MCRegisterAddress; 359 360 struct SMU71_Discrete_MCRegisterSet 361 { 362 uint32_t value[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 363 }; 364 365 typedef struct SMU71_Discrete_MCRegisterSet SMU71_Discrete_MCRegisterSet; 366 367 struct SMU71_Discrete_MCRegisters 368 { 369 uint8_t last; 370 uint8_t reserved[3]; 371 SMU71_Discrete_MCRegisterAddress address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 372 SMU71_Discrete_MCRegisterSet data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT]; 373 }; 374 375 typedef struct SMU71_Discrete_MCRegisters SMU71_Discrete_MCRegisters; 376 377 378 // --------------------------------------------------- Fan Table ----------------------------------------------------------- 379 struct SMU71_Discrete_FanTable 380 { 381 uint16_t FdoMode; 382 int16_t TempMin; 383 int16_t TempMed; 384 int16_t TempMax; 385 int16_t Slope1; 386 int16_t Slope2; 387 int16_t FdoMin; 388 int16_t HystUp; 389 int16_t HystDown; 390 int16_t HystSlope; 391 int16_t TempRespLim; 392 int16_t TempCurr; 393 int16_t SlopeCurr; 394 int16_t PwmCurr; 395 uint32_t RefreshPeriod; 396 int16_t FdoMax; 397 uint8_t TempSrc; 398 int8_t Padding; 399 }; 400 401 typedef struct SMU71_Discrete_FanTable SMU71_Discrete_FanTable; 402 403 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4 404 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG) 405 406 struct SMU71_MclkDpmScoreboard 407 { 408 409 uint32_t PercentageBusy; 410 411 int32_t PIDError; 412 int32_t PIDIntegral; 413 int32_t PIDOutput; 414 415 uint32_t SigmaDeltaAccum; 416 uint32_t SigmaDeltaOutput; 417 uint32_t SigmaDeltaLevel; 418 419 uint32_t UtilizationSetpoint; 420 421 uint8_t TdpClampMode; 422 uint8_t TdcClampMode; 423 uint8_t ThermClampMode; 424 uint8_t VoltageBusy; 425 426 int8_t CurrLevel; 427 int8_t TargLevel; 428 uint8_t LevelChangeInProgress; 429 uint8_t UpHyst; 430 431 uint8_t DownHyst; 432 uint8_t VoltageDownHyst; 433 uint8_t DpmEnable; 434 uint8_t DpmRunning; 435 436 uint8_t DpmForce; 437 uint8_t DpmForceLevel; 438 uint8_t DisplayWatermark; 439 uint8_t McArbIndex; 440 441 uint32_t MinimumPerfMclk; 442 443 uint8_t AcpiReq; 444 uint8_t AcpiAck; 445 uint8_t MclkSwitchInProgress; 446 uint8_t MclkSwitchCritical; 447 448 uint8_t TargetMclkIndex; 449 uint8_t TargetMvddIndex; 450 uint8_t MclkSwitchResult; 451 452 uint8_t EnabledLevelsChange; 453 454 uint16_t LevelResidencyCounters [SMU71_MAX_LEVELS_MEMORY]; 455 uint16_t LevelSwitchCounters [SMU71_MAX_LEVELS_MEMORY]; 456 457 void (*TargetStateCalculator)(uint8_t); 458 void (*SavedTargetStateCalculator)(uint8_t); 459 460 uint16_t AutoDpmInterval; 461 uint16_t AutoDpmRange; 462 463 uint16_t MclkSwitchingTime; 464 uint8_t padding[2]; 465 }; 466 467 typedef struct SMU71_MclkDpmScoreboard SMU71_MclkDpmScoreboard; 468 469 struct SMU71_UlvScoreboard 470 { 471 uint8_t EnterUlv; 472 uint8_t ExitUlv; 473 uint8_t UlvActive; 474 uint8_t WaitingForUlv; 475 uint8_t UlvEnable; 476 uint8_t UlvRunning; 477 uint8_t UlvMasterEnable; 478 uint8_t padding; 479 uint32_t UlvAbortedCount; 480 uint32_t UlvTimeStamp; 481 }; 482 483 typedef struct SMU71_UlvScoreboard SMU71_UlvScoreboard; 484 485 struct SMU71_VddGfxScoreboard 486 { 487 uint8_t VddGfxEnable; 488 uint8_t VddGfxActive; 489 uint8_t padding[2]; 490 491 uint32_t VddGfxEnteredCount; 492 uint32_t VddGfxAbortedCount; 493 }; 494 495 typedef struct SMU71_VddGfxScoreboard SMU71_VddGfxScoreboard; 496 497 struct SMU71_AcpiScoreboard { 498 uint32_t SavedInterruptMask[2]; 499 uint8_t LastACPIRequest; 500 uint8_t CgBifResp; 501 uint8_t RequestType; 502 uint8_t Padding; 503 SMU71_Discrete_ACPILevel D0Level; 504 }; 505 506 typedef struct SMU71_AcpiScoreboard SMU71_AcpiScoreboard; 507 508 509 struct SMU71_Discrete_PmFuses { 510 // dw0-dw1 511 uint8_t BapmVddCVidHiSidd[8]; 512 513 // dw2-dw3 514 uint8_t BapmVddCVidLoSidd[8]; 515 516 // dw4-dw5 517 uint8_t VddCVid[8]; 518 519 // dw6 520 uint8_t SviLoadLineEn; 521 uint8_t SviLoadLineVddC; 522 uint8_t SviLoadLineTrimVddC; 523 uint8_t SviLoadLineOffsetVddC; 524 525 // dw7 526 uint16_t TDC_VDDC_PkgLimit; 527 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 528 uint8_t TDC_MAWt; 529 530 // dw8 531 uint8_t TdcWaterfallCtl; 532 uint8_t LPMLTemperatureMin; 533 uint8_t LPMLTemperatureMax; 534 uint8_t Reserved; 535 536 // dw9-dw12 537 uint8_t LPMLTemperatureScaler[16]; 538 539 // dw13-dw14 540 int16_t FuzzyFan_ErrorSetDelta; 541 int16_t FuzzyFan_ErrorRateSetDelta; 542 int16_t FuzzyFan_PwmSetDelta; 543 uint16_t Reserved6; 544 545 // dw15 546 uint8_t GnbLPML[16]; 547 548 // dw15 549 uint8_t GnbLPMLMaxVid; 550 uint8_t GnbLPMLMinVid; 551 uint8_t Reserved1[2]; 552 553 // dw16 554 uint16_t BapmVddCBaseLeakageHiSidd; 555 uint16_t BapmVddCBaseLeakageLoSidd; 556 }; 557 558 typedef struct SMU71_Discrete_PmFuses SMU71_Discrete_PmFuses; 559 560 struct SMU71_Discrete_Log_Header_Table { 561 uint32_t version; 562 uint32_t asic_id; 563 uint16_t flags; 564 uint16_t entry_size; 565 uint32_t total_size; 566 uint32_t num_of_entries; 567 uint8_t type; 568 uint8_t mode; 569 uint8_t filler_0[2]; 570 uint32_t filler_1[2]; 571 }; 572 573 typedef struct SMU71_Discrete_Log_Header_Table SMU71_Discrete_Log_Header_Table; 574 575 struct SMU71_Discrete_Log_Cntl { 576 uint8_t Enabled; 577 uint8_t Type; 578 uint8_t padding[2]; 579 uint32_t BufferSize; 580 uint32_t SamplesLogged; 581 uint32_t SampleSize; 582 uint32_t AddrL; 583 uint32_t AddrH; 584 }; 585 586 typedef struct SMU71_Discrete_Log_Cntl SMU71_Discrete_Log_Cntl; 587 588 #if defined SMU__DGPU_ONLY 589 #define CAC_ACC_NW_NUM_OF_SIGNALS 83 590 #endif 591 592 593 struct SMU71_Discrete_Cac_Collection_Table { 594 uint32_t temperature; 595 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; 596 uint32_t filler[4]; 597 }; 598 599 typedef struct SMU71_Discrete_Cac_Collection_Table SMU71_Discrete_Cac_Collection_Table; 600 601 struct SMU71_Discrete_Cac_Verification_Table { 602 uint32_t VddcTotalPower; 603 uint32_t VddcLeakagePower; 604 uint32_t VddcConstantPower; 605 uint32_t VddcGfxDynamicPower; 606 uint32_t VddcUvdDynamicPower; 607 uint32_t VddcVceDynamicPower; 608 uint32_t VddcAcpDynamicPower; 609 uint32_t VddcPcieDynamicPower; 610 uint32_t VddcDceDynamicPower; 611 uint32_t VddcCurrent; 612 uint32_t VddcVoltage; 613 uint32_t VddciTotalPower; 614 uint32_t VddciLeakagePower; 615 uint32_t VddciConstantPower; 616 uint32_t VddciDynamicPower; 617 uint32_t Vddr1TotalPower; 618 uint32_t Vddr1LeakagePower; 619 uint32_t Vddr1ConstantPower; 620 uint32_t Vddr1DynamicPower; 621 uint32_t spare[8]; 622 uint32_t temperature; 623 }; 624 625 typedef struct SMU71_Discrete_Cac_Verification_Table SMU71_Discrete_Cac_Verification_Table; 626 627 #if !defined(SMC_MICROCODE) 628 #pragma pack(pop) 629 #endif 630 631 632 #endif 633 634
Indexes created Tue Sep 30 11:09:46 GMT 2025