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intel_overlay.c revision 1.1
      1 /*	$NetBSD: intel_overlay.c,v 1.1 2021/12/18 20:15:30 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright  2009
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice (including the next
     14  * paragraph) shall be included in all copies or substantial portions of the
     15  * Software.
     16  *
     17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     23  * SOFTWARE.
     24  *
     25  * Authors:
     26  *    Daniel Vetter <daniel (at) ffwll.ch>
     27  *
     28  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
     29  */
     30 
     31 #include <sys/cdefs.h>
     32 __KERNEL_RCSID(0, "$NetBSD: intel_overlay.c,v 1.1 2021/12/18 20:15:30 riastradh Exp $");
     33 
     34 #include <drm/drm_fourcc.h>
     35 #include <drm/i915_drm.h>
     36 
     37 #include "gem/i915_gem_pm.h"
     38 #include "gt/intel_ring.h"
     39 
     40 #include "i915_drv.h"
     41 #include "i915_reg.h"
     42 #include "intel_display_types.h"
     43 #include "intel_frontbuffer.h"
     44 #include "intel_overlay.h"
     45 
     46 /* Limits for overlay size. According to intel doc, the real limits are:
     47  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
     48  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
     49  * the mininum of both.  */
     50 #define IMAGE_MAX_WIDTH		2048
     51 #define IMAGE_MAX_HEIGHT	2046 /* 2 * 1023 */
     52 /* on 830 and 845 these large limits result in the card hanging */
     53 #define IMAGE_MAX_WIDTH_LEGACY	1024
     54 #define IMAGE_MAX_HEIGHT_LEGACY	1088
     55 
     56 /* overlay register definitions */
     57 /* OCMD register */
     58 #define OCMD_TILED_SURFACE	(0x1<<19)
     59 #define OCMD_MIRROR_MASK	(0x3<<17)
     60 #define OCMD_MIRROR_MODE	(0x3<<17)
     61 #define OCMD_MIRROR_HORIZONTAL	(0x1<<17)
     62 #define OCMD_MIRROR_VERTICAL	(0x2<<17)
     63 #define OCMD_MIRROR_BOTH	(0x3<<17)
     64 #define OCMD_BYTEORDER_MASK	(0x3<<14) /* zero for YUYV or FOURCC YUY2 */
     65 #define OCMD_UV_SWAP		(0x1<<14) /* YVYU */
     66 #define OCMD_Y_SWAP		(0x2<<14) /* UYVY or FOURCC UYVY */
     67 #define OCMD_Y_AND_UV_SWAP	(0x3<<14) /* VYUY */
     68 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
     69 #define OCMD_RGB_888		(0x1<<10) /* not in i965 Intel docs */
     70 #define OCMD_RGB_555		(0x2<<10) /* not in i965 Intel docs */
     71 #define OCMD_RGB_565		(0x3<<10) /* not in i965 Intel docs */
     72 #define OCMD_YUV_422_PACKED	(0x8<<10)
     73 #define OCMD_YUV_411_PACKED	(0x9<<10) /* not in i965 Intel docs */
     74 #define OCMD_YUV_420_PLANAR	(0xc<<10)
     75 #define OCMD_YUV_422_PLANAR	(0xd<<10)
     76 #define OCMD_YUV_410_PLANAR	(0xe<<10) /* also 411 */
     77 #define OCMD_TVSYNCFLIP_PARITY	(0x1<<9)
     78 #define OCMD_TVSYNCFLIP_ENABLE	(0x1<<7)
     79 #define OCMD_BUF_TYPE_MASK	(0x1<<5)
     80 #define OCMD_BUF_TYPE_FRAME	(0x0<<5)
     81 #define OCMD_BUF_TYPE_FIELD	(0x1<<5)
     82 #define OCMD_TEST_MODE		(0x1<<4)
     83 #define OCMD_BUFFER_SELECT	(0x3<<2)
     84 #define OCMD_BUFFER0		(0x0<<2)
     85 #define OCMD_BUFFER1		(0x1<<2)
     86 #define OCMD_FIELD_SELECT	(0x1<<2)
     87 #define OCMD_FIELD0		(0x0<<1)
     88 #define OCMD_FIELD1		(0x1<<1)
     89 #define OCMD_ENABLE		(0x1<<0)
     90 
     91 /* OCONFIG register */
     92 #define OCONF_PIPE_MASK		(0x1<<18)
     93 #define OCONF_PIPE_A		(0x0<<18)
     94 #define OCONF_PIPE_B		(0x1<<18)
     95 #define OCONF_GAMMA2_ENABLE	(0x1<<16)
     96 #define OCONF_CSC_MODE_BT601	(0x0<<5)
     97 #define OCONF_CSC_MODE_BT709	(0x1<<5)
     98 #define OCONF_CSC_BYPASS	(0x1<<4)
     99 #define OCONF_CC_OUT_8BIT	(0x1<<3)
    100 #define OCONF_TEST_MODE		(0x1<<2)
    101 #define OCONF_THREE_LINE_BUFFER	(0x1<<0)
    102 #define OCONF_TWO_LINE_BUFFER	(0x0<<0)
    103 
    104 /* DCLRKM (dst-key) register */
    105 #define DST_KEY_ENABLE		(0x1<<31)
    106 #define CLK_RGB24_MASK		0x0
    107 #define CLK_RGB16_MASK		0x070307
    108 #define CLK_RGB15_MASK		0x070707
    109 #define CLK_RGB8I_MASK		0xffffff
    110 
    111 #define RGB16_TO_COLORKEY(c) \
    112 	(((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
    113 #define RGB15_TO_COLORKEY(c) \
    114 	(((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
    115 
    116 /* overlay flip addr flag */
    117 #define OFC_UPDATE		0x1
    118 
    119 /* polyphase filter coefficients */
    120 #define N_HORIZ_Y_TAPS          5
    121 #define N_VERT_Y_TAPS           3
    122 #define N_HORIZ_UV_TAPS         3
    123 #define N_VERT_UV_TAPS          3
    124 #define N_PHASES                17
    125 #define MAX_TAPS                5
    126 
    127 /* memory bufferd overlay registers */
    128 struct overlay_registers {
    129 	u32 OBUF_0Y;
    130 	u32 OBUF_1Y;
    131 	u32 OBUF_0U;
    132 	u32 OBUF_0V;
    133 	u32 OBUF_1U;
    134 	u32 OBUF_1V;
    135 	u32 OSTRIDE;
    136 	u32 YRGB_VPH;
    137 	u32 UV_VPH;
    138 	u32 HORZ_PH;
    139 	u32 INIT_PHS;
    140 	u32 DWINPOS;
    141 	u32 DWINSZ;
    142 	u32 SWIDTH;
    143 	u32 SWIDTHSW;
    144 	u32 SHEIGHT;
    145 	u32 YRGBSCALE;
    146 	u32 UVSCALE;
    147 	u32 OCLRC0;
    148 	u32 OCLRC1;
    149 	u32 DCLRKV;
    150 	u32 DCLRKM;
    151 	u32 SCLRKVH;
    152 	u32 SCLRKVL;
    153 	u32 SCLRKEN;
    154 	u32 OCONFIG;
    155 	u32 OCMD;
    156 	u32 RESERVED1; /* 0x6C */
    157 	u32 OSTART_0Y;
    158 	u32 OSTART_1Y;
    159 	u32 OSTART_0U;
    160 	u32 OSTART_0V;
    161 	u32 OSTART_1U;
    162 	u32 OSTART_1V;
    163 	u32 OTILEOFF_0Y;
    164 	u32 OTILEOFF_1Y;
    165 	u32 OTILEOFF_0U;
    166 	u32 OTILEOFF_0V;
    167 	u32 OTILEOFF_1U;
    168 	u32 OTILEOFF_1V;
    169 	u32 FASTHSCALE; /* 0xA0 */
    170 	u32 UVSCALEV; /* 0xA4 */
    171 	u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
    172 	u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
    173 	u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
    174 	u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
    175 	u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
    176 	u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
    177 	u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
    178 	u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
    179 	u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
    180 };
    181 
    182 struct intel_overlay {
    183 	struct drm_i915_private *i915;
    184 	struct intel_context *context;
    185 	struct intel_crtc *crtc;
    186 	struct i915_vma *vma;
    187 	struct i915_vma *old_vma;
    188 	bool active;
    189 	bool pfit_active;
    190 	u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
    191 	u32 color_key:24;
    192 	u32 color_key_enabled:1;
    193 	u32 brightness, contrast, saturation;
    194 	u32 old_xscale, old_yscale;
    195 	/* register access */
    196 	struct drm_i915_gem_object *reg_bo;
    197 	struct overlay_registers __iomem *regs;
    198 	u32 flip_addr;
    199 	/* flip handling */
    200 	struct i915_active last_flip;
    201 	void (*flip_complete)(struct intel_overlay *ovl);
    202 };
    203 
    204 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
    205 				      bool enable)
    206 {
    207 	struct pci_dev *pdev = dev_priv->drm.pdev;
    208 	u8 val;
    209 
    210 	/* WA_OVERLAY_CLKGATE:alm */
    211 	if (enable)
    212 		I915_WRITE(DSPCLK_GATE_D, 0);
    213 	else
    214 		I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
    215 
    216 	/* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
    217 	pci_bus_read_config_byte(pdev->bus,
    218 				 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
    219 	if (enable)
    220 		val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
    221 	else
    222 		val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
    223 	pci_bus_write_config_byte(pdev->bus,
    224 				  PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
    225 }
    226 
    227 static struct i915_request *
    228 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *))
    229 {
    230 	struct i915_request *rq;
    231 	int err;
    232 
    233 	overlay->flip_complete = fn;
    234 
    235 	rq = i915_request_create(overlay->context);
    236 	if (IS_ERR(rq))
    237 		return rq;
    238 
    239 	err = i915_active_add_request(&overlay->last_flip, rq);
    240 	if (err) {
    241 		i915_request_add(rq);
    242 		return ERR_PTR(err);
    243 	}
    244 
    245 	return rq;
    246 }
    247 
    248 /* overlay needs to be disable in OCMD reg */
    249 static int intel_overlay_on(struct intel_overlay *overlay)
    250 {
    251 	struct drm_i915_private *dev_priv = overlay->i915;
    252 	struct i915_request *rq;
    253 	u32 *cs;
    254 
    255 	WARN_ON(overlay->active);
    256 
    257 	rq = alloc_request(overlay, NULL);
    258 	if (IS_ERR(rq))
    259 		return PTR_ERR(rq);
    260 
    261 	cs = intel_ring_begin(rq, 4);
    262 	if (IS_ERR(cs)) {
    263 		i915_request_add(rq);
    264 		return PTR_ERR(cs);
    265 	}
    266 
    267 	overlay->active = true;
    268 
    269 	if (IS_I830(dev_priv))
    270 		i830_overlay_clock_gating(dev_priv, false);
    271 
    272 	*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON;
    273 	*cs++ = overlay->flip_addr | OFC_UPDATE;
    274 	*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
    275 	*cs++ = MI_NOOP;
    276 	intel_ring_advance(rq, cs);
    277 
    278 	i915_request_add(rq);
    279 
    280 	return i915_active_wait(&overlay->last_flip);
    281 }
    282 
    283 static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
    284 				       struct i915_vma *vma)
    285 {
    286 	enum pipe pipe = overlay->crtc->pipe;
    287 	struct intel_frontbuffer *from = NULL, *to = NULL;
    288 
    289 	WARN_ON(overlay->old_vma);
    290 
    291 	if (overlay->vma)
    292 		from = intel_frontbuffer_get(overlay->vma->obj);
    293 	if (vma)
    294 		to = intel_frontbuffer_get(vma->obj);
    295 
    296 	intel_frontbuffer_track(from, to, INTEL_FRONTBUFFER_OVERLAY(pipe));
    297 
    298 	if (to)
    299 		intel_frontbuffer_put(to);
    300 	if (from)
    301 		intel_frontbuffer_put(from);
    302 
    303 	intel_frontbuffer_flip_prepare(overlay->i915,
    304 				       INTEL_FRONTBUFFER_OVERLAY(pipe));
    305 
    306 	overlay->old_vma = overlay->vma;
    307 	if (vma)
    308 		overlay->vma = i915_vma_get(vma);
    309 	else
    310 		overlay->vma = NULL;
    311 }
    312 
    313 /* overlay needs to be enabled in OCMD reg */
    314 static int intel_overlay_continue(struct intel_overlay *overlay,
    315 				  struct i915_vma *vma,
    316 				  bool load_polyphase_filter)
    317 {
    318 	struct drm_i915_private *dev_priv = overlay->i915;
    319 	struct i915_request *rq;
    320 	u32 flip_addr = overlay->flip_addr;
    321 	u32 tmp, *cs;
    322 
    323 	WARN_ON(!overlay->active);
    324 
    325 	if (load_polyphase_filter)
    326 		flip_addr |= OFC_UPDATE;
    327 
    328 	/* check for underruns */
    329 	tmp = I915_READ(DOVSTA);
    330 	if (tmp & (1 << 17))
    331 		DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
    332 
    333 	rq = alloc_request(overlay, NULL);
    334 	if (IS_ERR(rq))
    335 		return PTR_ERR(rq);
    336 
    337 	cs = intel_ring_begin(rq, 2);
    338 	if (IS_ERR(cs)) {
    339 		i915_request_add(rq);
    340 		return PTR_ERR(cs);
    341 	}
    342 
    343 	*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
    344 	*cs++ = flip_addr;
    345 	intel_ring_advance(rq, cs);
    346 
    347 	intel_overlay_flip_prepare(overlay, vma);
    348 	i915_request_add(rq);
    349 
    350 	return 0;
    351 }
    352 
    353 static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
    354 {
    355 	struct i915_vma *vma;
    356 
    357 	vma = fetch_and_zero(&overlay->old_vma);
    358 	if (WARN_ON(!vma))
    359 		return;
    360 
    361 	intel_frontbuffer_flip_complete(overlay->i915,
    362 					INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
    363 
    364 	i915_gem_object_unpin_from_display_plane(vma);
    365 	i915_vma_put(vma);
    366 }
    367 
    368 static void
    369 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
    370 {
    371 	intel_overlay_release_old_vma(overlay);
    372 }
    373 
    374 static void intel_overlay_off_tail(struct intel_overlay *overlay)
    375 {
    376 	struct drm_i915_private *dev_priv = overlay->i915;
    377 
    378 	intel_overlay_release_old_vma(overlay);
    379 
    380 	overlay->crtc->overlay = NULL;
    381 	overlay->crtc = NULL;
    382 	overlay->active = false;
    383 
    384 	if (IS_I830(dev_priv))
    385 		i830_overlay_clock_gating(dev_priv, true);
    386 }
    387 
    388 static void
    389 intel_overlay_last_flip_retire(struct i915_active *active)
    390 {
    391 	struct intel_overlay *overlay =
    392 		container_of(active, typeof(*overlay), last_flip);
    393 
    394 	if (overlay->flip_complete)
    395 		overlay->flip_complete(overlay);
    396 }
    397 
    398 /* overlay needs to be disabled in OCMD reg */
    399 static int intel_overlay_off(struct intel_overlay *overlay)
    400 {
    401 	struct i915_request *rq;
    402 	u32 *cs, flip_addr = overlay->flip_addr;
    403 
    404 	WARN_ON(!overlay->active);
    405 
    406 	/* According to intel docs the overlay hw may hang (when switching
    407 	 * off) without loading the filter coeffs. It is however unclear whether
    408 	 * this applies to the disabling of the overlay or to the switching off
    409 	 * of the hw. Do it in both cases */
    410 	flip_addr |= OFC_UPDATE;
    411 
    412 	rq = alloc_request(overlay, intel_overlay_off_tail);
    413 	if (IS_ERR(rq))
    414 		return PTR_ERR(rq);
    415 
    416 	cs = intel_ring_begin(rq, 6);
    417 	if (IS_ERR(cs)) {
    418 		i915_request_add(rq);
    419 		return PTR_ERR(cs);
    420 	}
    421 
    422 	/* wait for overlay to go idle */
    423 	*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
    424 	*cs++ = flip_addr;
    425 	*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
    426 
    427 	/* turn overlay off */
    428 	*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF;
    429 	*cs++ = flip_addr;
    430 	*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
    431 
    432 	intel_ring_advance(rq, cs);
    433 
    434 	intel_overlay_flip_prepare(overlay, NULL);
    435 	i915_request_add(rq);
    436 
    437 	return i915_active_wait(&overlay->last_flip);
    438 }
    439 
    440 /* recover from an interruption due to a signal
    441  * We have to be careful not to repeat work forever an make forward progess. */
    442 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
    443 {
    444 	return i915_active_wait(&overlay->last_flip);
    445 }
    446 
    447 /* Wait for pending overlay flip and release old frame.
    448  * Needs to be called before the overlay register are changed
    449  * via intel_overlay_(un)map_regs
    450  */
    451 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
    452 {
    453 	struct drm_i915_private *dev_priv = overlay->i915;
    454 	struct i915_request *rq;
    455 	u32 *cs;
    456 
    457 	/*
    458 	 * Only wait if there is actually an old frame to release to
    459 	 * guarantee forward progress.
    460 	 */
    461 	if (!overlay->old_vma)
    462 		return 0;
    463 
    464 	if (!(I915_READ(GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {
    465 		intel_overlay_release_old_vid_tail(overlay);
    466 		return 0;
    467 	}
    468 
    469 	rq = alloc_request(overlay, intel_overlay_release_old_vid_tail);
    470 	if (IS_ERR(rq))
    471 		return PTR_ERR(rq);
    472 
    473 	cs = intel_ring_begin(rq, 2);
    474 	if (IS_ERR(cs)) {
    475 		i915_request_add(rq);
    476 		return PTR_ERR(cs);
    477 	}
    478 
    479 	*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
    480 	*cs++ = MI_NOOP;
    481 	intel_ring_advance(rq, cs);
    482 
    483 	i915_request_add(rq);
    484 
    485 	return i915_active_wait(&overlay->last_flip);
    486 }
    487 
    488 void intel_overlay_reset(struct drm_i915_private *dev_priv)
    489 {
    490 	struct intel_overlay *overlay = dev_priv->overlay;
    491 
    492 	if (!overlay)
    493 		return;
    494 
    495 	overlay->old_xscale = 0;
    496 	overlay->old_yscale = 0;
    497 	overlay->crtc = NULL;
    498 	overlay->active = false;
    499 }
    500 
    501 static int packed_depth_bytes(u32 format)
    502 {
    503 	switch (format & I915_OVERLAY_DEPTH_MASK) {
    504 	case I915_OVERLAY_YUV422:
    505 		return 4;
    506 	case I915_OVERLAY_YUV411:
    507 		/* return 6; not implemented */
    508 	default:
    509 		return -EINVAL;
    510 	}
    511 }
    512 
    513 static int packed_width_bytes(u32 format, short width)
    514 {
    515 	switch (format & I915_OVERLAY_DEPTH_MASK) {
    516 	case I915_OVERLAY_YUV422:
    517 		return width << 1;
    518 	default:
    519 		return -EINVAL;
    520 	}
    521 }
    522 
    523 static int uv_hsubsampling(u32 format)
    524 {
    525 	switch (format & I915_OVERLAY_DEPTH_MASK) {
    526 	case I915_OVERLAY_YUV422:
    527 	case I915_OVERLAY_YUV420:
    528 		return 2;
    529 	case I915_OVERLAY_YUV411:
    530 	case I915_OVERLAY_YUV410:
    531 		return 4;
    532 	default:
    533 		return -EINVAL;
    534 	}
    535 }
    536 
    537 static int uv_vsubsampling(u32 format)
    538 {
    539 	switch (format & I915_OVERLAY_DEPTH_MASK) {
    540 	case I915_OVERLAY_YUV420:
    541 	case I915_OVERLAY_YUV410:
    542 		return 2;
    543 	case I915_OVERLAY_YUV422:
    544 	case I915_OVERLAY_YUV411:
    545 		return 1;
    546 	default:
    547 		return -EINVAL;
    548 	}
    549 }
    550 
    551 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
    552 {
    553 	u32 sw;
    554 
    555 	if (IS_GEN(dev_priv, 2))
    556 		sw = ALIGN((offset & 31) + width, 32);
    557 	else
    558 		sw = ALIGN((offset & 63) + width, 64);
    559 
    560 	if (sw == 0)
    561 		return 0;
    562 
    563 	return (sw - 32) >> 3;
    564 }
    565 
    566 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
    567 	[ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
    568 	[ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
    569 	[ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
    570 	[ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
    571 	[ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
    572 	[ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
    573 	[ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
    574 	[ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
    575 	[ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
    576 	[ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
    577 	[10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
    578 	[11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
    579 	[12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
    580 	[13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
    581 	[14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
    582 	[15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
    583 	[16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
    584 };
    585 
    586 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
    587 	[ 0] = { 0x3000, 0x1800, 0x1800, },
    588 	[ 1] = { 0xb000, 0x18d0, 0x2e60, },
    589 	[ 2] = { 0xb000, 0x1990, 0x2ce0, },
    590 	[ 3] = { 0xb020, 0x1a68, 0x2b40, },
    591 	[ 4] = { 0xb040, 0x1b20, 0x29e0, },
    592 	[ 5] = { 0xb060, 0x1bd8, 0x2880, },
    593 	[ 6] = { 0xb080, 0x1c88, 0x3e60, },
    594 	[ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
    595 	[ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
    596 	[ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
    597 	[10] = { 0xb100, 0x1eb8, 0x3620, },
    598 	[11] = { 0xb100, 0x1f18, 0x34a0, },
    599 	[12] = { 0xb100, 0x1f68, 0x3360, },
    600 	[13] = { 0xb0e0, 0x1fa8, 0x3240, },
    601 	[14] = { 0xb0c0, 0x1fe0, 0x3140, },
    602 	[15] = { 0xb060, 0x1ff0, 0x30a0, },
    603 	[16] = { 0x3000, 0x0800, 0x3000, },
    604 };
    605 
    606 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
    607 {
    608 	memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
    609 	memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
    610 		    sizeof(uv_static_hcoeffs));
    611 }
    612 
    613 static bool update_scaling_factors(struct intel_overlay *overlay,
    614 				   struct overlay_registers __iomem *regs,
    615 				   struct drm_intel_overlay_put_image *params)
    616 {
    617 	/* fixed point with a 12 bit shift */
    618 	u32 xscale, yscale, xscale_UV, yscale_UV;
    619 #define FP_SHIFT 12
    620 #define FRACT_MASK 0xfff
    621 	bool scale_changed = false;
    622 	int uv_hscale = uv_hsubsampling(params->flags);
    623 	int uv_vscale = uv_vsubsampling(params->flags);
    624 
    625 	if (params->dst_width > 1)
    626 		xscale = ((params->src_scan_width - 1) << FP_SHIFT) /
    627 			params->dst_width;
    628 	else
    629 		xscale = 1 << FP_SHIFT;
    630 
    631 	if (params->dst_height > 1)
    632 		yscale = ((params->src_scan_height - 1) << FP_SHIFT) /
    633 			params->dst_height;
    634 	else
    635 		yscale = 1 << FP_SHIFT;
    636 
    637 	/*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
    638 	xscale_UV = xscale/uv_hscale;
    639 	yscale_UV = yscale/uv_vscale;
    640 	/* make the Y scale to UV scale ratio an exact multiply */
    641 	xscale = xscale_UV * uv_hscale;
    642 	yscale = yscale_UV * uv_vscale;
    643 	/*} else {
    644 	  xscale_UV = 0;
    645 	  yscale_UV = 0;
    646 	  }*/
    647 
    648 	if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
    649 		scale_changed = true;
    650 	overlay->old_xscale = xscale;
    651 	overlay->old_yscale = yscale;
    652 
    653 	iowrite32(((yscale & FRACT_MASK) << 20) |
    654 		  ((xscale >> FP_SHIFT)  << 16) |
    655 		  ((xscale & FRACT_MASK) << 3),
    656 		 &regs->YRGBSCALE);
    657 
    658 	iowrite32(((yscale_UV & FRACT_MASK) << 20) |
    659 		  ((xscale_UV >> FP_SHIFT)  << 16) |
    660 		  ((xscale_UV & FRACT_MASK) << 3),
    661 		 &regs->UVSCALE);
    662 
    663 	iowrite32((((yscale    >> FP_SHIFT) << 16) |
    664 		   ((yscale_UV >> FP_SHIFT) << 0)),
    665 		 &regs->UVSCALEV);
    666 
    667 	if (scale_changed)
    668 		update_polyphase_filter(regs);
    669 
    670 	return scale_changed;
    671 }
    672 
    673 static void update_colorkey(struct intel_overlay *overlay,
    674 			    struct overlay_registers __iomem *regs)
    675 {
    676 	const struct intel_plane_state *state =
    677 		to_intel_plane_state(overlay->crtc->base.primary->state);
    678 	u32 key = overlay->color_key;
    679 	u32 format = 0;
    680 	u32 flags = 0;
    681 
    682 	if (overlay->color_key_enabled)
    683 		flags |= DST_KEY_ENABLE;
    684 
    685 	if (state->uapi.visible)
    686 		format = state->hw.fb->format->format;
    687 
    688 	switch (format) {
    689 	case DRM_FORMAT_C8:
    690 		key = 0;
    691 		flags |= CLK_RGB8I_MASK;
    692 		break;
    693 	case DRM_FORMAT_XRGB1555:
    694 		key = RGB15_TO_COLORKEY(key);
    695 		flags |= CLK_RGB15_MASK;
    696 		break;
    697 	case DRM_FORMAT_RGB565:
    698 		key = RGB16_TO_COLORKEY(key);
    699 		flags |= CLK_RGB16_MASK;
    700 		break;
    701 	default:
    702 		flags |= CLK_RGB24_MASK;
    703 		break;
    704 	}
    705 
    706 	iowrite32(key, &regs->DCLRKV);
    707 	iowrite32(flags, &regs->DCLRKM);
    708 }
    709 
    710 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)
    711 {
    712 	u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
    713 
    714 	if (params->flags & I915_OVERLAY_YUV_PLANAR) {
    715 		switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
    716 		case I915_OVERLAY_YUV422:
    717 			cmd |= OCMD_YUV_422_PLANAR;
    718 			break;
    719 		case I915_OVERLAY_YUV420:
    720 			cmd |= OCMD_YUV_420_PLANAR;
    721 			break;
    722 		case I915_OVERLAY_YUV411:
    723 		case I915_OVERLAY_YUV410:
    724 			cmd |= OCMD_YUV_410_PLANAR;
    725 			break;
    726 		}
    727 	} else { /* YUV packed */
    728 		switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
    729 		case I915_OVERLAY_YUV422:
    730 			cmd |= OCMD_YUV_422_PACKED;
    731 			break;
    732 		case I915_OVERLAY_YUV411:
    733 			cmd |= OCMD_YUV_411_PACKED;
    734 			break;
    735 		}
    736 
    737 		switch (params->flags & I915_OVERLAY_SWAP_MASK) {
    738 		case I915_OVERLAY_NO_SWAP:
    739 			break;
    740 		case I915_OVERLAY_UV_SWAP:
    741 			cmd |= OCMD_UV_SWAP;
    742 			break;
    743 		case I915_OVERLAY_Y_SWAP:
    744 			cmd |= OCMD_Y_SWAP;
    745 			break;
    746 		case I915_OVERLAY_Y_AND_UV_SWAP:
    747 			cmd |= OCMD_Y_AND_UV_SWAP;
    748 			break;
    749 		}
    750 	}
    751 
    752 	return cmd;
    753 }
    754 
    755 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
    756 				      struct drm_i915_gem_object *new_bo,
    757 				      struct drm_intel_overlay_put_image *params)
    758 {
    759 	struct overlay_registers __iomem *regs = overlay->regs;
    760 	struct drm_i915_private *dev_priv = overlay->i915;
    761 	u32 swidth, swidthsw, sheight, ostride;
    762 	enum pipe pipe = overlay->crtc->pipe;
    763 	bool scale_changed = false;
    764 	struct i915_vma *vma;
    765 	int ret, tmp_width;
    766 
    767 	WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
    768 
    769 	ret = intel_overlay_release_old_vid(overlay);
    770 	if (ret != 0)
    771 		return ret;
    772 
    773 	atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
    774 
    775 	vma = i915_gem_object_pin_to_display_plane(new_bo,
    776 						   0, NULL, PIN_MAPPABLE);
    777 	if (IS_ERR(vma)) {
    778 		ret = PTR_ERR(vma);
    779 		goto out_pin_section;
    780 	}
    781 	i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB);
    782 
    783 	if (!overlay->active) {
    784 		u32 oconfig;
    785 
    786 		oconfig = OCONF_CC_OUT_8BIT;
    787 		if (IS_GEN(dev_priv, 4))
    788 			oconfig |= OCONF_CSC_MODE_BT709;
    789 		oconfig |= pipe == 0 ?
    790 			OCONF_PIPE_A : OCONF_PIPE_B;
    791 		iowrite32(oconfig, &regs->OCONFIG);
    792 
    793 		ret = intel_overlay_on(overlay);
    794 		if (ret != 0)
    795 			goto out_unpin;
    796 	}
    797 
    798 	iowrite32(params->dst_y << 16 | params->dst_x, &regs->DWINPOS);
    799 	iowrite32(params->dst_height << 16 | params->dst_width, &regs->DWINSZ);
    800 
    801 	if (params->flags & I915_OVERLAY_YUV_PACKED)
    802 		tmp_width = packed_width_bytes(params->flags,
    803 					       params->src_width);
    804 	else
    805 		tmp_width = params->src_width;
    806 
    807 	swidth = params->src_width;
    808 	swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
    809 	sheight = params->src_height;
    810 	iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);
    811 	ostride = params->stride_Y;
    812 
    813 	if (params->flags & I915_OVERLAY_YUV_PLANAR) {
    814 		int uv_hscale = uv_hsubsampling(params->flags);
    815 		int uv_vscale = uv_vsubsampling(params->flags);
    816 		u32 tmp_U, tmp_V;
    817 
    818 		swidth |= (params->src_width / uv_hscale) << 16;
    819 		sheight |= (params->src_height / uv_vscale) << 16;
    820 
    821 		tmp_U = calc_swidthsw(dev_priv, params->offset_U,
    822 				      params->src_width / uv_hscale);
    823 		tmp_V = calc_swidthsw(dev_priv, params->offset_V,
    824 				      params->src_width / uv_hscale);
    825 		swidthsw |= max(tmp_U, tmp_V) << 16;
    826 
    827 		iowrite32(i915_ggtt_offset(vma) + params->offset_U,
    828 			  &regs->OBUF_0U);
    829 		iowrite32(i915_ggtt_offset(vma) + params->offset_V,
    830 			  &regs->OBUF_0V);
    831 
    832 		ostride |= params->stride_UV << 16;
    833 	}
    834 
    835 	iowrite32(swidth, &regs->SWIDTH);
    836 	iowrite32(swidthsw, &regs->SWIDTHSW);
    837 	iowrite32(sheight, &regs->SHEIGHT);
    838 	iowrite32(ostride, &regs->OSTRIDE);
    839 
    840 	scale_changed = update_scaling_factors(overlay, regs, params);
    841 
    842 	update_colorkey(overlay, regs);
    843 
    844 	iowrite32(overlay_cmd_reg(params), &regs->OCMD);
    845 
    846 	ret = intel_overlay_continue(overlay, vma, scale_changed);
    847 	if (ret)
    848 		goto out_unpin;
    849 
    850 	return 0;
    851 
    852 out_unpin:
    853 	i915_gem_object_unpin_from_display_plane(vma);
    854 out_pin_section:
    855 	atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
    856 
    857 	return ret;
    858 }
    859 
    860 int intel_overlay_switch_off(struct intel_overlay *overlay)
    861 {
    862 	struct drm_i915_private *dev_priv = overlay->i915;
    863 	int ret;
    864 
    865 	WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
    866 
    867 	ret = intel_overlay_recover_from_interrupt(overlay);
    868 	if (ret != 0)
    869 		return ret;
    870 
    871 	if (!overlay->active)
    872 		return 0;
    873 
    874 	ret = intel_overlay_release_old_vid(overlay);
    875 	if (ret != 0)
    876 		return ret;
    877 
    878 	iowrite32(0, &overlay->regs->OCMD);
    879 
    880 	return intel_overlay_off(overlay);
    881 }
    882 
    883 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
    884 					  struct intel_crtc *crtc)
    885 {
    886 	if (!crtc->active)
    887 		return -EINVAL;
    888 
    889 	/* can't use the overlay with double wide pipe */
    890 	if (crtc->config->double_wide)
    891 		return -EINVAL;
    892 
    893 	return 0;
    894 }
    895 
    896 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
    897 {
    898 	struct drm_i915_private *dev_priv = overlay->i915;
    899 	u32 pfit_control = I915_READ(PFIT_CONTROL);
    900 	u32 ratio;
    901 
    902 	/* XXX: This is not the same logic as in the xorg driver, but more in
    903 	 * line with the intel documentation for the i965
    904 	 */
    905 	if (INTEL_GEN(dev_priv) >= 4) {
    906 		/* on i965 use the PGM reg to read out the autoscaler values */
    907 		ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
    908 	} else {
    909 		if (pfit_control & VERT_AUTO_SCALE)
    910 			ratio = I915_READ(PFIT_AUTO_RATIOS);
    911 		else
    912 			ratio = I915_READ(PFIT_PGM_RATIOS);
    913 		ratio >>= PFIT_VERT_SCALE_SHIFT;
    914 	}
    915 
    916 	overlay->pfit_vscale_ratio = ratio;
    917 }
    918 
    919 static int check_overlay_dst(struct intel_overlay *overlay,
    920 			     struct drm_intel_overlay_put_image *rec)
    921 {
    922 	const struct intel_crtc_state *pipe_config =
    923 		overlay->crtc->config;
    924 
    925 	if (rec->dst_x < pipe_config->pipe_src_w &&
    926 	    rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
    927 	    rec->dst_y < pipe_config->pipe_src_h &&
    928 	    rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h)
    929 		return 0;
    930 	else
    931 		return -EINVAL;
    932 }
    933 
    934 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec)
    935 {
    936 	u32 tmp;
    937 
    938 	/* downscaling limit is 8.0 */
    939 	tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;
    940 	if (tmp > 7)
    941 		return -EINVAL;
    942 
    943 	tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;
    944 	if (tmp > 7)
    945 		return -EINVAL;
    946 
    947 	return 0;
    948 }
    949 
    950 static int check_overlay_src(struct drm_i915_private *dev_priv,
    951 			     struct drm_intel_overlay_put_image *rec,
    952 			     struct drm_i915_gem_object *new_bo)
    953 {
    954 	int uv_hscale = uv_hsubsampling(rec->flags);
    955 	int uv_vscale = uv_vsubsampling(rec->flags);
    956 	u32 stride_mask;
    957 	int depth;
    958 	u32 tmp;
    959 
    960 	/* check src dimensions */
    961 	if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
    962 		if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
    963 		    rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
    964 			return -EINVAL;
    965 	} else {
    966 		if (rec->src_height > IMAGE_MAX_HEIGHT ||
    967 		    rec->src_width  > IMAGE_MAX_WIDTH)
    968 			return -EINVAL;
    969 	}
    970 
    971 	/* better safe than sorry, use 4 as the maximal subsampling ratio */
    972 	if (rec->src_height < N_VERT_Y_TAPS*4 ||
    973 	    rec->src_width  < N_HORIZ_Y_TAPS*4)
    974 		return -EINVAL;
    975 
    976 	/* check alignment constraints */
    977 	switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
    978 	case I915_OVERLAY_RGB:
    979 		/* not implemented */
    980 		return -EINVAL;
    981 
    982 	case I915_OVERLAY_YUV_PACKED:
    983 		if (uv_vscale != 1)
    984 			return -EINVAL;
    985 
    986 		depth = packed_depth_bytes(rec->flags);
    987 		if (depth < 0)
    988 			return depth;
    989 
    990 		/* ignore UV planes */
    991 		rec->stride_UV = 0;
    992 		rec->offset_U = 0;
    993 		rec->offset_V = 0;
    994 		/* check pixel alignment */
    995 		if (rec->offset_Y % depth)
    996 			return -EINVAL;
    997 		break;
    998 
    999 	case I915_OVERLAY_YUV_PLANAR:
   1000 		if (uv_vscale < 0 || uv_hscale < 0)
   1001 			return -EINVAL;
   1002 		/* no offset restrictions for planar formats */
   1003 		break;
   1004 
   1005 	default:
   1006 		return -EINVAL;
   1007 	}
   1008 
   1009 	if (rec->src_width % uv_hscale)
   1010 		return -EINVAL;
   1011 
   1012 	/* stride checking */
   1013 	if (IS_I830(dev_priv) || IS_I845G(dev_priv))
   1014 		stride_mask = 255;
   1015 	else
   1016 		stride_mask = 63;
   1017 
   1018 	if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
   1019 		return -EINVAL;
   1020 	if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512)
   1021 		return -EINVAL;
   1022 
   1023 	tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
   1024 		4096 : 8192;
   1025 	if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
   1026 		return -EINVAL;
   1027 
   1028 	/* check buffer dimensions */
   1029 	switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
   1030 	case I915_OVERLAY_RGB:
   1031 	case I915_OVERLAY_YUV_PACKED:
   1032 		/* always 4 Y values per depth pixels */
   1033 		if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
   1034 			return -EINVAL;
   1035 
   1036 		tmp = rec->stride_Y*rec->src_height;
   1037 		if (rec->offset_Y + tmp > new_bo->base.size)
   1038 			return -EINVAL;
   1039 		break;
   1040 
   1041 	case I915_OVERLAY_YUV_PLANAR:
   1042 		if (rec->src_width > rec->stride_Y)
   1043 			return -EINVAL;
   1044 		if (rec->src_width/uv_hscale > rec->stride_UV)
   1045 			return -EINVAL;
   1046 
   1047 		tmp = rec->stride_Y * rec->src_height;
   1048 		if (rec->offset_Y + tmp > new_bo->base.size)
   1049 			return -EINVAL;
   1050 
   1051 		tmp = rec->stride_UV * (rec->src_height / uv_vscale);
   1052 		if (rec->offset_U + tmp > new_bo->base.size ||
   1053 		    rec->offset_V + tmp > new_bo->base.size)
   1054 			return -EINVAL;
   1055 		break;
   1056 	}
   1057 
   1058 	return 0;
   1059 }
   1060 
   1061 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
   1062 				  struct drm_file *file_priv)
   1063 {
   1064 	struct drm_intel_overlay_put_image *params = data;
   1065 	struct drm_i915_private *dev_priv = to_i915(dev);
   1066 	struct intel_overlay *overlay;
   1067 	struct drm_crtc *drmmode_crtc;
   1068 	struct intel_crtc *crtc;
   1069 	struct drm_i915_gem_object *new_bo;
   1070 	int ret;
   1071 
   1072 	overlay = dev_priv->overlay;
   1073 	if (!overlay) {
   1074 		DRM_DEBUG("userspace bug: no overlay\n");
   1075 		return -ENODEV;
   1076 	}
   1077 
   1078 	if (!(params->flags & I915_OVERLAY_ENABLE)) {
   1079 		drm_modeset_lock_all(dev);
   1080 		ret = intel_overlay_switch_off(overlay);
   1081 		drm_modeset_unlock_all(dev);
   1082 
   1083 		return ret;
   1084 	}
   1085 
   1086 	drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id);
   1087 	if (!drmmode_crtc)
   1088 		return -ENOENT;
   1089 	crtc = to_intel_crtc(drmmode_crtc);
   1090 
   1091 	new_bo = i915_gem_object_lookup(file_priv, params->bo_handle);
   1092 	if (!new_bo)
   1093 		return -ENOENT;
   1094 
   1095 	drm_modeset_lock_all(dev);
   1096 
   1097 	if (i915_gem_object_is_tiled(new_bo)) {
   1098 		DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
   1099 		ret = -EINVAL;
   1100 		goto out_unlock;
   1101 	}
   1102 
   1103 	ret = intel_overlay_recover_from_interrupt(overlay);
   1104 	if (ret != 0)
   1105 		goto out_unlock;
   1106 
   1107 	if (overlay->crtc != crtc) {
   1108 		ret = intel_overlay_switch_off(overlay);
   1109 		if (ret != 0)
   1110 			goto out_unlock;
   1111 
   1112 		ret = check_overlay_possible_on_crtc(overlay, crtc);
   1113 		if (ret != 0)
   1114 			goto out_unlock;
   1115 
   1116 		overlay->crtc = crtc;
   1117 		crtc->overlay = overlay;
   1118 
   1119 		/* line too wide, i.e. one-line-mode */
   1120 		if (crtc->config->pipe_src_w > 1024 &&
   1121 		    crtc->config->gmch_pfit.control & PFIT_ENABLE) {
   1122 			overlay->pfit_active = true;
   1123 			update_pfit_vscale_ratio(overlay);
   1124 		} else
   1125 			overlay->pfit_active = false;
   1126 	}
   1127 
   1128 	ret = check_overlay_dst(overlay, params);
   1129 	if (ret != 0)
   1130 		goto out_unlock;
   1131 
   1132 	if (overlay->pfit_active) {
   1133 		params->dst_y = (((u32)params->dst_y << 12) /
   1134 				 overlay->pfit_vscale_ratio);
   1135 		/* shifting right rounds downwards, so add 1 */
   1136 		params->dst_height = (((u32)params->dst_height << 12) /
   1137 				 overlay->pfit_vscale_ratio) + 1;
   1138 	}
   1139 
   1140 	if (params->src_scan_height > params->src_height ||
   1141 	    params->src_scan_width > params->src_width) {
   1142 		ret = -EINVAL;
   1143 		goto out_unlock;
   1144 	}
   1145 
   1146 	ret = check_overlay_src(dev_priv, params, new_bo);
   1147 	if (ret != 0)
   1148 		goto out_unlock;
   1149 
   1150 	/* Check scaling after src size to prevent a divide-by-zero. */
   1151 	ret = check_overlay_scaling(params);
   1152 	if (ret != 0)
   1153 		goto out_unlock;
   1154 
   1155 	ret = intel_overlay_do_put_image(overlay, new_bo, params);
   1156 	if (ret != 0)
   1157 		goto out_unlock;
   1158 
   1159 	drm_modeset_unlock_all(dev);
   1160 	i915_gem_object_put(new_bo);
   1161 
   1162 	return 0;
   1163 
   1164 out_unlock:
   1165 	drm_modeset_unlock_all(dev);
   1166 	i915_gem_object_put(new_bo);
   1167 
   1168 	return ret;
   1169 }
   1170 
   1171 static void update_reg_attrs(struct intel_overlay *overlay,
   1172 			     struct overlay_registers __iomem *regs)
   1173 {
   1174 	iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
   1175 		  &regs->OCLRC0);
   1176 	iowrite32(overlay->saturation, &regs->OCLRC1);
   1177 }
   1178 
   1179 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
   1180 {
   1181 	int i;
   1182 
   1183 	if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
   1184 		return false;
   1185 
   1186 	for (i = 0; i < 3; i++) {
   1187 		if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
   1188 			return false;
   1189 	}
   1190 
   1191 	return true;
   1192 }
   1193 
   1194 static bool check_gamma5_errata(u32 gamma5)
   1195 {
   1196 	int i;
   1197 
   1198 	for (i = 0; i < 3; i++) {
   1199 		if (((gamma5 >> i*8) & 0xff) == 0x80)
   1200 			return false;
   1201 	}
   1202 
   1203 	return true;
   1204 }
   1205 
   1206 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
   1207 {
   1208 	if (!check_gamma_bounds(0, attrs->gamma0) ||
   1209 	    !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
   1210 	    !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
   1211 	    !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
   1212 	    !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
   1213 	    !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
   1214 	    !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
   1215 		return -EINVAL;
   1216 
   1217 	if (!check_gamma5_errata(attrs->gamma5))
   1218 		return -EINVAL;
   1219 
   1220 	return 0;
   1221 }
   1222 
   1223 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
   1224 			      struct drm_file *file_priv)
   1225 {
   1226 	struct drm_intel_overlay_attrs *attrs = data;
   1227 	struct drm_i915_private *dev_priv = to_i915(dev);
   1228 	struct intel_overlay *overlay;
   1229 	int ret;
   1230 
   1231 	overlay = dev_priv->overlay;
   1232 	if (!overlay) {
   1233 		DRM_DEBUG("userspace bug: no overlay\n");
   1234 		return -ENODEV;
   1235 	}
   1236 
   1237 	drm_modeset_lock_all(dev);
   1238 
   1239 	ret = -EINVAL;
   1240 	if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
   1241 		attrs->color_key  = overlay->color_key;
   1242 		attrs->brightness = overlay->brightness;
   1243 		attrs->contrast   = overlay->contrast;
   1244 		attrs->saturation = overlay->saturation;
   1245 
   1246 		if (!IS_GEN(dev_priv, 2)) {
   1247 			attrs->gamma0 = I915_READ(OGAMC0);
   1248 			attrs->gamma1 = I915_READ(OGAMC1);
   1249 			attrs->gamma2 = I915_READ(OGAMC2);
   1250 			attrs->gamma3 = I915_READ(OGAMC3);
   1251 			attrs->gamma4 = I915_READ(OGAMC4);
   1252 			attrs->gamma5 = I915_READ(OGAMC5);
   1253 		}
   1254 	} else {
   1255 		if (attrs->brightness < -128 || attrs->brightness > 127)
   1256 			goto out_unlock;
   1257 		if (attrs->contrast > 255)
   1258 			goto out_unlock;
   1259 		if (attrs->saturation > 1023)
   1260 			goto out_unlock;
   1261 
   1262 		overlay->color_key  = attrs->color_key;
   1263 		overlay->brightness = attrs->brightness;
   1264 		overlay->contrast   = attrs->contrast;
   1265 		overlay->saturation = attrs->saturation;
   1266 
   1267 		update_reg_attrs(overlay, overlay->regs);
   1268 
   1269 		if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
   1270 			if (IS_GEN(dev_priv, 2))
   1271 				goto out_unlock;
   1272 
   1273 			if (overlay->active) {
   1274 				ret = -EBUSY;
   1275 				goto out_unlock;
   1276 			}
   1277 
   1278 			ret = check_gamma(attrs);
   1279 			if (ret)
   1280 				goto out_unlock;
   1281 
   1282 			I915_WRITE(OGAMC0, attrs->gamma0);
   1283 			I915_WRITE(OGAMC1, attrs->gamma1);
   1284 			I915_WRITE(OGAMC2, attrs->gamma2);
   1285 			I915_WRITE(OGAMC3, attrs->gamma3);
   1286 			I915_WRITE(OGAMC4, attrs->gamma4);
   1287 			I915_WRITE(OGAMC5, attrs->gamma5);
   1288 		}
   1289 	}
   1290 	overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
   1291 
   1292 	ret = 0;
   1293 out_unlock:
   1294 	drm_modeset_unlock_all(dev);
   1295 
   1296 	return ret;
   1297 }
   1298 
   1299 static int get_registers(struct intel_overlay *overlay, bool use_phys)
   1300 {
   1301 	struct drm_i915_private *i915 = overlay->i915;
   1302 	struct drm_i915_gem_object *obj;
   1303 	struct i915_vma *vma;
   1304 	int err;
   1305 
   1306 	obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
   1307 	if (IS_ERR(obj))
   1308 		obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
   1309 	if (IS_ERR(obj))
   1310 		return PTR_ERR(obj);
   1311 
   1312 	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
   1313 	if (IS_ERR(vma)) {
   1314 		err = PTR_ERR(vma);
   1315 		goto err_put_bo;
   1316 	}
   1317 
   1318 	if (use_phys)
   1319 		overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl);
   1320 	else
   1321 		overlay->flip_addr = i915_ggtt_offset(vma);
   1322 	overlay->regs = i915_vma_pin_iomap(vma);
   1323 	i915_vma_unpin(vma);
   1324 
   1325 	if (IS_ERR(overlay->regs)) {
   1326 		err = PTR_ERR(overlay->regs);
   1327 		goto err_put_bo;
   1328 	}
   1329 
   1330 	overlay->reg_bo = obj;
   1331 	return 0;
   1332 
   1333 err_put_bo:
   1334 	i915_gem_object_put(obj);
   1335 	return err;
   1336 }
   1337 
   1338 void intel_overlay_setup(struct drm_i915_private *dev_priv)
   1339 {
   1340 	struct intel_overlay *overlay;
   1341 	struct intel_engine_cs *engine;
   1342 	int ret;
   1343 
   1344 	if (!HAS_OVERLAY(dev_priv))
   1345 		return;
   1346 
   1347 	engine = dev_priv->engine[RCS0];
   1348 	if (!engine || !engine->kernel_context)
   1349 		return;
   1350 
   1351 	overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
   1352 	if (!overlay)
   1353 		return;
   1354 
   1355 	overlay->i915 = dev_priv;
   1356 	overlay->context = engine->kernel_context;
   1357 	GEM_BUG_ON(!overlay->context);
   1358 
   1359 	overlay->color_key = 0x0101fe;
   1360 	overlay->color_key_enabled = true;
   1361 	overlay->brightness = -19;
   1362 	overlay->contrast = 75;
   1363 	overlay->saturation = 146;
   1364 
   1365 	i915_active_init(&overlay->last_flip,
   1366 			 NULL, intel_overlay_last_flip_retire);
   1367 
   1368 	ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv));
   1369 	if (ret)
   1370 		goto out_free;
   1371 
   1372 	memset_io(overlay->regs, 0, sizeof(struct overlay_registers));
   1373 	update_polyphase_filter(overlay->regs);
   1374 	update_reg_attrs(overlay, overlay->regs);
   1375 
   1376 	dev_priv->overlay = overlay;
   1377 	DRM_INFO("Initialized overlay support.\n");
   1378 	return;
   1379 
   1380 out_free:
   1381 	kfree(overlay);
   1382 }
   1383 
   1384 void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
   1385 {
   1386 	struct intel_overlay *overlay;
   1387 
   1388 	overlay = fetch_and_zero(&dev_priv->overlay);
   1389 	if (!overlay)
   1390 		return;
   1391 
   1392 	/*
   1393 	 * The bo's should be free'd by the generic code already.
   1394 	 * Furthermore modesetting teardown happens beforehand so the
   1395 	 * hardware should be off already.
   1396 	 */
   1397 	WARN_ON(overlay->active);
   1398 
   1399 	i915_gem_object_put(overlay->reg_bo);
   1400 	i915_active_fini(&overlay->last_flip);
   1401 
   1402 	kfree(overlay);
   1403 }
   1404 
   1405 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
   1406 
   1407 struct intel_overlay_error_state {
   1408 	struct overlay_registers regs;
   1409 	unsigned long base;
   1410 	u32 dovsta;
   1411 	u32 isr;
   1412 };
   1413 
   1414 struct intel_overlay_error_state *
   1415 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
   1416 {
   1417 	struct intel_overlay *overlay = dev_priv->overlay;
   1418 	struct intel_overlay_error_state *error;
   1419 
   1420 	if (!overlay || !overlay->active)
   1421 		return NULL;
   1422 
   1423 	error = kmalloc(sizeof(*error), GFP_ATOMIC);
   1424 	if (error == NULL)
   1425 		return NULL;
   1426 
   1427 	error->dovsta = I915_READ(DOVSTA);
   1428 	error->isr = I915_READ(GEN2_ISR);
   1429 	error->base = overlay->flip_addr;
   1430 
   1431 	memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));
   1432 
   1433 	return error;
   1434 }
   1435 
   1436 void
   1437 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
   1438 				struct intel_overlay_error_state *error)
   1439 {
   1440 	i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
   1441 			  error->dovsta, error->isr);
   1442 	i915_error_printf(m, "  Register file at 0x%08lx:\n",
   1443 			  error->base);
   1444 
   1445 #define P(x) i915_error_printf(m, "    " #x ":	0x%08x\n", error->regs.x)
   1446 	P(OBUF_0Y);
   1447 	P(OBUF_1Y);
   1448 	P(OBUF_0U);
   1449 	P(OBUF_0V);
   1450 	P(OBUF_1U);
   1451 	P(OBUF_1V);
   1452 	P(OSTRIDE);
   1453 	P(YRGB_VPH);
   1454 	P(UV_VPH);
   1455 	P(HORZ_PH);
   1456 	P(INIT_PHS);
   1457 	P(DWINPOS);
   1458 	P(DWINSZ);
   1459 	P(SWIDTH);
   1460 	P(SWIDTHSW);
   1461 	P(SHEIGHT);
   1462 	P(YRGBSCALE);
   1463 	P(UVSCALE);
   1464 	P(OCLRC0);
   1465 	P(OCLRC1);
   1466 	P(DCLRKV);
   1467 	P(DCLRKM);
   1468 	P(SCLRKVH);
   1469 	P(SCLRKVL);
   1470 	P(SCLRKEN);
   1471 	P(OCONFIG);
   1472 	P(OCMD);
   1473 	P(OSTART_0Y);
   1474 	P(OSTART_1Y);
   1475 	P(OSTART_0U);
   1476 	P(OSTART_0V);
   1477 	P(OSTART_1U);
   1478 	P(OSTART_1V);
   1479 	P(OTILEOFF_0Y);
   1480 	P(OTILEOFF_1Y);
   1481 	P(OTILEOFF_0U);
   1482 	P(OTILEOFF_0V);
   1483 	P(OTILEOFF_1U);
   1484 	P(OTILEOFF_1V);
   1485 	P(FASTHSCALE);
   1486 	P(UVSCALEV);
   1487 #undef P
   1488 }
   1489 
   1490 #endif
   1491